bus_machdep.c revision 104486
1/*- 2 * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 7 * NASA Ames Research Center. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of The NetBSD Foundation nor the names of its 22 * contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37/* 38 * Copyright (c) 1992, 1993 39 * The Regents of the University of California. All rights reserved. 40 * 41 * This software was developed by the Computer Systems Engineering group 42 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 43 * contributed to Berkeley. 44 * 45 * All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by the University of 48 * California, Lawrence Berkeley Laboratory. 49 * 50 * Redistribution and use in source and binary forms, with or without 51 * modification, are permitted provided that the following conditions 52 * are met: 53 * 1. Redistributions of source code must retain the above copyright 54 * notice, this list of conditions and the following disclaimer. 55 * 2. Redistributions in binary form must reproduce the above copyright 56 * notice, this list of conditions and the following disclaimer in the 57 * documentation and/or other materials provided with the distribution. 58 * 3. All advertising materials mentioning features or use of this software 59 * must display the following acknowledgement: 60 * This product includes software developed by the University of 61 * California, Berkeley and its contributors. 62 * 4. Neither the name of the University nor the names of its contributors 63 * may be used to endorse or promote products derived from this software 64 * without specific prior written permission. 65 * 66 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 67 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 69 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 72 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 73 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 74 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 75 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 76 * SUCH DAMAGE. 77 */ 78/* 79 * Copyright (c) 1997, 1998 Justin T. Gibbs. 80 * All rights reserved. 81 * Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>. All rights reserved. 82 * 83 * Redistribution and use in source and binary forms, with or without 84 * modification, are permitted provided that the following conditions 85 * are met: 86 * 1. Redistributions of source code must retain the above copyright 87 * notice, this list of conditions, and the following disclaimer, 88 * without modification, immediately at the beginning of the file. 89 * 2. The name of the author may not be used to endorse or promote products 90 * derived from this software without specific prior written permission. 91 * 92 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 93 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 94 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 95 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 96 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 97 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 98 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 99 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 100 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 101 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 102 * SUCH DAMAGE. 103 * 104 * from: @(#)machdep.c 8.6 (Berkeley) 1/14/94 105 * from: NetBSD: machdep.c,v 1.111 2001/09/15 07:13:40 eeh Exp 106 * and 107 * from: FreeBSD: src/sys/i386/i386/busdma_machdep.c,v 1.24 2001/08/15 108 * 109 * $FreeBSD: head/sys/sparc64/sparc64/bus_machdep.c 104486 2002-10-04 20:40:39Z sam $ 110 */ 111 112#include <sys/param.h> 113#include <sys/bus.h> 114#include <sys/malloc.h> 115#include <sys/mbuf.h> 116#include <sys/proc.h> 117#include <sys/smp.h> 118#include <sys/systm.h> 119#include <sys/uio.h> 120 121#include <vm/vm.h> 122#include <vm/vm_extern.h> 123#include <vm/vm_kern.h> 124#include <vm/vm_page.h> 125#include <vm/vm_param.h> 126#include <vm/vm_map.h> 127 128#include <machine/asi.h> 129#include <machine/bus.h> 130#include <machine/bus_private.h> 131#include <machine/cache.h> 132#include <machine/pmap.h> 133#include <machine/smp.h> 134#include <machine/tlb.h> 135 136/* ASI's for bus access. */ 137int bus_type_asi[] = { 138 ASI_PHYS_BYPASS_EC_WITH_EBIT, /* UPA */ 139 ASI_PHYS_BYPASS_EC_WITH_EBIT, /* SBUS */ 140 ASI_PHYS_BYPASS_EC_WITH_EBIT_L, /* PCI configuration space */ 141 ASI_PHYS_BYPASS_EC_WITH_EBIT_L, /* PCI memory space */ 142 ASI_PHYS_BYPASS_EC_WITH_EBIT_L, /* PCI I/O space */ 143 0 144}; 145 146int bus_stream_asi[] = { 147 ASI_PHYS_BYPASS_EC_WITH_EBIT, /* UPA */ 148 ASI_PHYS_BYPASS_EC_WITH_EBIT, /* SBUS */ 149 ASI_PHYS_BYPASS_EC_WITH_EBIT, /* PCI configuration space */ 150 ASI_PHYS_BYPASS_EC_WITH_EBIT, /* PCI memory space */ 151 ASI_PHYS_BYPASS_EC_WITH_EBIT, /* PCI I/O space */ 152 0 153}; 154 155/* 156 * busdma support code. 157 * Note: there is no support for bounce buffers yet. 158 */ 159 160static int nexus_dmamap_create(bus_dma_tag_t, bus_dma_tag_t, int, 161 bus_dmamap_t *); 162static int nexus_dmamap_destroy(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 163static int nexus_dmamap_load(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 164 void *, bus_size_t, bus_dmamap_callback_t *, void *, int); 165static int nexus_dmamap_load_mbuf(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 166 struct mbuf *, bus_dmamap_callback2_t *, void *, int); 167static int nexus_dmamap_load_uio(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 168 struct uio *, bus_dmamap_callback2_t *, void *, int); 169static void nexus_dmamap_unload(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 170static void nexus_dmamap_sync(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 171 bus_dmasync_op_t); 172static int nexus_dmamem_alloc(bus_dma_tag_t, bus_dma_tag_t, void **, int, 173 bus_dmamap_t *); 174static void nexus_dmamem_free(bus_dma_tag_t, bus_dma_tag_t, void *, 175 bus_dmamap_t); 176 177/* 178 * Since there is now way for a device to obtain a dma tag from its parent 179 * we use this kluge to handle different the different supported bus systems. 180 * The sparc64_root_dma_tag is used as parent for tags that have none, so that 181 * the correct methods will be used. 182 */ 183bus_dma_tag_t sparc64_root_dma_tag; 184 185/* 186 * Allocate a device specific dma_tag. 187 */ 188int 189bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignment, 190 bus_size_t boundary, bus_addr_t lowaddr, bus_addr_t highaddr, 191 bus_dma_filter_t *filter, void *filterarg, bus_size_t maxsize, 192 int nsegments, bus_size_t maxsegsz, int flags, bus_dma_tag_t *dmat) 193{ 194 195 bus_dma_tag_t newtag; 196 197 /* Return a NULL tag on failure */ 198 *dmat = NULL; 199 200 newtag = (bus_dma_tag_t)malloc(sizeof(*newtag), M_DEVBUF, M_NOWAIT); 201 if (newtag == NULL) 202 return (ENOMEM); 203 204 newtag->parent = parent != NULL ? parent : sparc64_root_dma_tag; 205 newtag->alignment = alignment; 206 newtag->boundary = boundary; 207 newtag->lowaddr = trunc_page((vm_offset_t)lowaddr) + (PAGE_SIZE - 1); 208 newtag->highaddr = trunc_page((vm_offset_t)highaddr) + (PAGE_SIZE - 1); 209 newtag->filter = filter; 210 newtag->filterarg = filterarg; 211 newtag->maxsize = maxsize; 212 newtag->nsegments = nsegments; 213 newtag->maxsegsz = maxsegsz; 214 newtag->flags = flags; 215 newtag->ref_count = 1; /* Count ourselves */ 216 newtag->map_count = 0; 217 218 newtag->dmamap_create = NULL; 219 newtag->dmamap_destroy = NULL; 220 newtag->dmamap_load = NULL; 221 newtag->dmamap_load_mbuf = NULL; 222 newtag->dmamap_load_uio = NULL; 223 newtag->dmamap_unload = NULL; 224 newtag->dmamap_sync = NULL; 225 newtag->dmamem_alloc = NULL; 226 newtag->dmamem_free = NULL; 227 228 /* Take into account any restrictions imposed by our parent tag */ 229 if (parent != NULL) { 230 newtag->lowaddr = ulmin(parent->lowaddr, newtag->lowaddr); 231 newtag->highaddr = ulmax(parent->highaddr, newtag->highaddr); 232 /* 233 * XXX Not really correct??? Probably need to honor boundary 234 * all the way up the inheritence chain. 235 */ 236 newtag->boundary = ulmax(parent->boundary, newtag->boundary); 237 } 238 newtag->parent->ref_count++; 239 240 *dmat = newtag; 241 return (0); 242} 243 244int 245bus_dma_tag_destroy(bus_dma_tag_t dmat) 246{ 247 bus_dma_tag_t parent; 248 249 if (dmat != NULL) { 250 if (dmat->map_count != 0) 251 return (EBUSY); 252 while (dmat != NULL) { 253 parent = dmat->parent; 254 dmat->ref_count--; 255 if (dmat->ref_count == 0) { 256 free(dmat, M_DEVBUF); 257 /* 258 * Last reference count, so 259 * release our reference 260 * count on our parent. 261 */ 262 dmat = parent; 263 } else 264 dmat = NULL; 265 } 266 } 267 return (0); 268} 269 270/* 271 * Common function for DMA map creation. May be called by bus-specific 272 * DMA map creation functions. 273 */ 274static int 275nexus_dmamap_create(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, int flags, 276 bus_dmamap_t *mapp) 277{ 278 279 /* Not much to do...? */ 280 *mapp = malloc(sizeof(**mapp), M_DEVBUF, M_NOWAIT | M_ZERO); 281 if (*mapp != NULL) { 282 ddmat->map_count++; 283 return (0); 284 } else 285 return (ENOMEM); 286} 287 288/* 289 * Common function for DMA map destruction. May be called by bus-specific 290 * DMA map destruction functions. 291 */ 292static int 293nexus_dmamap_destroy(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map) 294{ 295 296 free(map, M_DEVBUF); 297 ddmat->map_count--; 298 return (0); 299} 300 301#define BUS_DMAMAP_NSEGS ((BUS_SPACE_MAXSIZE / PAGE_SIZE) + 1) 302 303/* 304 * Common function for loading a DMA map with a linear buffer. May 305 * be called by bus-specific DMA map load functions. 306 * 307 * Most SPARCs have IOMMUs in the bus controllers. In those cases 308 * they only need one segment and will use virtual addresses for DVMA. 309 * Those bus controllers should intercept these vectors and should 310 * *NEVER* call nexus_dmamap_load() which is used only by devices that 311 * bypass DVMA. 312 */ 313static int 314nexus_dmamap_load(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map, 315 void *buf, bus_size_t buflen, bus_dmamap_callback_t *callback, 316 void *callback_arg, int flags) 317{ 318 vm_offset_t vaddr; 319 vm_offset_t paddr; 320#ifdef __GNUC__ 321 bus_dma_segment_t dm_segments[ddmat->nsegments]; 322#else 323 bus_dma_segment_t dm_segments[BUS_DMAMAP_NSEGS]; 324#endif 325 bus_dma_segment_t *sg; 326 int seg; 327 int error; 328 vm_offset_t nextpaddr; 329 bus_size_t size; 330 331 error = 0; 332 333 vaddr = (vm_offset_t)buf; 334 sg = &dm_segments[0]; 335 seg = 1; 336 sg->ds_len = 0; 337 338 map->buf = buf; 339 map->buflen = buflen; 340 map->start = (bus_addr_t)buf; 341 342 nextpaddr = 0; 343 do { 344 paddr = pmap_kextract(vaddr); 345 size = PAGE_SIZE - (paddr & PAGE_MASK); 346 if (size > buflen) 347 size = buflen; 348 349 if (sg->ds_len == 0) { 350 sg->ds_addr = paddr; 351 sg->ds_len = size; 352 } else if (paddr == nextpaddr) { 353 sg->ds_len += size; 354 } else { 355 /* Go to the next segment */ 356 sg++; 357 seg++; 358 if (seg > ddmat->nsegments) 359 break; 360 sg->ds_addr = paddr; 361 sg->ds_len = size; 362 } 363 vaddr += size; 364 nextpaddr = paddr + size; 365 buflen -= size; 366 } while (buflen > 0); 367 368 if (buflen != 0) { 369 printf("bus_dmamap_load: Too many segs! buf_len = 0x%lx\n", 370 (u_long)buflen); 371 error = EFBIG; 372 } 373 374 (*callback)(callback_arg, dm_segments, seg, error); 375 376 return (0); 377} 378 379/* 380 * Utility function to load a linear buffer. lastaddrp holds state 381 * between invocations (for multiple-buffer loads). segp contains 382 * the starting segment on entrace, and the ending segment on exit. 383 * first indicates if this is the first invocation of this function. 384 */ 385static int 386_nexus_dmamap_load_buffer(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, 387 bus_dma_segment_t segs[], 388 void *buf, bus_size_t buflen, 389 struct thread *td, 390 int flags, 391 vm_offset_t *lastaddrp, 392 int *segp, 393 int first) 394{ 395 bus_size_t sgsize; 396 bus_addr_t curaddr, lastaddr, baddr, bmask; 397 vm_offset_t vaddr = (vm_offset_t)buf; 398 int seg; 399 pmap_t pmap; 400 401 if (td != NULL) 402 pmap = vmspace_pmap(td->td_proc->p_vmspace); 403 else 404 pmap = NULL; 405 406 lastaddr = *lastaddrp; 407 bmask = ~(ddmat->boundary - 1); 408 409 for (seg = *segp; buflen > 0 ; ) { 410 /* 411 * Get the physical address for this segment. 412 */ 413 if (pmap) 414 curaddr = pmap_extract(pmap, vaddr); 415 else 416 curaddr = pmap_kextract(vaddr); 417 418 /* 419 * Compute the segment size, and adjust counts. 420 */ 421 sgsize = PAGE_SIZE - ((u_long)curaddr & PAGE_MASK); 422 if (buflen < sgsize) 423 sgsize = buflen; 424 425 /* 426 * Make sure we don't cross any boundaries. 427 */ 428 if (ddmat->boundary > 0) { 429 baddr = (curaddr + ddmat->boundary) & bmask; 430 if (sgsize > (baddr - curaddr)) 431 sgsize = (baddr - curaddr); 432 } 433 434 /* 435 * Insert chunk into a segment, coalescing with 436 * previous segment if possible. 437 */ 438 if (first) { 439 segs[seg].ds_addr = curaddr; 440 segs[seg].ds_len = sgsize; 441 first = 0; 442 } else { 443 if (curaddr == lastaddr && 444 (segs[seg].ds_len + sgsize) <= ddmat->maxsegsz && 445 (ddmat->boundary == 0 || 446 (segs[seg].ds_addr & bmask) == (curaddr & bmask))) 447 segs[seg].ds_len += sgsize; 448 else { 449 if (++seg >= ddmat->nsegments) 450 break; 451 segs[seg].ds_addr = curaddr; 452 segs[seg].ds_len = sgsize; 453 } 454 } 455 456 lastaddr = curaddr + sgsize; 457 vaddr += sgsize; 458 buflen -= sgsize; 459 } 460 461 *segp = seg; 462 *lastaddrp = lastaddr; 463 464 /* 465 * Did we fit? 466 */ 467 return (buflen != 0 ? EFBIG : 0); /* XXX better return value here? */ 468} 469 470/* 471 * Like _bus_dmamap_load(), but for mbufs. 472 */ 473static int 474nexus_dmamap_load_mbuf(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, 475 bus_dmamap_t map, 476 struct mbuf *m0, 477 bus_dmamap_callback2_t *callback, void *callback_arg, 478 int flags) 479{ 480#ifdef __GNUC__ 481 bus_dma_segment_t dm_segments[ddmat->nsegments]; 482#else 483 bus_dma_segment_t dm_segments[BUS_DMAMAP_NSEGS]; 484#endif 485 int nsegs, error; 486 487 KASSERT(m0->m_flags & M_PKTHDR, 488 ("nexus_dmamap_load_mbuf: no packet header")); 489 490 nsegs = 0; 491 error = 0; 492 if (m0->m_pkthdr.len <= ddmat->maxsize) { 493 int first = 1; 494 vm_offset_t lastaddr = 0; 495 struct mbuf *m; 496 497 for (m = m0; m != NULL && error == 0; m = m->m_next) { 498 error = _nexus_dmamap_load_buffer(pdmat, ddmat, 499 dm_segments, 500 m->m_data, m->m_len, 501 NULL, flags, &lastaddr, &nsegs, first); 502 first = 0; 503 } 504 } else { 505 error = EINVAL; 506 } 507 508 if (error) { 509 /* force "no valid mappings" in callback */ 510 (*callback)(callback_arg, dm_segments, 0, 0, error); 511 } else { 512 (*callback)(callback_arg, dm_segments, 513 nsegs+1, m0->m_pkthdr.len, error); 514 } 515 return (error); 516} 517 518/* 519 * Like _bus_dmamap_load(), but for uios. 520 */ 521static int 522nexus_dmamap_load_uio(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, 523 bus_dmamap_t map, 524 struct uio *uio, 525 bus_dmamap_callback2_t *callback, void *callback_arg, 526 int flags) 527{ 528 vm_offset_t lastaddr; 529#ifdef __GNUC__ 530 bus_dma_segment_t dm_segments[ddmat->nsegments]; 531#else 532 bus_dma_segment_t dm_segments[BUS_DMAMAP_NSEGS]; 533#endif 534 int nsegs, error, first, i; 535 bus_size_t resid; 536 struct iovec *iov; 537 struct thread *td = NULL; 538 539 resid = uio->uio_resid; 540 iov = uio->uio_iov; 541 542 if (uio->uio_segflg == UIO_USERSPACE) { 543 td = uio->uio_td; 544 KASSERT(td != NULL, 545 ("nexus_dmamap_load_uio: USERSPACE but no proc")); 546 } 547 548 nsegs = 0; 549 error = 0; 550 first = 1; 551 for (i = 0; i < uio->uio_iovcnt && resid != 0 && !error; i++) { 552 /* 553 * Now at the first iovec to load. Load each iovec 554 * until we have exhausted the residual count. 555 */ 556 bus_size_t minlen = 557 resid < iov[i].iov_len ? resid : iov[i].iov_len; 558 caddr_t addr = (caddr_t) iov[i].iov_base; 559 560 error = _nexus_dmamap_load_buffer(pdmat, ddmat, 561 dm_segments, 562 addr, minlen, 563 td, flags, &lastaddr, &nsegs, first); 564 first = 0; 565 566 resid -= minlen; 567 } 568 569 if (error) { 570 /* force "no valid mappings" in callback */ 571 (*callback)(callback_arg, dm_segments, 0, 0, error); 572 } else { 573 (*callback)(callback_arg, dm_segments, 574 nsegs+1, uio->uio_resid, error); 575 } 576 return (error); 577} 578 579/* 580 * Common function for unloading a DMA map. May be called by 581 * bus-specific DMA map unload functions. 582 */ 583static void 584nexus_dmamap_unload(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map) 585{ 586 587 /* Nothing to do...? */ 588} 589 590/* 591 * Common function for DMA map synchronization. May be called 592 * by bus-specific DMA map synchronization functions. 593 */ 594static void 595nexus_dmamap_sync(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map, 596 bus_dmasync_op_t op) 597{ 598 599 /* 600 * We sync out our caches, but the bus must do the same. 601 * 602 * Actually a #Sync is expensive. We should optimize. 603 */ 604 if ((op == BUS_DMASYNC_PREREAD) || (op == BUS_DMASYNC_PREWRITE)) { 605 /* 606 * Don't really need to do anything, but flush any pending 607 * writes anyway. 608 */ 609 membar(Sync); 610 } 611 if (op == BUS_DMASYNC_POSTREAD) { 612 /* 613 * Invalidate the caches (it is unclear whether that is really 614 * needed. The manual only mentions that PCI transactions are 615 * cache coherent). 616 */ 617 ecache_flush((vm_offset_t)map->buf, 618 (vm_offset_t)map->buf + map->buflen - 1); 619 } 620 if (op == BUS_DMASYNC_POSTWRITE) { 621 /* Nothing to do. Handled by the bus controller. */ 622 } 623} 624 625/* 626 * Helper functions for buses that use their private dmamem_alloc/dmamem_free 627 * versions. 628 * These differ from the dmamap_alloc() functions in that they create a tag 629 * that is specifically for use with dmamem_alloc'ed memory. 630 * These are primitive now, but I expect that some fields of the map will need 631 * to be filled soon. 632 */ 633int 634sparc64_dmamem_alloc_map(bus_dma_tag_t dmat, bus_dmamap_t *mapp) 635{ 636 637 *mapp = malloc(sizeof(**mapp), M_DEVBUF, M_NOWAIT | M_ZERO); 638 if (*mapp == NULL) 639 return (ENOMEM); 640 641 dmat->map_count++; 642 return (0); 643} 644 645void 646sparc64_dmamem_free_map(bus_dma_tag_t dmat, bus_dmamap_t map) 647{ 648 649 free(map, M_DEVBUF); 650 dmat->map_count--; 651} 652 653/* 654 * Common function for DMA-safe memory allocation. May be called 655 * by bus-specific DMA memory allocation functions. 656 */ 657static int 658nexus_dmamem_alloc(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void **vaddr, 659 int flags, bus_dmamap_t *mapp) 660{ 661 662 if ((ddmat->maxsize <= PAGE_SIZE)) { 663 *vaddr = malloc(ddmat->maxsize, M_DEVBUF, 664 (flags & BUS_DMA_NOWAIT) ? M_NOWAIT : M_WAITOK); 665 } else { 666 /* 667 * XXX: Use contigmalloc until it is merged into this facility 668 * and handles multi-seg allocations. Nobody is doing multi-seg 669 * allocations yet though. 670 */ 671 *vaddr = contigmalloc(ddmat->maxsize, M_DEVBUF, 672 (flags & BUS_DMA_NOWAIT) ? M_NOWAIT : M_WAITOK, 673 0ul, ddmat->lowaddr, 674 ddmat->alignment ? ddmat->alignment : 1UL, 675 ddmat->boundary); 676 } 677 if (*vaddr == NULL) { 678 free(*mapp, M_DEVBUF); 679 return (ENOMEM); 680 } 681 return (0); 682} 683 684/* 685 * Common function for freeing DMA-safe memory. May be called by 686 * bus-specific DMA memory free functions. 687 */ 688static void 689nexus_dmamem_free(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void *vaddr, 690 bus_dmamap_t map) 691{ 692 693 sparc64_dmamem_free_map(ddmat, map); 694 if ((ddmat->maxsize <= PAGE_SIZE)) 695 free(vaddr, M_DEVBUF); 696 else 697 contigfree(vaddr, ddmat->maxsize, M_DEVBUF); 698} 699 700struct bus_dma_tag nexus_dmatag = { 701 NULL, 702 NULL, 703 8, 704 0, 705 0, 706 0x3ffffffff, 707 NULL, /* XXX */ 708 NULL, 709 0x3ffffffff, /* XXX */ 710 0xff, /* XXX */ 711 0xffffffff, /* XXX */ 712 0, 713 0, 714 0, 715 nexus_dmamap_create, 716 nexus_dmamap_destroy, 717 nexus_dmamap_load, 718 nexus_dmamap_load_mbuf, 719 nexus_dmamap_load_uio, 720 nexus_dmamap_unload, 721 nexus_dmamap_sync, 722 723 nexus_dmamem_alloc, 724 nexus_dmamem_free, 725}; 726 727/* 728 * Helpers to map/unmap bus memory 729 */ 730int 731sparc64_bus_mem_map(bus_space_tag_t tag, bus_space_handle_t handle, 732 bus_size_t size, int flags, vm_offset_t vaddr, void **hp) 733{ 734 vm_offset_t addr; 735 vm_offset_t sva; 736 vm_offset_t va; 737 vm_offset_t pa; 738 vm_size_t vsz; 739 u_long pm_flags; 740 741 addr = (vm_offset_t)handle; 742 size = round_page(size); 743 if (size == 0) { 744 printf("sparc64_bus_map: zero size\n"); 745 return (EINVAL); 746 } 747 switch (tag->type) { 748 case PCI_CONFIG_BUS_SPACE: 749 case PCI_IO_BUS_SPACE: 750 case PCI_MEMORY_BUS_SPACE: 751 pm_flags = TD_IE; 752 break; 753 default: 754 pm_flags = 0; 755 break; 756 } 757 758 if (!(flags & BUS_SPACE_MAP_CACHEABLE)) 759 pm_flags |= TD_E; 760 761 if (vaddr != NULL) 762 sva = trunc_page(vaddr); 763 else { 764 if ((sva = kmem_alloc_nofault(kernel_map, size)) == NULL) 765 panic("sparc64_bus_map: cannot allocate virtual " 766 "memory"); 767 } 768 769 /* note: preserve page offset */ 770 *hp = (void *)(sva | ((u_long)addr & PAGE_MASK)); 771 772 pa = trunc_page(addr); 773 if ((flags & BUS_SPACE_MAP_READONLY) == 0) 774 pm_flags |= TD_W; 775 776 va = sva; 777 vsz = size; 778 do { 779 pmap_kenter_flags(va, pa, pm_flags); 780 va += PAGE_SIZE; 781 pa += PAGE_SIZE; 782 } while ((vsz -= PAGE_SIZE) > 0); 783 tlb_range_demap(kernel_pmap, sva, sva + size - 1); 784 return (0); 785} 786 787int 788sparc64_bus_mem_unmap(void *bh, bus_size_t size) 789{ 790 vm_offset_t sva; 791 vm_offset_t va; 792 vm_offset_t endva; 793 794 sva = trunc_page((vm_offset_t)bh); 795 endva = sva + round_page(size); 796 for (va = sva; va < endva; va += PAGE_SIZE) 797 pmap_kremove_flags(va); 798 tlb_range_demap(kernel_pmap, sva, sva + size - 1); 799 kmem_free(kernel_map, sva, size); 800 return (0); 801} 802 803/* 804 * Fake up a bus tag, for use by console drivers in early boot when the regular 805 * means to allocate resources are not yet available. 806 * Note that these tags are not eligible for bus_space_barrier operations. 807 * Addr is the physical address of the desired start of the handle. 808 */ 809bus_space_handle_t 810sparc64_fake_bustag(int space, bus_addr_t addr, struct bus_space_tag *ptag) 811{ 812 813 ptag->cookie = NULL; 814 ptag->parent = NULL; 815 ptag->type = space; 816 ptag->bus_barrier = NULL; 817 return (addr); 818} 819 820/* 821 * Base bus space handlers. 822 */ 823static void nexus_bus_barrier(bus_space_tag_t, bus_space_handle_t, 824 bus_size_t, bus_size_t, int); 825 826static void 827nexus_bus_barrier(bus_space_tag_t t, bus_space_handle_t h, bus_size_t offset, 828 bus_size_t size, int flags) 829{ 830 831 /* 832 * We have lots of alternatives depending on whether we're 833 * synchronizing loads with loads, loads with stores, stores 834 * with loads, or stores with stores. The only ones that seem 835 * generic are #Sync and #MemIssue. I'll use #Sync for safety. 836 */ 837 switch(flags) { 838 case BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE: 839 case BUS_SPACE_BARRIER_READ: 840 case BUS_SPACE_BARRIER_WRITE: 841 membar(Sync); 842 break; 843 default: 844 panic("sparc64_bus_barrier: unknown flags"); 845 } 846 return; 847} 848 849struct bus_space_tag nexus_bustag = { 850 NULL, /* cookie */ 851 NULL, /* parent bus tag */ 852 UPA_BUS_SPACE, /* type */ 853 nexus_bus_barrier, /* bus_space_barrier */ 854}; 855