1139825Simp/*- 290618Stmm * Copyright (c) 1996-1999 Eduardo Horvath 390618Stmm * 490618Stmm * Redistribution and use in source and binary forms, with or without 590618Stmm * modification, are permitted provided that the following conditions 690618Stmm * are met: 790618Stmm * 1. Redistributions of source code must retain the above copyright 890618Stmm * notice, this list of conditions and the following disclaimer. 990618Stmm * 1090618Stmm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 1190618Stmm * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1290618Stmm * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1390618Stmm * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 1490618Stmm * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1590618Stmm * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 1690618Stmm * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 1790618Stmm * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 1890618Stmm * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 1990618Stmm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2090618Stmm * SUCH DAMAGE. 2190618Stmm * 2290618Stmm * from: NetBSD: sbusreg.h,v 1.7 1999/06/07 05:28:03 eeh Exp 2390618Stmm * 2490618Stmm * $FreeBSD$ 2590618Stmm */ 2690618Stmm 2790618Stmm#ifndef _SPARC64_SBUS_SBUSREG_H_ 2890618Stmm#define _SPARC64_SBUS_SBUSREG_H_ 2990618Stmm 3090618Stmm/* 3190618Stmm * Sbus device addresses are obtained from the FORTH PROMs. They come 3290618Stmm * in `absolute' and `relative' address flavors, so we have to handle both. 3390618Stmm * Relative addresses do *not* include the slot number. 3490618Stmm */ 3590618Stmm#define SBUS_BASE 0xf8000000 3690618Stmm#define SBUS_ADDR(slot, off) (SBUS_BASE + ((slot) << 25) + (off)) 3790618Stmm#define SBUS_ABS(a) ((unsigned)(a) >= SBUS_BASE) 3890618Stmm#define SBUS_ABS_TO_SLOT(a) (((a) - SBUS_BASE) >> 25) 3990618Stmm#define SBUS_ABS_TO_OFFSET(a) (((a) - SBUS_BASE) & 0x1ffffff) 4090618Stmm 4190618Stmm/* 4290618Stmm * Sun4u S-bus definitions. Here's where we deal w/the machine 4390618Stmm * dependencies of sysio. 4490618Stmm * 4590618Stmm * SYSIO implements or is the interface to several things: 4690618Stmm * 4790618Stmm * o The SBUS interface itself 4890618Stmm * o The IOMMU 4990618Stmm * o The DVMA units 5090618Stmm * o The interrupt controller 5190618Stmm * o The counter/timers 5290618Stmm * 5390618Stmm * Since it has registers to control lots of different things 5490618Stmm * as well as several on-board SBUS devices and external SBUS 5590618Stmm * slots scattered throughout its address space, it's a pain. 5690618Stmm * 5790618Stmm * One good point, however, is that all registers are 64-bit. 5890618Stmm */ 5990618Stmm#define SBR_UPA_PORTID 0x0000 /* UPA port ID register */ 6090618Stmm#define SBR_UPA_CONFIG 0x0008 /* UPA config register */ 6190618Stmm#define SBR_CS 0x0010 /* SYSIO control/status register */ 6290618Stmm#define SBR_ECCC 0x0020 /* ECC control register */ 6390618Stmm#define SBR_UE_AFS 0x0030 /* Uncorrectable Error AFSR */ 6490618Stmm#define SBR_UE_AFA 0x0038 /* Uncorrectable Error AFAR */ 6590618Stmm#define SBR_CE_AFS 0x0040 /* Correctable Error AFSR */ 6690618Stmm#define SBR_CE_AFA 0x0048 /* Correctable Error AFAR */ 6790618Stmm#define SBR_PM_CTL 0x0100 /* Performance monitor control reg */ 6890618Stmm#define SBR_PM_COUNT 0x0108 /* Performance monitor counter reg */ 6990618Stmm#define SBR_CTL 0x2000 /* SBUS Control Register */ 7090618Stmm#define SBR_AFS 0x2010 /* SBUS AFSR */ 7190618Stmm#define SBR_AFA 0x2018 /* SBUS AFAR */ 7290618Stmm#define SBR_CONFIG0 0x2020 /* SBUS Slot 0 config register */ 7390618Stmm#define SBR_CONFIG1 0x2028 /* SBUS Slot 1 config register */ 7490618Stmm#define SBR_CONFIG2 0x2030 /* SBUS Slot 2 config register */ 7590618Stmm#define SBR_CONFIG3 0x2038 /* SBUS Slot 3 config register */ 7690618Stmm#define SBR_CONFIG13 0x2040 /* Slot 13 config register <audio> */ 7790618Stmm#define SBR_CONFIG14 0x2048 /* Slot 14 config register <macio> */ 7890618Stmm#define SBR_CONFIG15 0x2050 /* Slot 15 config register <slavio> */ 7990618Stmm#define SBR_IOMMU 0x2400 /* IOMMU register block */ 8090618Stmm#define SBR_STRBUF 0x2800 /* stream buffer register block */ 8190618Stmm#define SBR_SLOT0_INT_MAP 0x2c00 /* SBUS slot 0 interrupt map reg */ 8290618Stmm#define SBR_SLOT1_INT_MAP 0x2c08 /* SBUS slot 1 interrupt map reg */ 8390618Stmm#define SBR_SLOT2_INT_MAP 0x2c10 /* SBUS slot 2 interrupt map reg */ 8490618Stmm#define SBR_SLOT3_INT_MAP 0x2c18 /* SBUS slot 3 interrupt map reg */ 8590618Stmm#define SBR_INTR_RETRY_TIM 0x2c20 /* interrupt retry timer reg */ 8690618Stmm#define SBR_SCSI_INT_MAP 0x3000 /* SCSI interrupt map reg */ 8790618Stmm#define SBR_ETHER_INT_MAP 0x3008 /* ethernet interrupt map reg */ 8890618Stmm#define SBR_BPP_INT_MAP 0x3010 /* parallel interrupt map reg */ 8990618Stmm#define SBR_AUDIO_INT_MAP 0x3018 /* audio interrupt map reg */ 9090618Stmm#define SBR_POWER_INT_MAP 0x3020 /* power fail interrupt map reg */ 9190618Stmm#define SBR_SKBDMS_INT_MAP 0x3028 /* serial/kbd/mouse interrupt map reg */ 9290618Stmm#define SBR_FD_INT_MAP 0x3030 /* floppy interrupt map reg */ 9390618Stmm#define SBR_THERM_INT_MAP 0x3038 /* thermal warn interrupt map reg */ 9490618Stmm#define SBR_KBD_INT_MAP 0x3040 /* kbd [unused] interrupt map reg */ 9590618Stmm#define SBR_MOUSE_INT_MAP 0x3048 /* mouse [unused] interrupt map reg */ 9690618Stmm#define SBR_SERIAL_INT_MAP 0x3050 /* second serial interrupt map reg */ 9790618Stmm#define SBR_TIMER0_INT_MAP 0x3060 /* timer 0 interrupt map reg */ 9890618Stmm#define SBR_TIMER1_INT_MAP 0x3068 /* timer 1 interrupt map reg */ 9990618Stmm#define SBR_UE_INT_MAP 0x3070 /* UE interrupt map reg */ 10090618Stmm#define SBR_CE_INT_MAP 0x3078 /* CE interrupt map reg */ 10190618Stmm#define SBR_ASYNC_INT_MAP 0x3080 /* SBUS error interrupt map reg */ 10290618Stmm#define SBR_PWRMGT_INT_MAP 0x3088 /* power mgmt wake interrupt map reg */ 10390618Stmm#define SBR_UPAGR_INT_MAP 0x3090 /* UPA graphics interrupt map reg */ 10490618Stmm#define SBR_RESERVED_INT_MAP 0x3098 /* reserved interrupt map reg */ 10590618Stmm/* 10690618Stmm * Note: clear interrupt 0 registers are not really used 10790618Stmm */ 10890618Stmm#define SBR_SLOT0_INT_CLR 0x3400 /* SBUS slot 0 clear int regs 0..7 */ 10990618Stmm#define SBR_SLOT1_INT_CLR 0x3440 /* SBUS slot 1 clear int regs 0..7 */ 11090618Stmm#define SBR_SLOT2_INT_CLR 0x3480 /* SBUS slot 2 clear int regs 0..7 */ 11190618Stmm#define SBR_SLOT3_INT_CLR 0x34c0 /* SBUS slot 3 clear int regs 0..7 */ 11290618Stmm#define SBR_SCSI_INT_CLR 0x3800 /* SCSI clear int reg */ 11390618Stmm#define SBR_ETHER_INT_CLR 0x3808 /* ethernet clear int reg */ 11490618Stmm#define SBR_BPP_INT_CLR 0x3810 /* parallel clear int reg */ 11590618Stmm#define SBR_AUDIO_INT_CLR 0x3818 /* audio clear int reg */ 11690618Stmm#define SBR_POWER_INT_CLR 0x3820 /* power fail clear int reg */ 11790618Stmm#define SBR_SKBDMS_INT_CLR 0x3828 /* serial/kbd/mouse clear int reg */ 11890618Stmm#define SBR_FD_INT_CLR 0x3830 /* floppy clear int reg */ 11990618Stmm#define SBR_THERM_INT_CLR 0x3838 /* thermal warn clear int reg */ 12090618Stmm#define SBR_KBD_INT_CLR 0x3840 /* kbd [unused] clear int reg */ 12190618Stmm#define SBR_MOUSE_INT_CLR 0x3848 /* mouse [unused] clear int reg */ 12290618Stmm#define SBR_SERIAL_INT_CLR 0x3850 /* second serial clear int reg */ 12390618Stmm#define SBR_TIMER0_INT_CLR 0x3860 /* timer 0 clear int reg */ 12490618Stmm#define SBR_TIMER1_INT_CLR 0x3868 /* timer 1 clear int reg */ 12590618Stmm#define SBR_UE_INT_CLR 0x3870 /* UE clear int reg */ 12690618Stmm#define SBR_CE_INT_CLR 0x3878 /* CE clear int reg */ 12790618Stmm#define SBR_ASYNC_INT_CLR 0x3880 /* SBUS error clr interrupt reg */ 12890618Stmm#define SBR_PWRMGT_INT_CLR 0x3888 /* power mgmt wake clr interrupt reg */ 12990618Stmm#define SBR_TC0 0x3c00 /* timer/counter 0 */ 13090618Stmm#define SBR_TC1 0x3c10 /* timer/counter 1 */ 13190618Stmm#define SBR_IOMMU_SVADIAG 0x4400 /* SBUS virtual addr diag reg */ 13290618Stmm#define SBR_IOMMU_QUEUE_DIAG 0x4500 /* IOMMU LRU queue diag 0..15 */ 13390618Stmm#define SBR_IOMMU_TLB_TAG_DIAG 0x4580 /* TLB tag diag 0..15 */ 13490618Stmm#define SBR_IOMMU_TLB_DATA_DIAG 0x4600 /* TLB data RAM diag 0..31 */ 13590618Stmm#define SBR_INT_DIAG 0x4800 /* SBUS int state diag reg */ 13690618Stmm#define SBR_OBIO_DIAG 0x4808 /* OBIO and misc int state diag reg */ 13790618Stmm#define SBR_STRBUF_DIAG 0x5000 /* Streaming buffer diag regs */ 13890618Stmm 139172066Smarius/* INO defines */ 140172066Smarius#define SBUS_MAX_INO 0x3f 141172066Smarius 142171730Smarius/* Width of the physical addresses the IOMMU translates to */ 143171730Smarius#define SBUS_IOMMU_BITS 41 144171730Smarius 14590618Stmm#endif /* _SPARC64_SBUS_SBUSREG_H_ */ 146