sbbc.c revision 225931
1/* $OpenBSD: sbbc.c,v 1.7 2009/11/09 17:53:39 nicm Exp $ */ 2/*- 3 * Copyright (c) 2008 Mark Kettenis 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17/*- 18 * Copyright (c) 2010 Marius Strobl <marius@FreeBSD.org> 19 * All rights reserved. 20 * 21 * Redistribution and use in source and binary forms, with or without 22 * modification, are permitted provided that the following conditions 23 * are met: 24 * 1. Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * 2. Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in the 28 * documentation and/or other materials provided with the distribution. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 */ 42 43#include <sys/cdefs.h> 44__FBSDID("$FreeBSD: head/sys/sparc64/pci/sbbc.c 225931 2011-10-02 23:22:38Z marius $"); 45 46#include <sys/param.h> 47#include <sys/systm.h> 48#include <sys/bus.h> 49#include <sys/clock.h> 50#include <sys/endian.h> 51#include <sys/kernel.h> 52#include <sys/lock.h> 53#include <sys/module.h> 54#include <sys/mutex.h> 55#include <sys/resource.h> 56#include <sys/rman.h> 57 58#include <dev/ofw/ofw_bus.h> 59#include <dev/ofw/openfirm.h> 60 61#include <machine/bus.h> 62#include <machine/cpu.h> 63#include <machine/resource.h> 64 65#include <dev/pci/pcireg.h> 66#include <dev/pci/pcivar.h> 67#include <dev/uart/uart.h> 68#include <dev/uart/uart_cpu.h> 69#include <dev/uart/uart_bus.h> 70 71#include "clock_if.h" 72#include "uart_if.h" 73 74#define SBBC_PCI_BAR PCIR_BAR(0) 75#define SBBC_PCI_VENDOR 0x108e 76#define SBBC_PCI_PRODUCT 0xc416 77 78#define SBBC_REGS_OFFSET 0x800000 79#define SBBC_REGS_SIZE 0x6230 80#define SBBC_EPLD_OFFSET 0x8e0000 81#define SBBC_EPLD_SIZE 0x20 82#define SBBC_SRAM_OFFSET 0x900000 83#define SBBC_SRAM_SIZE 0x20000 /* 128KB SRAM */ 84 85#define SBBC_PCI_INT_STATUS 0x2320 86#define SBBC_PCI_INT_ENABLE 0x2330 87#define SBBC_PCI_ENABLE_INT_A 0x11 88 89#define SBBC_EPLD_INTERRUPT 0x13 90#define SBBC_EPLD_INTERRUPT_ON 0x01 91 92#define SBBC_SRAM_CONS_IN 0x00000001 93#define SBBC_SRAM_CONS_OUT 0x00000002 94#define SBBC_SRAM_CONS_BRK 0x00000004 95#define SBBC_SRAM_CONS_SPACE_IN 0x00000008 96#define SBBC_SRAM_CONS_SPACE_OUT 0x00000010 97 98#define SBBC_TAG_KEY_SIZE 8 99#define SBBC_TAG_KEY_SCSOLIE "SCSOLIE" /* SC -> OS int. enable */ 100#define SBBC_TAG_KEY_SCSOLIR "SCSOLIR" /* SC -> OS int. reason */ 101#define SBBC_TAG_KEY_SOLCONS "SOLCONS" /* OS console buffer */ 102#define SBBC_TAG_KEY_SOLSCIE "SOLSCIE" /* OS -> SC int. enable */ 103#define SBBC_TAG_KEY_SOLSCIR "SOLSCIR" /* OS -> SC int. reason */ 104#define SBBC_TAG_KEY_TODDATA "TODDATA" /* OS TOD struct */ 105#define SBBC_TAG_OFF(x) offsetof(struct sbbc_sram_tag, x) 106 107struct sbbc_sram_tag { 108 char tag_key[SBBC_TAG_KEY_SIZE]; 109 uint32_t tag_size; 110 uint32_t tag_offset; 111} __packed; 112 113#define SBBC_TOC_MAGIC "TOCSRAM" 114#define SBBC_TOC_MAGIC_SIZE 8 115#define SBBC_TOC_TAGS_MAX 32 116#define SBBC_TOC_OFF(x) offsetof(struct sbbc_sram_toc, x) 117 118struct sbbc_sram_toc { 119 char toc_magic[SBBC_TOC_MAGIC_SIZE]; 120 uint8_t toc_reserved; 121 uint8_t toc_type; 122 uint16_t toc_version; 123 uint32_t toc_ntags; 124 struct sbbc_sram_tag toc_tag[SBBC_TOC_TAGS_MAX]; 125} __packed; 126 127#define SBBC_TOD_MAGIC 0x54443100 /* "TD1" */ 128#define SBBC_TOD_VERSION 1 129#define SBBC_TOD_OFF(x) offsetof(struct sbbc_sram_tod, x) 130 131struct sbbc_sram_tod { 132 uint32_t tod_magic; 133 uint32_t tod_version; 134 uint64_t tod_time; 135 uint64_t tod_skew; 136 uint32_t tod_reserved; 137 uint32_t tod_heartbeat; 138 uint32_t tod_timeout; 139} __packed; 140 141#define SBBC_CONS_MAGIC 0x434f4e00 /* "CON" */ 142#define SBBC_CONS_VERSION 1 143#define SBBC_CONS_OFF(x) offsetof(struct sbbc_sram_cons, x) 144 145struct sbbc_sram_cons { 146 uint32_t cons_magic; 147 uint32_t cons_version; 148 uint32_t cons_size; 149 150 uint32_t cons_in_begin; 151 uint32_t cons_in_end; 152 uint32_t cons_in_rdptr; 153 uint32_t cons_in_wrptr; 154 155 uint32_t cons_out_begin; 156 uint32_t cons_out_end; 157 uint32_t cons_out_rdptr; 158 uint32_t cons_out_wrptr; 159} __packed; 160 161struct sbbc_softc { 162 struct resource *sc_res; 163}; 164 165#define SBBC_READ_N(wdth, offs) \ 166 bus_space_read_ ## wdth((bst), (bsh), (offs)) 167#define SBBC_WRITE_N(wdth, offs, val) \ 168 bus_space_write_ ## wdth((bst), (bsh), (offs), (val)) 169 170#define SBBC_READ_1(offs) \ 171 SBBC_READ_N(1, (offs)) 172#define SBBC_READ_2(offs) \ 173 bswap16(SBBC_READ_N(2, (offs))) 174#define SBBC_READ_4(offs) \ 175 bswap32(SBBC_READ_N(4, (offs))) 176#define SBBC_READ_8(offs) \ 177 bswap64(SBBC_READ_N(8, (offs))) 178#define SBBC_WRITE_1(offs, val) \ 179 SBBC_WRITE_N(1, (offs), (val)) 180#define SBBC_WRITE_2(offs, val) \ 181 SBBC_WRITE_N(2, (offs), bswap16(val)) 182#define SBBC_WRITE_4(offs, val) \ 183 SBBC_WRITE_N(4, (offs), bswap32(val)) 184#define SBBC_WRITE_8(offs, val) \ 185 SBBC_WRITE_N(8, (offs), bswap64(val)) 186 187#define SBBC_REGS_READ_1(offs) \ 188 SBBC_READ_1((offs) + SBBC_REGS_OFFSET) 189#define SBBC_REGS_READ_2(offs) \ 190 SBBC_READ_2((offs) + SBBC_REGS_OFFSET) 191#define SBBC_REGS_READ_4(offs) \ 192 SBBC_READ_4((offs) + SBBC_REGS_OFFSET) 193#define SBBC_REGS_READ_8(offs) \ 194 SBBC_READ_8((offs) + SBBC_REGS_OFFSET) 195#define SBBC_REGS_WRITE_1(offs, val) \ 196 SBBC_WRITE_1((offs) + SBBC_REGS_OFFSET, (val)) 197#define SBBC_REGS_WRITE_2(offs, val) \ 198 SBBC_WRITE_2((offs) + SBBC_REGS_OFFSET, (val)) 199#define SBBC_REGS_WRITE_4(offs, val) \ 200 SBBC_WRITE_4((offs) + SBBC_REGS_OFFSET, (val)) 201#define SBBC_REGS_WRITE_8(offs, val) \ 202 SBBC_WRITE_8((offs) + SBBC_REGS_OFFSET, (val)) 203 204#define SBBC_EPLD_READ_1(offs) \ 205 SBBC_READ_1((offs) + SBBC_EPLD_OFFSET) 206#define SBBC_EPLD_READ_2(offs) \ 207 SBBC_READ_2((offs) + SBBC_EPLD_OFFSET) 208#define SBBC_EPLD_READ_4(offs) \ 209 SBBC_READ_4((offs) + SBBC_EPLD_OFFSET) 210#define SBBC_EPLD_READ_8(offs) \ 211 SBBC_READ_8((offs) + SBBC_EPLD_OFFSET) 212#define SBBC_EPLD_WRITE_1(offs, val) \ 213 SBBC_WRITE_1((offs) + SBBC_EPLD_OFFSET, (val)) 214#define SBBC_EPLD_WRITE_2(offs, val) \ 215 SBBC_WRITE_2((offs) + SBBC_EPLD_OFFSET, (val)) 216#define SBBC_EPLD_WRITE_4(offs, val) \ 217 SBBC_WRITE_4((offs) + SBBC_EPLD_OFFSET, (val)) 218#define SBBC_EPLD_WRITE_8(offs, val) \ 219 SBBC_WRITE_8((offs) + SBBC_EPLD_OFFSET, (val)) 220 221#define SBBC_SRAM_READ_1(offs) \ 222 SBBC_READ_1((offs) + SBBC_SRAM_OFFSET) 223#define SBBC_SRAM_READ_2(offs) \ 224 SBBC_READ_2((offs) + SBBC_SRAM_OFFSET) 225#define SBBC_SRAM_READ_4(offs) \ 226 SBBC_READ_4((offs) + SBBC_SRAM_OFFSET) 227#define SBBC_SRAM_READ_8(offs) \ 228 SBBC_READ_8((offs) + SBBC_SRAM_OFFSET) 229#define SBBC_SRAM_WRITE_1(offs, val) \ 230 SBBC_WRITE_1((offs) + SBBC_SRAM_OFFSET, (val)) 231#define SBBC_SRAM_WRITE_2(offs, val) \ 232 SBBC_WRITE_2((offs) + SBBC_SRAM_OFFSET, (val)) 233#define SBBC_SRAM_WRITE_4(offs, val) \ 234 SBBC_WRITE_4((offs) + SBBC_SRAM_OFFSET, (val)) 235#define SBBC_SRAM_WRITE_8(offs, val) \ 236 SBBC_WRITE_8((offs) + SBBC_SRAM_OFFSET, (val)) 237 238#define SUNW_SETCONSINPUT "SUNW,set-console-input" 239#define SUNW_SETCONSINPUT_CLNT "CON_CLNT" 240#define SUNW_SETCONSINPUT_OBP "CON_OBP" 241 242static u_int sbbc_console; 243 244static uint32_t sbbc_scsolie; 245static uint32_t sbbc_scsolir; 246static uint32_t sbbc_solcons; 247static uint32_t sbbc_solscie; 248static uint32_t sbbc_solscir; 249static uint32_t sbbc_toddata; 250 251/* 252 * internal helpers 253 */ 254static int sbbc_parse_toc(bus_space_tag_t bst, bus_space_handle_t bsh); 255static inline void sbbc_send_intr(bus_space_tag_t bst, 256 bus_space_handle_t bsh); 257static const char *sbbc_serengeti_set_console_input(char *new); 258 259/* 260 * SBBC PCI interface 261 */ 262static bus_activate_resource_t sbbc_bus_activate_resource; 263static bus_adjust_resource_t sbbc_bus_adjust_resource; 264static bus_deactivate_resource_t sbbc_bus_deactivate_resource; 265static bus_alloc_resource_t sbbc_bus_alloc_resource; 266static bus_release_resource_t sbbc_bus_release_resource; 267static bus_get_resource_list_t sbbc_bus_get_resource_list; 268static bus_setup_intr_t sbbc_bus_setup_intr; 269static bus_teardown_intr_t sbbc_bus_teardown_intr; 270 271static device_attach_t sbbc_pci_attach; 272static device_probe_t sbbc_pci_probe; 273 274static clock_gettime_t sbbc_tod_gettime; 275static clock_settime_t sbbc_tod_settime; 276 277static device_method_t sbbc_pci_methods[] = { 278 /* Device interface */ 279 DEVMETHOD(device_probe, sbbc_pci_probe), 280 DEVMETHOD(device_attach, sbbc_pci_attach), 281 282 DEVMETHOD(bus_print_child, bus_generic_print_child), 283 DEVMETHOD(bus_alloc_resource, sbbc_bus_alloc_resource), 284 DEVMETHOD(bus_activate_resource,sbbc_bus_activate_resource), 285 DEVMETHOD(bus_deactivate_resource,sbbc_bus_deactivate_resource), 286 DEVMETHOD(bus_adjust_resource, sbbc_bus_adjust_resource), 287 DEVMETHOD(bus_release_resource, sbbc_bus_release_resource), 288 DEVMETHOD(bus_setup_intr, sbbc_bus_setup_intr), 289 DEVMETHOD(bus_teardown_intr, sbbc_bus_teardown_intr), 290 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 291 DEVMETHOD(bus_get_resource_list, sbbc_bus_get_resource_list), 292 293 /* clock interface */ 294 DEVMETHOD(clock_gettime, sbbc_tod_gettime), 295 DEVMETHOD(clock_settime, sbbc_tod_settime), 296 297 KOBJMETHOD_END 298}; 299 300static devclass_t sbbc_devclass; 301 302DEFINE_CLASS_0(sbbc, sbbc_driver, sbbc_pci_methods, sizeof(struct sbbc_softc)); 303DRIVER_MODULE(sbbc, pci, sbbc_driver, sbbc_devclass, 0, 0); 304 305static int 306sbbc_pci_probe(device_t dev) 307{ 308 309 if (pci_get_vendor(dev) == SBBC_PCI_VENDOR && 310 pci_get_device(dev) == SBBC_PCI_PRODUCT) { 311 device_set_desc(dev, "Sun BootBus controller"); 312 return (BUS_PROBE_DEFAULT); 313 } 314 return (ENXIO); 315} 316 317static int 318sbbc_pci_attach(device_t dev) 319{ 320 struct sbbc_softc *sc; 321 struct timespec ts; 322 device_t child; 323 bus_space_tag_t bst; 324 bus_space_handle_t bsh; 325 phandle_t node; 326 int error, rid; 327 uint32_t val; 328 329 /* Nothing to to if we're not the chosen one. */ 330 if ((node = OF_finddevice("/chosen")) == -1) { 331 device_printf(dev, "failed to find /chosen\n"); 332 return (ENXIO); 333 } 334 if (OF_getprop(node, "iosram", &node, sizeof(node)) == -1) { 335 device_printf(dev, "failed to get iosram\n"); 336 return (ENXIO); 337 } 338 if (node != ofw_bus_get_node(dev)) 339 return (0); 340 341 sc = device_get_softc(dev); 342 rid = SBBC_PCI_BAR; 343 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 344 RF_ACTIVE); 345 if (sc->sc_res == NULL) { 346 device_printf(dev, "failed to allocate resources\n"); 347 return (ENXIO); 348 } 349 bst = rman_get_bustag(sc->sc_res); 350 bsh = rman_get_bushandle(sc->sc_res); 351 if (sbbc_console != 0) { 352 /* Once again the interrupt pin isn't set. */ 353 if (pci_get_intpin(dev) == 0) 354 pci_set_intpin(dev, 1); 355 child = device_add_child(dev, NULL, -1); 356 if (child == NULL) 357 device_printf(dev, "failed to add UART device\n"); 358 error = bus_generic_attach(dev); 359 if (error != 0) 360 device_printf(dev, "failed to attach UART device\n"); 361 } else { 362 error = sbbc_parse_toc(rman_get_bustag(sc->sc_res), 363 rman_get_bushandle(sc->sc_res)); 364 if (error != 0) { 365 device_printf(dev, "failed to parse TOC\n"); 366 if (sbbc_console != 0) { 367 bus_release_resource(dev, SYS_RES_MEMORY, rid, 368 sc->sc_res); 369 return (error); 370 } 371 } 372 } 373 if (sbbc_toddata != 0) { 374 if ((val = SBBC_SRAM_READ_4(sbbc_toddata + 375 SBBC_TOD_OFF(tod_magic))) != SBBC_TOD_MAGIC) 376 device_printf(dev, "invalid TOD magic %#x\n", val); 377 else if ((val = SBBC_SRAM_READ_4(sbbc_toddata + 378 SBBC_TOD_OFF(tod_version))) < SBBC_TOD_VERSION) 379 device_printf(dev, "invalid TOD version %#x\n", val); 380 else { 381 clock_register(dev, 1000000); /* 1 sec. resolution */ 382 if (bootverbose) { 383 sbbc_tod_gettime(dev, &ts); 384 device_printf(dev, 385 "current time: %ld.%09ld\n", 386 (long)ts.tv_sec, ts.tv_nsec); 387 } 388 } 389 } 390 return (0); 391} 392 393/* 394 * Note that the bus methods don't pass-through the uart(4) requests but act 395 * as if they would come from sbbc(4) in order to avoid complications with 396 * pci(4) (actually, uart(4) isn't a real child but rather a function of 397 * sbbc(4) anyway). 398 */ 399 400static struct resource * 401sbbc_bus_alloc_resource(device_t dev, device_t child __unused, int type, 402 int *rid, u_long start, u_long end, u_long count, u_int flags) 403{ 404 struct sbbc_softc *sc; 405 406 sc = device_get_softc(dev); 407 switch (type) { 408 case SYS_RES_IRQ: 409 return (bus_generic_alloc_resource(dev, dev, type, rid, start, 410 end, count, flags)); 411 case SYS_RES_MEMORY: 412 return (sc->sc_res); 413 default: 414 return (NULL); 415 } 416} 417 418static int 419sbbc_bus_activate_resource(device_t bus, device_t child, int type, int rid, 420 struct resource *res) 421{ 422 423 if (type == SYS_RES_MEMORY) 424 return (0); 425 return (bus_generic_activate_resource(bus, child, type, rid, res)); 426} 427 428static int 429sbbc_bus_deactivate_resource(device_t bus, device_t child, int type, int rid, 430 struct resource *res) 431{ 432 433 if (type == SYS_RES_MEMORY) 434 return (0); 435 return (bus_generic_deactivate_resource(bus, child, type, rid, res)); 436} 437 438static int 439sbbc_bus_adjust_resource(device_t bus __unused, device_t child __unused, 440 int type __unused, struct resource *res __unused, u_long start __unused, 441 u_long end __unused) 442{ 443 444 return (ENXIO); 445} 446 447static int 448sbbc_bus_release_resource(device_t dev, device_t child __unused, int type, 449 int rid, struct resource *res) 450{ 451 452 if (type == SYS_RES_IRQ) 453 return (bus_generic_release_resource(dev, dev, type, rid, 454 res)); 455 return (0); 456} 457 458static struct resource_list * 459sbbc_bus_get_resource_list(device_t dev, device_t child __unused) 460{ 461 462 return (bus_generic_get_resource_list(dev, dev)); 463} 464 465static int 466sbbc_bus_setup_intr(device_t dev, device_t child __unused, 467 struct resource *res, int flags, driver_filter_t *filt, 468 driver_intr_t *intr, void *arg, void **cookiep) 469{ 470 471 return (bus_generic_setup_intr(dev, dev, res, flags, filt, intr, arg, 472 cookiep)); 473} 474 475static int 476sbbc_bus_teardown_intr(device_t dev, device_t child __unused, 477 struct resource *res, void *cookie) 478{ 479 480 return (bus_generic_teardown_intr(dev, dev, res, cookie)); 481} 482 483/* 484 * internal helpers 485 */ 486static int 487sbbc_parse_toc(bus_space_tag_t bst, bus_space_handle_t bsh) 488{ 489 char buf[MAX(SBBC_TAG_KEY_SIZE, SBBC_TOC_MAGIC_SIZE)]; 490 bus_size_t tag; 491 phandle_t node; 492 uint32_t off, sram_toc; 493 u_int i, tags; 494 495 if ((node = OF_finddevice("/chosen")) == -1) 496 return (ENXIO); 497 /* SRAM TOC offset defaults to 0. */ 498 if (OF_getprop(node, "iosram-toc", &sram_toc, sizeof(sram_toc)) <= 0) 499 sram_toc = 0; 500 501 bus_space_read_region_1(bst, bsh, SBBC_SRAM_OFFSET + sram_toc + 502 SBBC_TOC_OFF(toc_magic), buf, SBBC_TOC_MAGIC_SIZE); 503 buf[SBBC_TOC_MAGIC_SIZE - 1] = '\0'; 504 if (strcmp(buf, SBBC_TOC_MAGIC) != 0) 505 return (ENXIO); 506 507 tags = SBBC_SRAM_READ_4(sram_toc + SBBC_TOC_OFF(toc_ntags)); 508 for (i = 0; i < tags; i++) { 509 tag = sram_toc + SBBC_TOC_OFF(toc_tag) + 510 i * sizeof(struct sbbc_sram_tag); 511 bus_space_read_region_1(bst, bsh, SBBC_SRAM_OFFSET + tag + 512 SBBC_TAG_OFF(tag_key), buf, SBBC_TAG_KEY_SIZE); 513 buf[SBBC_TAG_KEY_SIZE - 1] = '\0'; 514 off = SBBC_SRAM_READ_4(tag + SBBC_TAG_OFF(tag_offset)); 515 if (strcmp(buf, SBBC_TAG_KEY_SCSOLIE) == 0) 516 sbbc_scsolie = off; 517 else if (strcmp(buf, SBBC_TAG_KEY_SCSOLIR) == 0) 518 sbbc_scsolir = off; 519 else if (strcmp(buf, SBBC_TAG_KEY_SOLCONS) == 0) 520 sbbc_solcons = off; 521 else if (strcmp(buf, SBBC_TAG_KEY_SOLSCIE) == 0) 522 sbbc_solscie = off; 523 else if (strcmp(buf, SBBC_TAG_KEY_SOLSCIR) == 0) 524 sbbc_solscir = off; 525 else if (strcmp(buf, SBBC_TAG_KEY_TODDATA) == 0) 526 sbbc_toddata = off; 527 } 528 return (0); 529} 530 531static const char * 532sbbc_serengeti_set_console_input(char *new) 533{ 534 struct { 535 cell_t name; 536 cell_t nargs; 537 cell_t nreturns; 538 cell_t new; 539 cell_t old; 540 } args = { 541 (cell_t)SUNW_SETCONSINPUT, 542 1, 543 1, 544 }; 545 546 args.new = (cell_t)new; 547 if (ofw_entry(&args) == -1) 548 return (NULL); 549 return ((const char *)args.old); 550} 551 552static inline void 553sbbc_send_intr(bus_space_tag_t bst, bus_space_handle_t bsh) 554{ 555 556 SBBC_EPLD_WRITE_1(SBBC_EPLD_INTERRUPT, SBBC_EPLD_INTERRUPT_ON); 557 bus_space_barrier(bst, bsh, SBBC_EPLD_OFFSET + SBBC_EPLD_INTERRUPT, 1, 558 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 559} 560 561/* 562 * TOD interface 563 */ 564static int 565sbbc_tod_gettime(device_t dev, struct timespec *ts) 566{ 567 struct sbbc_softc *sc; 568 bus_space_tag_t bst; 569 bus_space_handle_t bsh; 570 571 sc = device_get_softc(dev); 572 bst = rman_get_bustag(sc->sc_res); 573 bsh = rman_get_bushandle(sc->sc_res); 574 575 ts->tv_sec = SBBC_SRAM_READ_8(sbbc_toddata + SBBC_TOD_OFF(tod_time)) + 576 SBBC_SRAM_READ_8(sbbc_toddata + SBBC_TOD_OFF(tod_skew)); 577 ts->tv_nsec = 0; 578 return (0); 579} 580 581static int 582sbbc_tod_settime(device_t dev, struct timespec *ts) 583{ 584 struct sbbc_softc *sc; 585 bus_space_tag_t bst; 586 bus_space_handle_t bsh; 587 588 sc = device_get_softc(dev); 589 bst = rman_get_bustag(sc->sc_res); 590 bsh = rman_get_bushandle(sc->sc_res); 591 592 SBBC_SRAM_WRITE_8(sbbc_toddata + SBBC_TOD_OFF(tod_skew), ts->tv_sec - 593 SBBC_SRAM_READ_8(sbbc_toddata + SBBC_TOD_OFF(tod_time))); 594 return (0); 595} 596 597/* 598 * UART bus front-end 599 */ 600static device_probe_t sbbc_uart_sbbc_probe; 601 602static device_method_t sbbc_uart_sbbc_methods[] = { 603 /* Device interface */ 604 DEVMETHOD(device_probe, sbbc_uart_sbbc_probe), 605 DEVMETHOD(device_attach, uart_bus_attach), 606 DEVMETHOD(device_detach, uart_bus_detach), 607 608 KOBJMETHOD_END 609}; 610 611DEFINE_CLASS_0(uart, sbbc_uart_driver, sbbc_uart_sbbc_methods, 612 sizeof(struct uart_softc)); 613DRIVER_MODULE(uart, sbbc, sbbc_uart_driver, uart_devclass, 0, 0); 614 615static int 616sbbc_uart_sbbc_probe(device_t dev) 617{ 618 struct uart_softc *sc; 619 620 sc = device_get_softc(dev); 621 sc->sc_class = &uart_sbbc_class; 622 device_set_desc(dev, "Serengeti console"); 623 return (uart_bus_probe(dev, 0, 0, SBBC_PCI_BAR, 0)); 624} 625 626/* 627 * Low-level UART interface 628 */ 629static int sbbc_uart_probe(struct uart_bas *bas); 630static void sbbc_uart_init(struct uart_bas *bas, int baudrate, int databits, 631 int stopbits, int parity); 632static void sbbc_uart_term(struct uart_bas *bas); 633static void sbbc_uart_putc(struct uart_bas *bas, int c); 634static int sbbc_uart_rxready(struct uart_bas *bas); 635static int sbbc_uart_getc(struct uart_bas *bas, struct mtx *hwmtx); 636 637static struct uart_ops sbbc_uart_ops = { 638 .probe = sbbc_uart_probe, 639 .init = sbbc_uart_init, 640 .term = sbbc_uart_term, 641 .putc = sbbc_uart_putc, 642 .rxready = sbbc_uart_rxready, 643 .getc = sbbc_uart_getc, 644}; 645 646static int 647sbbc_uart_probe(struct uart_bas *bas) 648{ 649 bus_space_tag_t bst; 650 bus_space_handle_t bsh; 651 int error; 652 653 sbbc_console = 1; 654 bst = bas->bst; 655 bsh = bas->bsh; 656 error = sbbc_parse_toc(bst, bsh); 657 if (error != 0) 658 return (error); 659 660 if (sbbc_scsolie == 0 || sbbc_scsolir == 0 || sbbc_solcons == 0 || 661 sbbc_solscie == 0 || sbbc_solscir == 0) 662 return (ENXIO); 663 664 if (SBBC_SRAM_READ_4(sbbc_solcons + SBBC_CONS_OFF(cons_magic)) != 665 SBBC_CONS_MAGIC || SBBC_SRAM_READ_4(sbbc_solcons + 666 SBBC_CONS_OFF(cons_version)) < SBBC_CONS_VERSION) 667 return (ENXIO); 668 return (0); 669} 670 671static void 672sbbc_uart_init(struct uart_bas *bas, int baudrate __unused, 673 int databits __unused, int stopbits __unused, int parity __unused) 674{ 675 bus_space_tag_t bst; 676 bus_space_handle_t bsh; 677 678 bst = bas->bst; 679 bsh = bas->bsh; 680 681 /* Enable output to and space in from the SC interrupts. */ 682 SBBC_SRAM_WRITE_4(sbbc_solscie, SBBC_SRAM_READ_4(sbbc_solscie) | 683 SBBC_SRAM_CONS_OUT | SBBC_SRAM_CONS_SPACE_IN); 684 uart_barrier(bas); 685 686 /* Take over the console input. */ 687 sbbc_serengeti_set_console_input(SUNW_SETCONSINPUT_CLNT); 688} 689 690static void 691sbbc_uart_term(struct uart_bas *bas __unused) 692{ 693 694 /* Give back the console input. */ 695 sbbc_serengeti_set_console_input(SUNW_SETCONSINPUT_OBP); 696} 697 698static void 699sbbc_uart_putc(struct uart_bas *bas, int c) 700{ 701 bus_space_tag_t bst; 702 bus_space_handle_t bsh; 703 uint32_t wrptr; 704 705 bst = bas->bst; 706 bsh = bas->bsh; 707 708 wrptr = SBBC_SRAM_READ_4(sbbc_solcons + 709 SBBC_CONS_OFF(cons_out_wrptr)); 710 SBBC_SRAM_WRITE_1(sbbc_solcons + wrptr, c); 711 uart_barrier(bas); 712 if (++wrptr == SBBC_SRAM_READ_4(sbbc_solcons + 713 SBBC_CONS_OFF(cons_out_end))) 714 wrptr = SBBC_SRAM_READ_4(sbbc_solcons + 715 SBBC_CONS_OFF(cons_out_begin)); 716 SBBC_SRAM_WRITE_4(sbbc_solcons + SBBC_CONS_OFF(cons_out_wrptr), 717 wrptr); 718 uart_barrier(bas); 719 720 SBBC_SRAM_WRITE_4(sbbc_solscir, SBBC_SRAM_READ_4(sbbc_solscir) | 721 SBBC_SRAM_CONS_OUT); 722 uart_barrier(bas); 723 sbbc_send_intr(bst, bsh); 724} 725 726static int 727sbbc_uart_rxready(struct uart_bas *bas) 728{ 729 bus_space_tag_t bst; 730 bus_space_handle_t bsh; 731 732 bst = bas->bst; 733 bsh = bas->bsh; 734 735 if (SBBC_SRAM_READ_4(sbbc_solcons + SBBC_CONS_OFF(cons_in_rdptr)) == 736 SBBC_SRAM_READ_4(sbbc_solcons + SBBC_CONS_OFF(cons_in_wrptr))) 737 return (0); 738 return (1); 739} 740 741static int 742sbbc_uart_getc(struct uart_bas *bas, struct mtx *hwmtx) 743{ 744 bus_space_tag_t bst; 745 bus_space_handle_t bsh; 746 int c; 747 uint32_t rdptr; 748 749 bst = bas->bst; 750 bsh = bas->bsh; 751 752 uart_lock(hwmtx); 753 754 while (sbbc_uart_rxready(bas) == 0) { 755 uart_unlock(hwmtx); 756 DELAY(4); 757 uart_lock(hwmtx); 758 } 759 760 rdptr = SBBC_SRAM_READ_4(sbbc_solcons + SBBC_CONS_OFF(cons_in_rdptr)); 761 c = SBBC_SRAM_READ_1(sbbc_solcons + rdptr); 762 uart_barrier(bas); 763 if (++rdptr == SBBC_SRAM_READ_4(sbbc_solcons + 764 SBBC_CONS_OFF(cons_in_end))) 765 rdptr = SBBC_SRAM_READ_4(sbbc_solcons + 766 SBBC_CONS_OFF(cons_in_begin)); 767 SBBC_SRAM_WRITE_4(sbbc_solcons + SBBC_CONS_OFF(cons_in_rdptr), 768 rdptr); 769 uart_barrier(bas); 770 SBBC_SRAM_WRITE_4(sbbc_solscir, SBBC_SRAM_READ_4(sbbc_solscir) | 771 SBBC_SRAM_CONS_SPACE_IN); 772 uart_barrier(bas); 773 sbbc_send_intr(bst, bsh); 774 775 uart_unlock(hwmtx); 776 return (c); 777} 778 779/* 780 * High-level UART interface 781 */ 782static int sbbc_uart_bus_attach(struct uart_softc *sc); 783static int sbbc_uart_bus_detach(struct uart_softc *sc); 784static int sbbc_uart_bus_flush(struct uart_softc *sc, int what); 785static int sbbc_uart_bus_getsig(struct uart_softc *sc); 786static int sbbc_uart_bus_ioctl(struct uart_softc *sc, int request, 787 intptr_t data); 788static int sbbc_uart_bus_ipend(struct uart_softc *sc); 789static int sbbc_uart_bus_param(struct uart_softc *sc, int baudrate, 790 int databits, int stopbits, int parity); 791static int sbbc_uart_bus_probe(struct uart_softc *sc); 792static int sbbc_uart_bus_receive(struct uart_softc *sc); 793static int sbbc_uart_bus_setsig(struct uart_softc *sc, int sig); 794static int sbbc_uart_bus_transmit(struct uart_softc *sc); 795 796static kobj_method_t sbbc_uart_methods[] = { 797 KOBJMETHOD(uart_attach, sbbc_uart_bus_attach), 798 KOBJMETHOD(uart_detach, sbbc_uart_bus_detach), 799 KOBJMETHOD(uart_flush, sbbc_uart_bus_flush), 800 KOBJMETHOD(uart_getsig, sbbc_uart_bus_getsig), 801 KOBJMETHOD(uart_ioctl, sbbc_uart_bus_ioctl), 802 KOBJMETHOD(uart_ipend, sbbc_uart_bus_ipend), 803 KOBJMETHOD(uart_param, sbbc_uart_bus_param), 804 KOBJMETHOD(uart_probe, sbbc_uart_bus_probe), 805 KOBJMETHOD(uart_receive, sbbc_uart_bus_receive), 806 KOBJMETHOD(uart_setsig, sbbc_uart_bus_setsig), 807 KOBJMETHOD(uart_transmit, sbbc_uart_bus_transmit), 808 809 KOBJMETHOD_END 810}; 811 812struct uart_class uart_sbbc_class = { 813 "sbbc", 814 sbbc_uart_methods, 815 sizeof(struct uart_softc), 816 .uc_ops = &sbbc_uart_ops, 817 .uc_range = 1, 818 .uc_rclk = 0x5bbc /* arbitrary */ 819}; 820 821#define SIGCHG(c, i, s, d) \ 822 if ((c) != 0) { \ 823 i |= (((i) & (s)) != 0) ? (s) : (s) | (d); \ 824 } else { \ 825 i = (((i) & (s)) != 0) ? ((i) & ~(s)) | (d) : (i); \ 826 } 827 828static int 829sbbc_uart_bus_attach(struct uart_softc *sc) 830{ 831 struct uart_bas *bas; 832 bus_space_tag_t bst; 833 bus_space_handle_t bsh; 834 uint32_t wrptr; 835 836 bas = &sc->sc_bas; 837 bst = bas->bst; 838 bsh = bas->bsh; 839 840 sc->sc_rxfifosz = SBBC_SRAM_READ_4(sbbc_solcons + 841 SBBC_CONS_OFF(cons_in_end)) - SBBC_SRAM_READ_4(sbbc_solcons + 842 SBBC_CONS_OFF(cons_in_begin)) - 1; 843 sc->sc_txfifosz = SBBC_SRAM_READ_4(sbbc_solcons + 844 SBBC_CONS_OFF(cons_out_end)) - SBBC_SRAM_READ_4(sbbc_solcons + 845 SBBC_CONS_OFF(cons_out_begin)) - 1; 846 847 uart_lock(sc->sc_hwmtx); 848 849 /* 850 * Let the current output drain before enabling interrupts. Not 851 * doing so tends to cause lost output when turning them on. 852 */ 853 wrptr = SBBC_SRAM_READ_4(sbbc_solcons + 854 SBBC_CONS_OFF(cons_out_wrptr)); 855 while (SBBC_SRAM_READ_4(sbbc_solcons + 856 SBBC_CONS_OFF(cons_out_rdptr)) != wrptr); 857 cpu_spinwait(); 858 859 /* Clear and acknowledge possibly outstanding interrupts. */ 860 SBBC_SRAM_WRITE_4(sbbc_scsolir, 0); 861 uart_barrier(bas); 862 SBBC_REGS_WRITE_4(SBBC_PCI_INT_STATUS, 863 SBBC_SRAM_READ_4(sbbc_scsolir)); 864 uart_barrier(bas); 865 /* Enable PCI interrupts. */ 866 SBBC_REGS_WRITE_4(SBBC_PCI_INT_ENABLE, SBBC_PCI_ENABLE_INT_A); 867 uart_barrier(bas); 868 /* Enable input from and output to SC as well as break interrupts. */ 869 SBBC_SRAM_WRITE_4(sbbc_scsolie, SBBC_SRAM_READ_4(sbbc_scsolie) | 870 SBBC_SRAM_CONS_IN | SBBC_SRAM_CONS_BRK | 871 SBBC_SRAM_CONS_SPACE_OUT); 872 uart_barrier(bas); 873 874 uart_unlock(sc->sc_hwmtx); 875 return (0); 876} 877 878static int 879sbbc_uart_bus_detach(struct uart_softc *sc) 880{ 881 882 /* Give back the console input. */ 883 sbbc_serengeti_set_console_input(SUNW_SETCONSINPUT_OBP); 884 return (0); 885} 886 887static int 888sbbc_uart_bus_flush(struct uart_softc *sc, int what) 889{ 890 struct uart_bas *bas; 891 bus_space_tag_t bst; 892 bus_space_handle_t bsh; 893 894 bas = &sc->sc_bas; 895 bst = bas->bst; 896 bsh = bas->bsh; 897 898 if ((what & UART_FLUSH_TRANSMITTER) != 0) 899 return (ENODEV); 900 if ((what & UART_FLUSH_RECEIVER) != 0) { 901 SBBC_SRAM_WRITE_4(sbbc_solcons + 902 SBBC_CONS_OFF(cons_in_rdptr), 903 SBBC_SRAM_READ_4(sbbc_solcons + 904 SBBC_CONS_OFF(cons_in_wrptr))); 905 uart_barrier(bas); 906 } 907 return (0); 908} 909 910static int 911sbbc_uart_bus_getsig(struct uart_softc *sc) 912{ 913 uint32_t dummy, new, old, sig; 914 915 do { 916 old = sc->sc_hwsig; 917 sig = old; 918 dummy = 0; 919 SIGCHG(dummy, sig, SER_CTS, SER_DCTS); 920 SIGCHG(dummy, sig, SER_DCD, SER_DDCD); 921 SIGCHG(dummy, sig, SER_DSR, SER_DDSR); 922 new = sig & ~SER_MASK_DELTA; 923 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 924 return (sig); 925} 926 927static int 928sbbc_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 929{ 930 int error; 931 932 error = 0; 933 uart_lock(sc->sc_hwmtx); 934 switch (request) { 935 case UART_IOCTL_BAUD: 936 *(int*)data = 9600; /* arbitrary */ 937 break; 938 default: 939 error = EINVAL; 940 break; 941 } 942 uart_unlock(sc->sc_hwmtx); 943 return (error); 944} 945 946static int 947sbbc_uart_bus_ipend(struct uart_softc *sc) 948{ 949 struct uart_bas *bas; 950 bus_space_tag_t bst; 951 bus_space_handle_t bsh; 952 int ipend; 953 uint32_t reason, status; 954 955 bas = &sc->sc_bas; 956 bst = bas->bst; 957 bsh = bas->bsh; 958 959 uart_lock(sc->sc_hwmtx); 960 status = SBBC_REGS_READ_4(SBBC_PCI_INT_STATUS); 961 if (status == 0) { 962 uart_unlock(sc->sc_hwmtx); 963 return (0); 964 } 965 966 /* 967 * Unfortunately, we can't use compare and swap for non-cachable 968 * memory. 969 */ 970 reason = SBBC_SRAM_READ_4(sbbc_scsolir); 971 SBBC_SRAM_WRITE_4(sbbc_scsolir, 0); 972 uart_barrier(bas); 973 /* Acknowledge the interrupt. */ 974 SBBC_REGS_WRITE_4(SBBC_PCI_INT_STATUS, status); 975 uart_barrier(bas); 976 977 uart_unlock(sc->sc_hwmtx); 978 979 ipend = 0; 980 if ((reason & SBBC_SRAM_CONS_IN) != 0) 981 ipend |= SER_INT_RXREADY; 982 if ((reason & SBBC_SRAM_CONS_BRK) != 0) 983 ipend |= SER_INT_BREAK; 984 if ((reason & SBBC_SRAM_CONS_SPACE_OUT) != 0 && 985 SBBC_SRAM_READ_4(sbbc_solcons + SBBC_CONS_OFF(cons_out_rdptr)) == 986 SBBC_SRAM_READ_4(sbbc_solcons + SBBC_CONS_OFF(cons_out_wrptr))) 987 ipend |= SER_INT_TXIDLE; 988 return (ipend); 989} 990 991static int 992sbbc_uart_bus_param(struct uart_softc *sc __unused, int baudrate __unused, 993 int databits __unused, int stopbits __unused, int parity __unused) 994{ 995 996 return (0); 997} 998 999static int 1000sbbc_uart_bus_probe(struct uart_softc *sc __unused) 1001{ 1002 1003 if (sbbc_console != 0) 1004 return (0); 1005 return (ENXIO); 1006} 1007 1008static int 1009sbbc_uart_bus_receive(struct uart_softc *sc) 1010{ 1011 struct uart_bas *bas; 1012 bus_space_tag_t bst; 1013 bus_space_handle_t bsh; 1014 int c; 1015 uint32_t end, rdptr, wrptr; 1016 1017 bas = &sc->sc_bas; 1018 bst = bas->bst; 1019 bsh = bas->bsh; 1020 1021 uart_lock(sc->sc_hwmtx); 1022 1023 end = SBBC_SRAM_READ_4(sbbc_solcons + SBBC_CONS_OFF(cons_in_end)); 1024 rdptr = SBBC_SRAM_READ_4(sbbc_solcons + SBBC_CONS_OFF(cons_in_rdptr)); 1025 wrptr = SBBC_SRAM_READ_4(sbbc_solcons + SBBC_CONS_OFF(cons_in_wrptr)); 1026 while (rdptr != wrptr) { 1027 if (uart_rx_full(sc) != 0) { 1028 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 1029 break; 1030 } 1031 c = SBBC_SRAM_READ_1(sbbc_solcons + rdptr); 1032 uart_rx_put(sc, c); 1033 if (++rdptr == end) 1034 rdptr = SBBC_SRAM_READ_4(sbbc_solcons + 1035 SBBC_CONS_OFF(cons_in_begin)); 1036 } 1037 uart_barrier(bas); 1038 SBBC_SRAM_WRITE_4(sbbc_solcons + SBBC_CONS_OFF(cons_in_rdptr), 1039 rdptr); 1040 uart_barrier(bas); 1041 SBBC_SRAM_WRITE_4(sbbc_solscir, SBBC_SRAM_READ_4(sbbc_solscir) | 1042 SBBC_SRAM_CONS_SPACE_IN); 1043 uart_barrier(bas); 1044 sbbc_send_intr(bst, bsh); 1045 1046 uart_unlock(sc->sc_hwmtx); 1047 return (0); 1048} 1049 1050static int 1051sbbc_uart_bus_setsig(struct uart_softc *sc, int sig) 1052{ 1053 struct uart_bas *bas; 1054 uint32_t new, old; 1055 1056 bas = &sc->sc_bas; 1057 do { 1058 old = sc->sc_hwsig; 1059 new = old; 1060 if ((sig & SER_DDTR) != 0) { 1061 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR); 1062 } 1063 if ((sig & SER_DRTS) != 0) { 1064 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS); 1065 } 1066 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 1067 return (0); 1068} 1069 1070static int 1071sbbc_uart_bus_transmit(struct uart_softc *sc) 1072{ 1073 struct uart_bas *bas; 1074 bus_space_tag_t bst; 1075 bus_space_handle_t bsh; 1076 int i; 1077 uint32_t end, wrptr; 1078 1079 bas = &sc->sc_bas; 1080 bst = bas->bst; 1081 bsh = bas->bsh; 1082 1083 uart_lock(sc->sc_hwmtx); 1084 1085 end = SBBC_SRAM_READ_4(sbbc_solcons + SBBC_CONS_OFF(cons_out_end)); 1086 wrptr = SBBC_SRAM_READ_4(sbbc_solcons + 1087 SBBC_CONS_OFF(cons_out_wrptr)); 1088 for (i = 0; i < sc->sc_txdatasz; i++) { 1089 SBBC_SRAM_WRITE_1(sbbc_solcons + wrptr, sc->sc_txbuf[i]); 1090 if (++wrptr == end) 1091 wrptr = SBBC_SRAM_READ_4(sbbc_solcons + 1092 SBBC_CONS_OFF(cons_out_begin)); 1093 } 1094 uart_barrier(bas); 1095 SBBC_SRAM_WRITE_4(sbbc_solcons + SBBC_CONS_OFF(cons_out_wrptr), 1096 wrptr); 1097 uart_barrier(bas); 1098 SBBC_SRAM_WRITE_4(sbbc_solscir, SBBC_SRAM_READ_4(sbbc_solscir) | 1099 SBBC_SRAM_CONS_OUT); 1100 uart_barrier(bas); 1101 sbbc_send_intr(bst, bsh); 1102 sc->sc_txbusy = 1; 1103 1104 uart_unlock(sc->sc_hwmtx); 1105 return (0); 1106} 1107