psycho.c revision 93682
1/* 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * All rights reserved. 4 * Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 30 * 31 * $FreeBSD: head/sys/sparc64/pci/psycho.c 93682 2002-04-02 17:27:35Z tmm $ 32 */ 33 34/* 35 * Support for `psycho' and `psycho+' UPA to PCI bridge and 36 * UltraSPARC IIi and IIe `sabre' PCI controllers. 37 */ 38 39#include "opt_psycho.h" 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/kernel.h> 45#include <sys/malloc.h> 46 47#include <ofw/openfirm.h> 48#include <ofw/ofw_pci.h> 49 50#include <machine/bus.h> 51#include <machine/iommureg.h> 52#include <machine/bus_common.h> 53#include <machine/frame.h> 54#include <machine/intr_machdep.h> 55#include <machine/nexusvar.h> 56#include <machine/ofw_upa.h> 57#include <machine/resource.h> 58 59#include <sys/rman.h> 60 61#include <machine/iommuvar.h> 62 63#include <pci/pcivar.h> 64#include <pci/pcireg.h> 65 66#include <sparc64/pci/ofw_pci.h> 67#include <sparc64/pci/psychoreg.h> 68#include <sparc64/pci/psychovar.h> 69 70#include "pcib_if.h" 71#include "sparcbus_if.h" 72 73static void psycho_get_ranges(phandle_t, struct upa_ranges **, int *); 74static void psycho_set_intr(struct psycho_softc *, int, device_t, bus_addr_t, 75 int, driver_intr_t); 76static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *, 77 bus_addr_t *, u_long *); 78static void psycho_intr_stub(void *); 79#ifdef PSYCHO_STRAY 80static void psycho_intr_stray(void *); 81#endif 82static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 83 84 85/* Interrupt handlers */ 86static void psycho_ue(void *); 87static void psycho_ce(void *); 88static void psycho_bus_a(void *); 89static void psycho_bus_b(void *); 90static void psycho_powerfail(void *); 91#ifdef PSYCHO_MAP_WAKEUP 92static void psycho_wakeup(void *); 93#endif 94 95/* IOMMU support */ 96static void psycho_iommu_init(struct psycho_softc *, int); 97 98/* 99 * bus space and bus dma support for UltraSPARC `psycho'. note that most 100 * of the bus dma support is provided by the iommu dvma controller. 101 */ 102static int psycho_dmamap_create(bus_dma_tag_t, bus_dma_tag_t, int, 103 bus_dmamap_t *); 104static int psycho_dmamap_destroy(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 105static int psycho_dmamap_load(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 106 void *, bus_size_t, bus_dmamap_callback_t *, void *, int); 107static void psycho_dmamap_unload(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 108static void psycho_dmamap_sync(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 109 bus_dmasync_op_t); 110static int psycho_dmamem_alloc(bus_dma_tag_t, bus_dma_tag_t, void **, int, 111 bus_dmamap_t *); 112static void psycho_dmamem_free(bus_dma_tag_t, bus_dma_tag_t, void *, 113 bus_dmamap_t); 114 115/* 116 * autoconfiguration 117 */ 118static int psycho_probe(device_t); 119static int psycho_attach(device_t); 120static int psycho_read_ivar(device_t, device_t, int, u_long *); 121static int psycho_setup_intr(device_t, device_t, struct resource *, int, 122 driver_intr_t *, void *, void **); 123static int psycho_teardown_intr(device_t, device_t, struct resource *, void *); 124static struct resource *psycho_alloc_resource(device_t, device_t, int, int *, 125 u_long, u_long, u_long, u_int); 126static int psycho_activate_resource(device_t, device_t, int, int, 127 struct resource *); 128static int psycho_deactivate_resource(device_t, device_t, int, int, 129 struct resource *); 130static int psycho_release_resource(device_t, device_t, int, int, 131 struct resource *); 132static int psycho_maxslots(device_t); 133static u_int32_t psycho_read_config(device_t, u_int, u_int, u_int, u_int, int); 134static void psycho_write_config(device_t, u_int, u_int, u_int, u_int, u_int32_t, 135 int); 136static int psycho_route_interrupt(device_t, device_t, int); 137static int psycho_intr_pending(device_t, int); 138static bus_space_handle_t psycho_get_bus_handle(device_t dev, enum sbbt_id id, 139 bus_space_handle_t childhdl, bus_space_tag_t *tag); 140 141static device_method_t psycho_methods[] = { 142 /* Device interface */ 143 DEVMETHOD(device_probe, psycho_probe), 144 DEVMETHOD(device_attach, psycho_attach), 145 146 /* Bus interface */ 147 DEVMETHOD(bus_print_child, bus_generic_print_child), 148 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 149 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 150 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 151 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 152 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 153 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 154 DEVMETHOD(bus_release_resource, psycho_release_resource), 155 156 /* pcib interface */ 157 DEVMETHOD(pcib_maxslots, psycho_maxslots), 158 DEVMETHOD(pcib_read_config, psycho_read_config), 159 DEVMETHOD(pcib_write_config, psycho_write_config), 160 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 161 162 /* sparcbus interface */ 163 DEVMETHOD(sparcbus_intr_pending, psycho_intr_pending), 164 DEVMETHOD(sparcbus_get_bus_handle, psycho_get_bus_handle), 165 166 { 0, 0 } 167}; 168 169static driver_t psycho_driver = { 170 "pcib", 171 psycho_methods, 172 sizeof(struct psycho_softc), 173}; 174 175static devclass_t psycho_devclass; 176 177DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 178 179static int psycho_ndevs; 180static struct psycho_softc *psycho_softcs[4]; 181 182struct psycho_clr { 183 struct psycho_softc *pci_sc; 184 bus_addr_t pci_clr; /* clear register */ 185 driver_intr_t *pci_handler; /* handler to call */ 186 void *pci_arg; /* argument for the handler */ 187 void *pci_cookie; /* interrupt cookie of parent bus */ 188}; 189 190struct psycho_strayclr { 191 struct psycho_softc *psc_sc; 192 bus_addr_t psc_clr; /* clear register */ 193}; 194 195#define PSYCHO_READ8(sc, off) \ 196 bus_space_read_8((sc)->sc_bustag, (sc)->sc_bushandle, (off)) 197#define PSYCHO_WRITE8(sc, off, v) \ 198 bus_space_write_8((sc)->sc_bustag, (sc)->sc_bushandle, (off), (v)) 199#define PCICTL_READ8(sc, off) \ 200 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 201#define PCICTL_WRITE8(sc, off, v) \ 202 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 203 204/* 205 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 206 * single PCI bus and does not have a streaming buffer. It often has an APB 207 * (advanced PCI bridge) connected to it, which was designed specifically for 208 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 209 * appears as two "simba"'s underneath the sabre. 210 * 211 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 212 * and manages two PCI buses. "psycho" has two 64-bit 33MHz buses, while 213 * "psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 214 * will usually find a "psycho+" since I don't think the original "psycho" 215 * ever shipped, and if it did it would be in the U30. 216 * 217 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 218 * both part of the same IC, they only have a single register space. As such, 219 * they need to be configured together, even though the autoconfiguration will 220 * attach them separately. 221 * 222 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 223 * as pci1 and pci2, although they have been implemented with other PCI bus 224 * numbers on some machines. 225 * 226 * On UltraII machines, there can be any number of "psycho+" ICs, each 227 * providing two PCI buses. 228 * 229 * 230 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 231 * the values of the following interrupts in this order: 232 * 233 * PCI Bus Error (30) 234 * DMA UE (2e) 235 * DMA CE (2f) 236 * Power Fail (25) 237 * 238 * We really should attach handlers for each. 239 */ 240#define OFW_PCI_TYPE "pci" 241#define OFW_SABRE_MODEL "SUNW,sabre" 242#define OFW_SABRE_COMPAT "pci108e,a001" 243#define OFW_SIMBA_MODEL "SUNW,simba" 244#define OFW_PSYCHO_MODEL "SUNW,psycho" 245 246static int 247psycho_probe(device_t dev) 248{ 249 phandle_t node; 250 char *dtype, *model; 251 static char compat[32]; 252 253 node = nexus_get_node(dev); 254 if (OF_getprop(node, "compatible", compat, sizeof(compat)) == -1) 255 compat[0] = '\0'; 256 257 dtype = nexus_get_device_type(dev); 258 model = nexus_get_model(dev); 259 /* match on a type of "pci" and a sabre or a psycho */ 260 if (nexus_get_reg(dev) != NULL && dtype != NULL && 261 strcmp(dtype, OFW_PCI_TYPE) == 0 && 262 ((model != NULL && (strcmp(model, OFW_SABRE_MODEL) == 0 || 263 strcmp(model, OFW_PSYCHO_MODEL) == 0)) || 264 strcmp(compat, OFW_SABRE_COMPAT) == 0)) { 265 device_set_desc(dev, "U2P UPA-PCI bridge"); 266 return (0); 267 } 268 269 return (ENXIO); 270} 271 272/* 273 * SUNW,psycho initialisation .. 274 * - find the per-psycho registers 275 * - figure out the IGN. 276 * - find our partner psycho 277 * - configure ourselves 278 * - bus range, bus, 279 * - interrupt map, 280 * - setup the chipsets. 281 * - if we're the first of the pair, initialise the IOMMU, otherwise 282 * just copy it's tags and addresses. 283 */ 284static int 285psycho_attach(device_t dev) 286{ 287 struct psycho_softc *sc; 288 struct psycho_softc *osc = NULL; 289 struct psycho_softc *asc; 290 struct upa_regs *reg; 291 char compat[32]; 292 char *model; 293 phandle_t node; 294 u_int64_t csr; 295 u_long pcictl_offs, mlen; 296 int psycho_br[2]; 297 int n, i, nreg, rid; 298#if defined(PSYCHO_DEBUG) || defined(PSYCHO_STRAY) 299 bus_addr_t map, clr; 300 u_int64_t mr; 301#endif 302#ifdef PSYCHO_STRAY 303 struct psycho_strayclr *sclr; 304#endif 305 306 node = nexus_get_node(dev); 307 sc = device_get_softc(dev); 308 if (OF_getprop(node, "compatible", compat, sizeof(compat)) == -1) 309 compat[0] = '\0'; 310 311 sc->sc_node = node; 312 sc->sc_dev = dev; 313 sc->sc_dmatag = nexus_get_dmatag(dev); 314 315 /* 316 * call the model-specific initialisation routine. 317 */ 318 model = nexus_get_model(dev); 319 if ((model != NULL && 320 strcmp(model, OFW_SABRE_MODEL) == 0) || 321 strcmp(compat, OFW_SABRE_COMPAT) == 0) { 322 sc->sc_mode = PSYCHO_MODE_SABRE; 323 if (model == NULL) 324 model = "sabre"; 325 } else if (model != NULL && 326 strcmp(model, OFW_PSYCHO_MODEL) == 0) 327 sc->sc_mode = PSYCHO_MODE_PSYCHO; 328 else 329 panic("psycho_attach: unknown model!"); 330 331 /* 332 * The psycho gets three register banks: 333 * (0) per-PBM configuration and status registers 334 * (1) per-PBM PCI configuration space, containing only the 335 * PBM 256-byte PCI header 336 * (2) the shared psycho configuration registers (struct psychoreg) 337 * 338 * XXX use the prom address for the psycho registers? we do so far. 339 */ 340 reg = nexus_get_reg(dev); 341 nreg = nexus_get_nreg(dev); 342 /* Register layouts are different. stuupid. */ 343 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 344 if (nreg <= 2) 345 panic("psycho_attach: %d not enough registers", nreg); 346 sc->sc_basepaddr = (vm_offset_t)UPA_REG_PHYS(®[2]); 347 mlen = UPA_REG_SIZE(®[2]); 348 pcictl_offs = UPA_REG_PHYS(®[0]); 349 } else { 350 if (nreg <= 0) 351 panic("psycho_attach: %d not enough registers", nreg); 352 sc->sc_basepaddr = (vm_offset_t)UPA_REG_PHYS(®[0]); 353 mlen = UPA_REG_SIZE(reg); 354 pcictl_offs = sc->sc_basepaddr + PSR_PCICTL0; 355 } 356 357 /* 358 * Match other psycho's that are already configured against 359 * the base physical address. This will be the same for a 360 * pair of devices that share register space. 361 */ 362 for (n = 0; n < psycho_ndevs && n < sizeof(psycho_softcs) / 363 sizeof(psycho_softcs[0]); n++) { 364 asc = (struct psycho_softc *)psycho_softcs[n]; 365 366 if (asc == NULL || asc == sc) 367 /* This entry is not there or it is me */ 368 continue; 369 370 if (asc->sc_basepaddr != sc->sc_basepaddr) 371 /* This is an unrelated psycho */ 372 continue; 373 374 /* Found partner */ 375 osc = asc; 376 break; 377 } 378 379 if (osc == NULL) { 380 rid = 0; 381 sc->sc_mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 382 sc->sc_basepaddr, sc->sc_basepaddr + mlen - 1, mlen, 383 RF_ACTIVE); 384 if (sc->sc_mem_res == NULL || 385 rman_get_start(sc->sc_mem_res) != sc->sc_basepaddr) 386 panic("psycho_attach: can't allocate device memory"); 387 sc->sc_bustag = rman_get_bustag(sc->sc_mem_res); 388 sc->sc_bushandle = rman_get_bushandle(sc->sc_mem_res); 389 } else { 390 /* 391 * There's another psycho using the same register space. Copy the 392 * relevant stuff. 393 */ 394 sc->sc_mem_res = NULL; 395 sc->sc_bustag = osc->sc_bustag; 396 sc->sc_bushandle = osc->sc_bushandle; 397 } 398 if (pcictl_offs < sc->sc_basepaddr) 399 panic("psycho_attach: bogus pci control register location"); 400 sc->sc_pcictl = pcictl_offs - sc->sc_basepaddr; 401 csr = PSYCHO_READ8(sc, PSR_CS); 402 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 403 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 404 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 405 406 device_printf(dev, "%s: impl %d, version %d: ign %x ", 407 model, (int)PSYCHO_GCSR_IMPL(csr), (int)PSYCHO_GCSR_VERS(csr), 408 sc->sc_ign); 409 410 /* 411 * Setup the PCI control register 412 */ 413 csr = PCICTL_READ8(sc, PCR_CS); 414 csr |= PCICTL_MRLM | PCICTL_ARB_PARK | PCICTL_ERRINTEN | PCICTL_4ENABLE; 415 csr &= ~(PCICTL_SERR | PCICTL_CPU_PRIO | PCICTL_ARB_PRIO | 416 PCICTL_RTRYWAIT); 417 PCICTL_WRITE8(sc, PCR_CS, csr); 418 419 /* grab the psycho ranges */ 420 psycho_get_ranges(sc->sc_node, &sc->sc_range, &sc->sc_nrange); 421 422 /* get the bus-range for the psycho */ 423 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br)); 424 if (n == -1) 425 panic("could not get psycho bus-range"); 426 if (n != sizeof(psycho_br)) 427 panic("broken psycho bus-range (%d)", n); 428 429 printf("bus range %u to %u; PCI bus %d\n", psycho_br[0], psycho_br[1], 430 psycho_br[0]); 431 432 sc->sc_busno = psycho_br[0]; 433 434 /* Initialize memory and i/o rmans */ 435 sc->sc_io_rman.rm_type = RMAN_ARRAY; 436 sc->sc_io_rman.rm_descr = "Psycho PCI I/O Ports"; 437 if (rman_init(&sc->sc_io_rman) != 0 || 438 rman_manage_region(&sc->sc_io_rman, 0, PSYCHO_IO_SIZE) != 0) 439 panic("psycho_probe: failed to set up i/o rman"); 440 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 441 sc->sc_mem_rman.rm_descr = "Psycho PCI Memory"; 442 if (rman_init(&sc->sc_mem_rman) != 0 || 443 rman_manage_region(&sc->sc_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 444 panic("psycho_probe: failed to set up memory rman"); 445 /* 446 * Find the addresses of the various bus spaces. 447 * There should not be multiple ones of one kind. 448 * The physical start addresses of the ranges are the configuration, 449 * memory and IO handles. 450 */ 451 for (n = 0; n < sc->sc_nrange; n++) { 452 i = UPA_RANGE_CS(&sc->sc_range[n]); 453 if (sc->sc_bh[i] != 0) 454 panic("psycho_attach: duplicate range for space %d", i); 455 sc->sc_bh[i] = UPA_RANGE_PHYS(&sc->sc_range[n]); 456 } 457 /* 458 * Check that all needed handles are present. The PCI_CS_MEM64 one is 459 * not currently used. 460 */ 461 for (n = 0; n < 3; n++) { 462 if (sc->sc_bh[n] == 0) 463 panic("psycho_attach: range %d missing", n); 464 } 465 466 /* allocate our tags */ 467 sc->sc_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 468 sc->sc_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 469 sc->sc_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 470 if (bus_dma_tag_create(sc->sc_dmatag, 8, 1, 0, 0x3ffffffff, NULL, NULL, 471 0x3ffffffff, 0xff, 0xffffffff, 0, &sc->sc_dmat) != 0) 472 panic("psycho_attach: bus_dma_tag_create failed"); 473 /* Customize the tag */ 474 sc->sc_dmat->cookie = sc; 475 sc->sc_dmat->dmamap_create = psycho_dmamap_create; 476 sc->sc_dmat->dmamap_destroy = psycho_dmamap_destroy; 477 sc->sc_dmat->dmamap_load = psycho_dmamap_load; 478 sc->sc_dmat->dmamap_unload = psycho_dmamap_unload; 479 sc->sc_dmat->dmamap_sync = psycho_dmamap_sync; 480 sc->sc_dmat->dmamem_alloc = psycho_dmamem_alloc; 481 sc->sc_dmat->dmamem_free = psycho_dmamem_free; 482 /* XXX: register as root dma tag (kluge). */ 483 sparc64_root_dma_tag = sc->sc_dmat; 484 485 /* Register the softc, this is needed for paired psychos. */ 486 if (psycho_ndevs < sizeof(psycho_softcs) / sizeof(psycho_softcs[0])) 487 psycho_softcs[psycho_ndevs] = sc; 488 else 489 device_printf(dev, "XXX: bump the number of psycho_softcs"); 490 psycho_ndevs++; 491 /* 492 * And finally, if we're a sabre or the first of a pair of psycho's to 493 * arrive here, start up the IOMMU and get a config space tag. 494 */ 495 if (osc == NULL) { 496 /* 497 * Establish handlers for interesting interrupts.... 498 * 499 * XXX We need to remember these and remove this to support 500 * hotplug on the UPA/FHC bus. 501 * 502 * XXX Not all controllers have these, but installing them 503 * is better than trying to sort through this mess. 504 */ 505 psycho_set_intr(sc, 0, dev, PSR_UE_INT_MAP, INTR_FAST, 506 psycho_ue); 507 psycho_set_intr(sc, 1, dev, PSR_CE_INT_MAP, 0, psycho_ce); 508 psycho_set_intr(sc, 2, dev, PSR_PCIAERR_INT_MAP, INTR_FAST, 509 psycho_bus_a); 510 psycho_set_intr(sc, 4, dev, PSR_POWER_INT_MAP, INTR_FAST, 511 psycho_powerfail); 512 /* Psycho-specific initialization. */ 513 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 514 /* 515 * Sabres do not have the following two interrupts. 516 */ 517 psycho_set_intr(sc, 3, dev, PSR_PCIBERR_INT_MAP, 518 INTR_FAST, psycho_bus_b); 519#ifdef PSYCHO_MAP_WAKEUP 520 /* 521 * psycho_wakeup() doesn't do anything useful right 522 * now. 523 */ 524 psycho_set_intr(sc, 5, dev, PSR_PWRMGT_INT_MAP, 0, 525 psycho_wakeup); 526#endif /* PSYCHO_MAP_WAKEUP */ 527 528 /* Initialize the counter-timer. */ 529 sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, 530 PSR_TC0); 531 } 532 533 /* 534 * Setup IOMMU and PCI configuration if we're the first 535 * of a pair of psycho's to arrive here. 536 * 537 * We should calculate a TSB size based on amount of RAM 538 * and number of bus controllers and number an type of 539 * child devices. 540 * 541 * For the moment, 32KB should be more than enough. 542 */ 543 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 544 M_NOWAIT); 545 if (sc->sc_is == NULL) 546 panic("psycho_attach: malloc iommu_state failed"); 547 sc->sc_is->is_sb[0] = 0; 548 sc->sc_is->is_sb[1] = 0; 549 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 550 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 551 psycho_iommu_init(sc, 2); 552 } else { 553 /* Just copy IOMMU state, config tag and address */ 554 sc->sc_is = osc->sc_is; 555 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 556 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 557 iommu_reset(sc->sc_is); 558 } 559 560 /* 561 * Enable all interrupts, clear all interrupt states, and install an 562 * interrupt handler for OBIO interrupts, which can be ISA ones 563 * (to frob the interrupt clear registers). 564 * This aids the debugging of interrupt routing problems, and is needed 565 * for isa drivers that use isa_irq_pending (otherwise the registers 566 * will never be cleared). 567 */ 568#if defined(PSYCHO_DEBUG) || defined(PSYCHO_STRAY) 569 for (map = PSR_PCIA0_INT_MAP, clr = PSR_PCIA0_INT_CLR, n = 0; 570 map <= PSR_PCIB3_INT_MAP; map += 8, clr += 32, n++) { 571 mr = PSYCHO_READ8(sc, map); 572#ifdef PSYCHO_DEBUG 573 device_printf(dev, "intr map (pci) %d: %#lx\n", n, (u_long)mr); 574#endif 575 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 576 for (i = 0; i < 4; i++) 577 PCICTL_WRITE8(sc, clr + i * 8, 0); 578 PSYCHO_WRITE8(sc, map, mr | INTMAP_V); 579 } 580 for (map = PSR_SCSI_INT_MAP, clr = PSR_SCSI_INT_CLR, n = 0; 581 map <= PSR_FFB1_INT_MAP; map += 8, clr += 8, n++) { 582 mr = PSYCHO_READ8(sc, map); 583#ifdef PSYCHO_DEBUG 584 device_printf(dev, "intr map (obio) %d: %#lx, clr: %#lx\n", n, 585 (u_long)mr, (u_long)clr); 586#endif 587 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 588 PSYCHO_WRITE8(sc, clr, 0); 589#ifdef PSYCHO_STRAY 590 /* 591 * This can cause interrupt storms, and is therefore disabled 592 * by default. 593 * XXX: use intr_setup() to not confuse higher level code 594 */ 595 if (INTVEC(mr) != 0x7e6 && INTVEC(mr) != 0x7e7 && 596 INTVEC(mr) != 0) { 597 sclr = malloc(sizeof(*sclr), M_DEVBUF, M_WAITOK); 598 sclr->psc_sc = sc; 599 sclr->psc_clr = clr; 600 intr_setup(PIL_LOW, intr_dequeue, INTVEC(mr), 601 psycho_intr_stray, sclr); 602 } 603#endif 604 PSYCHO_WRITE8(sc, map, mr | INTMAP_V); 605 } 606#endif 607 608 /* 609 * Initialize the interrupt registers of all devices hanging from 610 * the host bridge directly or indirectly via PCI-PCI bridges. 611 * The MI code (and the PCI spec) assume that this is done during 612 * system initialization, however the firmware does not do this 613 * at least on some models, and we probably shouldn't trust that 614 * the firmware uses the same model as this driver if it does. 615 */ 616 ofw_pci_init_intr(dev, sc->sc_node); 617 618 device_add_child(dev, "pci", device_get_unit(dev)); 619 return (bus_generic_attach(dev)); 620} 621 622static void 623psycho_set_intr(struct psycho_softc *sc, int index, 624 device_t dev, bus_addr_t map, int iflags, driver_intr_t handler) 625{ 626 int rid, vec; 627 u_int64_t mr; 628 629 mr = PSYCHO_READ8(sc, map); 630 vec = INTVEC(mr); 631 sc->sc_irq_res[index] = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 632 vec, vec, 1, RF_ACTIVE); 633 if (sc->sc_irq_res[index] == NULL) 634 panic("psycho_set_intr: failed to get interrupt"); 635 bus_setup_intr(dev, sc->sc_irq_res[index], INTR_TYPE_MISC | iflags, 636 handler, sc, &sc->sc_ihand[index]); 637 PSYCHO_WRITE8(sc, map, mr | INTMAP_V); 638} 639 640static int 641psycho_find_intrmap(struct psycho_softc *sc, int ino, bus_addr_t *intrmapptr, 642 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 643{ 644 bus_addr_t intrmap, intrclr; 645 u_int64_t im; 646 u_long diag; 647 int found; 648 649 found = 0; 650 /* Hunt thru obio first */ 651 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 652 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 653 intrmap <= PSR_FFB1_INT_MAP; intrmap += 8, intrclr += 8, 654 diag >>= 2) { 655 im = PSYCHO_READ8(sc, intrmap); 656 if (INTINO(im) == ino) { 657 diag &= 2; 658 found = 1; 659 break; 660 } 661 } 662 663 if (!found) { 664 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 665 /* Now do PCI interrupts */ 666 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 667 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 668 diag >>= 8) { 669 im = PSYCHO_READ8(sc, intrmap); 670 if (((im ^ ino) & 0x3c) == 0) { 671 intrclr += 8 * (ino & 3); 672 diag = (diag >> ((ino & 3) * 2)) & 2; 673 found = 1; 674 break; 675 } 676 } 677 } 678 if (intrmapptr != NULL) 679 *intrmapptr = intrmap; 680 if (intrclrptr != NULL) 681 *intrclrptr = intrclr; 682 if (intrdiagptr != NULL) 683 *intrdiagptr = diag; 684 return (found); 685} 686 687/* grovel the OBP for various psycho properties */ 688static void 689psycho_get_ranges(phandle_t node, struct upa_ranges **rp, int *np) 690{ 691 692 *np = OF_getprop_alloc(node, "ranges", sizeof(**rp), (void **)rp); 693 if (*np == -1) 694 panic("could not get psycho ranges"); 695} 696 697/* 698 * Interrupt handlers. 699 */ 700static void 701psycho_ue(void *arg) 702{ 703 struct psycho_softc *sc = (struct psycho_softc *)arg; 704 u_int64_t afar, afsr; 705 706 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 707 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 708 /* 709 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 710 * the AFAR to be set to the physical address of the TTE entry that 711 * was invalid/write protected. Call into the iommu code to have 712 * them decoded to virtual IO addresses. 713 */ 714 if ((afsr & UEAFSR_P_DTE) != 0) 715 iommu_decode_fault(sc->sc_is, afar); 716 /* It's uncorrectable. Dump the regs and panic. */ 717 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx\n", 718 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 719} 720 721static void 722psycho_ce(void *arg) 723{ 724 struct psycho_softc *sc = (struct psycho_softc *)arg; 725 u_int64_t afar, afsr; 726 727 PSYCHO_WRITE8(sc, PSR_CE_INT_CLR, 0); 728 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 729 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 730 /* It's correctable. Dump the regs and continue. */ 731 printf("%s: correctable DMA error AFAR %#lx AFSR %#lx\n", 732 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 733} 734 735static void 736psycho_bus_a(void *arg) 737{ 738 struct psycho_softc *sc = (struct psycho_softc *)arg; 739 u_int64_t afar, afsr; 740 741 afar = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFA); 742 afsr = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFS); 743 /* It's uncorrectable. Dump the regs and panic. */ 744 panic("%s: PCI bus A error AFAR %#lx AFSR %#lx\n", 745 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 746} 747 748static void 749psycho_bus_b(void *arg) 750{ 751 struct psycho_softc *sc = (struct psycho_softc *)arg; 752 u_int64_t afar, afsr; 753 754 afar = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFA); 755 afsr = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFS); 756 /* It's uncorrectable. Dump the regs and panic. */ 757 panic("%s: PCI bus B error AFAR %#lx AFSR %#lx\n", 758 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 759} 760 761static void 762psycho_powerfail(void *arg) 763{ 764 765 /* We lost power. Try to shut down NOW. */ 766#ifdef DEBUGGER_ON_POWERFAIL 767 struct psycho_softc *sc = (struct psycho_softc *)arg; 768 769 Debugger("powerfail"); 770 PSYCHO_WRITE8(sc, PSR_POWER_INT_CLR, 0); 771#else 772 printf("Power Failure Detected: Shutting down NOW.\n"); 773 shutdown_nice(0); 774#endif 775} 776 777#ifdef PSYCHO_MAP_WAKEUP 778static void 779psycho_wakeup(void *arg) 780{ 781 struct psycho_softc *sc = (struct psycho_softc *)arg; 782 783 PSYCHO_WRITE8(sc, PSR_PWRMGT_INT_CLR, 0); 784 /* Gee, we don't really have a framework to deal with this properly. */ 785 printf("%s: power management wakeup\n", device_get_name(sc->sc_dev)); 786} 787#endif /* PSYCHO_MAP_WAKEUP */ 788 789/* initialise the IOMMU... */ 790void 791psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 792{ 793 char *name; 794 struct iommu_state *is = sc->sc_is; 795 u_int32_t iobase = -1; 796 int *vdma = NULL; 797 int nitem; 798 799 /* punch in our copies */ 800 is->is_bustag = sc->sc_bustag; 801 is->is_bushandle = sc->sc_bushandle; 802 is->is_iommu = PSR_IOMMU; 803 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 804 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 805 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 806 is->is_dva = PSR_IOMMU_SVADIAG; 807 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 808 809 /* 810 * Separate the men from the boys. Get the `virtual-dma' 811 * property for sabre and use that to make sure the damn 812 * iommu works. 813 * 814 * We could query the `#virtual-dma-size-cells' and 815 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 816 */ 817 nitem = OF_getprop_alloc(sc->sc_node, "virtual-dma", sizeof(vdma), 818 (void **)&vdma); 819 if (nitem > 0) { 820 iobase = vdma[0]; 821 tsbsize = ffs(vdma[1]); 822 if (tsbsize < 25 || tsbsize > 31 || 823 (vdma[1] & ~(1 << (tsbsize - 1))) != 0) { 824 printf("bogus tsb size %x, using 7\n", vdma[1]); 825 tsbsize = 31; 826 } 827 tsbsize -= 24; 828 free(vdma, M_OFWPROP); 829 } 830 831 /* give us a nice name.. */ 832 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 833 if (name == 0) 834 panic("couldn't malloc iommu name"); 835 snprintf(name, 32, "%s dvma", device_get_name(sc->sc_dev)); 836 837 iommu_init(name, is, tsbsize, iobase); 838} 839 840static int 841psycho_maxslots(device_t dev) 842{ 843 844 /* 845 * XXX: is this correct? At any rate, a number that is too high 846 * shouldn't do any harm, if only because of the way things are 847 * handled in psycho_read_config. 848 */ 849 return (31); 850} 851 852/* 853 * Keep a table of quirky PCI devices that need fixups before the MI PCI code 854 * creates the resource lists. This needs to be moved around once other bus 855 * drivers are added. Moving it to the MI code should maybe be reconsidered 856 * if one of these devices appear in non-sparc64 boxen. It's likely that not 857 * all BIOSes/firmwares can deal with them. 858 */ 859struct psycho_dquirk { 860 u_int32_t dq_devid; 861 int dq_quirk; 862}; 863 864/* Quirk types. May be or'ed together. */ 865#define DQT_BAD_INTPIN 1 /* Intpin reg 0, but intpin used */ 866 867static struct psycho_dquirk dquirks[] = { 868 { 0x1001108e, DQT_BAD_INTPIN }, /* Sun HME (PCIO func. 1) */ 869 { 0x1101108e, DQT_BAD_INTPIN }, /* Sun GEM (PCIO2 func. 1) */ 870 { 0x1102108e, DQT_BAD_INTPIN }, /* Sun FireWire ctl. (PCIO2 func. 2) */ 871 { 0x1103108e, DQT_BAD_INTPIN }, /* Sun USB ctl. (PCIO2 func. 3) */ 872}; 873 874#define NDQUIRKS (sizeof(dquirks) / sizeof(dquirks[0])) 875 876static u_int32_t 877psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 878 int width) 879{ 880 struct psycho_softc *sc; 881 bus_space_handle_t bh; 882 u_long offset = 0; 883 u_int32_t r, devid; 884 int i; 885 886 /* 887 * The psycho bridge does not tolerate accesses to unconfigured PCI 888 * devices' or function's config space, so look up the device in the 889 * firmware device tree first, and if it is not present, return a value 890 * that will make the detection code think that there is no device here. 891 * This is ugly... 892 */ 893 if (reg == 0 && ofw_pci_find_node(bus, slot, func) == 0) 894 return (0xffffffff); 895 sc = (struct psycho_softc *)device_get_softc(dev); 896 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 897 bh = sc->sc_bh[PCI_CS_CONFIG]; 898 switch (width) { 899 case 1: 900 r = bus_space_read_1(sc->sc_cfgt, bh, offset); 901 break; 902 case 2: 903 r = bus_space_read_2(sc->sc_cfgt, bh, offset); 904 break; 905 case 4: 906 r = bus_space_read_4(sc->sc_cfgt, bh, offset); 907 break; 908 default: 909 panic("psycho_read_config: bad width"); 910 } 911 if (reg == PCIR_INTPIN && r == 0) { 912 /* Check for DQT_BAD_INTPIN quirk. */ 913 devid = psycho_read_config(dev, bus, slot, func, 914 PCIR_DEVVENDOR, 4); 915 for (i = 0; i < NDQUIRKS; i++) { 916 if (dquirks[i].dq_devid == devid) { 917 /* 918 * Need to set the intpin to a value != 0 so 919 * that the MI code will think that this device 920 * has an interrupt. 921 * Just use 1 (intpin a) for now. This is, of 922 * course, bogus, but since interrupts are 923 * routed in advance, this does not really 924 * matter. 925 */ 926 if ((dquirks[i].dq_quirk & DQT_BAD_INTPIN) != 0) 927 r = 1; 928 break; 929 } 930 } 931 } 932 return (r); 933} 934 935static void 936psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, 937 u_int reg, u_int32_t val, int width) 938{ 939 struct psycho_softc *sc; 940 bus_space_handle_t bh; 941 u_long offset = 0; 942 943 sc = (struct psycho_softc *)device_get_softc(dev); 944 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 945 bh = sc->sc_bh[PCI_CS_CONFIG]; 946 switch (width) { 947 case 1: 948 bus_space_write_1(sc->sc_cfgt, bh, offset, val); 949 break; 950 case 2: 951 bus_space_write_2(sc->sc_cfgt, bh, offset, val); 952 break; 953 case 4: 954 bus_space_write_4(sc->sc_cfgt, bh, offset, val); 955 break; 956 default: 957 panic("psycho_write_config: bad width"); 958 } 959} 960 961static int 962psycho_route_interrupt(device_t bus, device_t dev, int pin) 963{ 964 int intline; 965 966 /* 967 * XXX: ugly loathsome hack: 968 * We can't use ofw_pci_route_intr() here; the device passed may be 969 * the one of a bridge, so the original device can't be recovered. 970 * 971 * We need to use the firmware to route interrupts, however it has 972 * no interface which could be used to interpret intpins; instead, 973 * all assignments are done by device. 974 * 975 * The MI pci code will try to reroute interrupts of 0, although they 976 * are correct; all other interrupts are preinitialized, so if we 977 * get here, the intline is either 0 (so return 0), or we hit a 978 * device which was not preinitialized (e.g. hotplugged stuff), in 979 * which case we are lost. 980 */ 981 return (0); 982} 983 984static int 985psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 986{ 987 struct psycho_softc *sc; 988 989 sc = (struct psycho_softc *)device_get_softc(dev); 990 switch (which) { 991 case PCIB_IVAR_BUS: 992 *result = sc->sc_busno; 993 return (0); 994 } 995 return (ENOENT); 996} 997 998/* Write to the correct clr register, and call the actual handler. */ 999static void 1000psycho_intr_stub(void *arg) 1001{ 1002 struct psycho_clr *pc; 1003 1004 pc = (struct psycho_clr *)arg; 1005 pc->pci_handler(pc->pci_arg); 1006 PSYCHO_WRITE8(pc->pci_sc, pc->pci_clr, 0); 1007} 1008 1009#ifdef PSYCHO_STRAY 1010/* 1011 * Write to the correct clr register and return. arg is the address of the clear 1012 * register to be used. 1013 * XXX: print a message? 1014 */ 1015static void 1016psycho_intr_stray(void *arg) 1017{ 1018 struct psycho_strayclr *sclr = arg; 1019 1020 PSYCHO_WRITE8(sclr->psc_sc, sclr->psc_clr, 0); 1021} 1022#endif 1023 1024static int 1025psycho_setup_intr(device_t dev, device_t child, 1026 struct resource *ires, int flags, driver_intr_t *intr, void *arg, 1027 void **cookiep) 1028{ 1029 struct psycho_softc *sc; 1030 struct psycho_clr *pc; 1031 bus_addr_t intrmapptr, intrclrptr; 1032 long vec = rman_get_start(ires); 1033 u_int64_t mr; 1034 int ino, error; 1035 1036 sc = (struct psycho_softc *)device_get_softc(dev); 1037 pc = (struct psycho_clr *)malloc(sizeof(*pc), M_DEVBUF, M_NOWAIT); 1038 if (pc == NULL) 1039 return (NULL); 1040 1041 /* 1042 * Hunt through all the interrupt mapping regs to look for our 1043 * interrupt vector. 1044 * 1045 * XXX We only compare INOs rather than IGNs since the firmware may 1046 * not provide the IGN and the IGN is constant for all device on that 1047 * PCI controller. This could cause problems for the FFB/external 1048 * interrupt which has a full vector that can be set arbitrarily. 1049 */ 1050 ino = INTINO(vec); 1051 1052 if (!psycho_find_intrmap(sc, ino, &intrmapptr, &intrclrptr, NULL)) { 1053 printf("Cannot find interrupt vector %lx\n", vec); 1054 free(pc, M_DEVBUF); 1055 return (NULL); 1056 } 1057 1058#ifdef PSYCHO_DEBUG 1059 device_printf(dev, "psycho_setup_intr: INO %d, map %#lx, clr %#lx\n", 1060 ino, (u_long)intrmapptr, (u_long)intrclrptr); 1061#endif 1062 pc->pci_sc = sc; 1063 pc->pci_arg = arg; 1064 pc->pci_handler = intr; 1065 pc->pci_clr = intrclrptr; 1066 /* Disable the interrupt while we fiddle with it */ 1067 mr = PSYCHO_READ8(sc, intrmapptr); 1068 PSYCHO_WRITE8(sc, intrmapptr, mr & ~INTMAP_V); 1069 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 1070 psycho_intr_stub, pc, cookiep); 1071 if (error != 0) { 1072 free(pc, M_DEVBUF); 1073 return (error); 1074 } 1075 pc->pci_cookie = *cookiep; 1076 *cookiep = pc; 1077 1078 /* 1079 * Clear the interrupt, it might have been triggered before it was 1080 * set up. 1081 */ 1082 PSYCHO_WRITE8(sc, intrclrptr, 0); 1083 /* 1084 * Enable the interrupt now we have the handler installed. 1085 * Read the current value as we can't change it besides the 1086 * valid bit so so make sure only this bit is changed. 1087 */ 1088 PSYCHO_WRITE8(sc, intrmapptr, mr | INTMAP_V); 1089 return (error); 1090} 1091 1092static int 1093psycho_teardown_intr(device_t dev, device_t child, 1094 struct resource *vec, void *cookie) 1095{ 1096 struct psycho_clr *pc; 1097 int error; 1098 1099 pc = (struct psycho_clr *)cookie; 1100 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 1101 pc->pci_cookie); 1102 /* 1103 * Don't disable the interrupt for now, so that stray interupts get 1104 * detected... 1105 */ 1106 if (error != 0) 1107 free(pc, M_DEVBUF); 1108 return (error); 1109} 1110 1111static struct resource * 1112psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1113 u_long start, u_long end, u_long count, u_int flags) 1114{ 1115 struct psycho_softc *sc; 1116 struct resource *rv; 1117 struct rman *rm; 1118 bus_space_tag_t bt; 1119 bus_space_handle_t bh; 1120 int needactivate = flags & RF_ACTIVE; 1121 1122 flags &= ~RF_ACTIVE; 1123 1124 sc = (struct psycho_softc *)device_get_softc(bus); 1125 if (type == SYS_RES_IRQ) { 1126 /* 1127 * XXX: Don't accept blank ranges for now, only single 1128 * interrupts. The other case should not happen with the MI pci 1129 * code... 1130 * XXX: This may return a resource that is out of the range 1131 * that was specified. Is this correct...? 1132 */ 1133 if (start != end) 1134 panic("psycho_alloc_resource: XXX: interrupt range"); 1135 start = end |= sc->sc_ign; 1136 return (bus_alloc_resource(bus, type, rid, start, end, 1137 count, flags)); 1138 } 1139 switch (type) { 1140 case SYS_RES_MEMORY: 1141 rm = &sc->sc_mem_rman; 1142 bt = sc->sc_memt; 1143 bh = sc->sc_bh[PCI_CS_MEM32]; 1144 break; 1145 case SYS_RES_IOPORT: 1146 rm = &sc->sc_io_rman; 1147 bt = sc->sc_iot; 1148 /* XXX: probably should use ranges property here. */ 1149 bh = sc->sc_bh[PCI_CS_IO]; 1150 break; 1151 default: 1152 return (NULL); 1153 } 1154 1155 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1156 if (rv == NULL) 1157 return (NULL); 1158 1159 bh += rman_get_start(rv); 1160 rman_set_bustag(rv, bt); 1161 rman_set_bushandle(rv, bh); 1162 1163 if (needactivate) { 1164 if (bus_activate_resource(child, type, *rid, rv)) { 1165 rman_release_resource(rv); 1166 return (NULL); 1167 } 1168 } 1169 1170 return (rv); 1171} 1172 1173static int 1174psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1175 struct resource *r) 1176{ 1177 void *p; 1178 int error; 1179 1180 if (type == SYS_RES_IRQ) 1181 return (bus_activate_resource(bus, type, rid, r)); 1182 if (type == SYS_RES_MEMORY) { 1183 /* 1184 * Need to memory-map the device space, as some drivers depend 1185 * on the virtual address being set and useable. 1186 */ 1187 error = sparc64_bus_mem_map(rman_get_bustag(r), 1188 rman_get_bushandle(r), rman_get_size(r), 0, NULL, &p); 1189 if (error != 0) 1190 return (error); 1191 rman_set_virtual(r, p); 1192 } 1193 return (rman_activate_resource(r)); 1194} 1195 1196static int 1197psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1198 struct resource *r) 1199{ 1200 1201 if (type == SYS_RES_IRQ) 1202 return (bus_deactivate_resource(bus, type, rid, r)); 1203 if (type == SYS_RES_MEMORY) { 1204 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1205 rman_set_virtual(r, NULL); 1206 } 1207 return (rman_deactivate_resource(r)); 1208} 1209 1210static int 1211psycho_release_resource(device_t bus, device_t child, int type, int rid, 1212 struct resource *r) 1213{ 1214 int error; 1215 1216 if (type == SYS_RES_IRQ) 1217 return (bus_release_resource(bus, type, rid, r)); 1218 if (rman_get_flags(r) & RF_ACTIVE) { 1219 error = bus_deactivate_resource(child, type, rid, r); 1220 if (error) 1221 return error; 1222 } 1223 return (rman_release_resource(r)); 1224} 1225 1226static int 1227psycho_intr_pending(device_t dev, int intr) 1228{ 1229 struct psycho_softc *sc; 1230 u_long diag; 1231 1232 sc = (struct psycho_softc *)device_get_softc(dev); 1233 if (!psycho_find_intrmap(sc, intr, NULL, NULL, &diag)) { 1234 printf("psycho_intr_pending: mapping not found for %d\n", intr); 1235 return (0); 1236 } 1237 return (diag != 0); 1238} 1239 1240static bus_space_handle_t 1241psycho_get_bus_handle(device_t dev, enum sbbt_id id, 1242 bus_space_handle_t childhdl, bus_space_tag_t *tag) 1243{ 1244 struct psycho_softc *sc; 1245 1246 sc = (struct psycho_softc *)device_get_softc(dev); 1247 switch(id) { 1248 case SBBT_IO: 1249 *tag = sc->sc_iot; 1250 return (sc->sc_bh[PCI_CS_IO] + childhdl); 1251 case SBBT_MEM: 1252 *tag = sc->sc_memt; 1253 return (sc->sc_bh[PCI_CS_MEM32] + childhdl); 1254 default: 1255 panic("psycho_get_bus_handle: illegal space\n"); 1256 } 1257} 1258 1259/* 1260 * below here is bus space and bus dma support 1261 */ 1262static bus_space_tag_t 1263psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1264{ 1265 bus_space_tag_t bt; 1266 1267 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1268 M_NOWAIT | M_ZERO); 1269 if (bt == NULL) 1270 panic("psycho_alloc_bus_tag: out of memory"); 1271 1272 bzero(bt, sizeof *bt); 1273 bt->cookie = sc; 1274 bt->parent = sc->sc_bustag; 1275 bt->type = type; 1276 return (bt); 1277} 1278 1279/* 1280 * hooks into the iommu dvma calls. 1281 */ 1282static int 1283psycho_dmamem_alloc(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void **vaddr, 1284 int flags, bus_dmamap_t *mapp) 1285{ 1286 struct psycho_softc *sc; 1287 1288 sc = (struct psycho_softc *)pdmat->cookie; 1289 return (iommu_dvmamem_alloc(pdmat, ddmat, sc->sc_is, vaddr, flags, 1290 mapp)); 1291} 1292 1293static void 1294psycho_dmamem_free(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void *vaddr, 1295 bus_dmamap_t map) 1296{ 1297 struct psycho_softc *sc; 1298 1299 sc = (struct psycho_softc *)pdmat->cookie; 1300 iommu_dvmamem_free(pdmat, ddmat, sc->sc_is, vaddr, map); 1301} 1302 1303static int 1304psycho_dmamap_create(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, int flags, 1305 bus_dmamap_t *mapp) 1306{ 1307 struct psycho_softc *sc; 1308 1309 sc = (struct psycho_softc *)pdmat->cookie; 1310 return (iommu_dvmamap_create(pdmat, ddmat, sc->sc_is, flags, mapp)); 1311 1312} 1313 1314static int 1315psycho_dmamap_destroy(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, 1316 bus_dmamap_t map) 1317{ 1318 struct psycho_softc *sc; 1319 1320 sc = (struct psycho_softc *)pdmat->cookie; 1321 return (iommu_dvmamap_destroy(pdmat, ddmat, sc->sc_is, map)); 1322} 1323 1324static int 1325psycho_dmamap_load(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map, 1326 void *buf, bus_size_t buflen, bus_dmamap_callback_t *callback, 1327 void *callback_arg, int flags) 1328{ 1329 struct psycho_softc *sc; 1330 1331 sc = (struct psycho_softc *)pdmat->cookie; 1332 return (iommu_dvmamap_load(pdmat, ddmat, sc->sc_is, map, buf, buflen, 1333 callback, callback_arg, flags)); 1334} 1335 1336static void 1337psycho_dmamap_unload(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map) 1338{ 1339 struct psycho_softc *sc; 1340 1341 sc = (struct psycho_softc *)pdmat->cookie; 1342 iommu_dvmamap_unload(pdmat, ddmat, sc->sc_is, map); 1343} 1344 1345static void 1346psycho_dmamap_sync(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map, 1347 bus_dmasync_op_t op) 1348{ 1349 struct psycho_softc *sc; 1350 1351 sc = (struct psycho_softc *)pdmat->cookie; 1352 iommu_dvmamap_sync(pdmat, ddmat, sc->sc_is, map, op); 1353} 1354