psycho.c revision 93070
1/* 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * All rights reserved. 4 * Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 30 * 31 * $FreeBSD: head/sys/sparc64/pci/psycho.c 93070 2002-03-24 02:50:53Z tmm $ 32 */ 33 34/* 35 * Support for `psycho' and `psycho+' UPA to PCI bridge and 36 * UltraSPARC IIi and IIe `sabre' PCI controllers. 37 */ 38 39#include "opt_psycho.h" 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/kernel.h> 45#include <sys/malloc.h> 46 47#include <ofw/openfirm.h> 48#include <ofw/ofw_pci.h> 49 50#include <machine/bus.h> 51#include <machine/iommureg.h> 52#include <machine/bus_common.h> 53#include <machine/frame.h> 54#include <machine/intr_machdep.h> 55#include <machine/nexusvar.h> 56#include <machine/ofw_upa.h> 57#include <machine/resource.h> 58 59#include <sys/rman.h> 60 61#include <machine/iommuvar.h> 62 63#include <pci/pcivar.h> 64#include <pci/pcireg.h> 65 66#include <sparc64/pci/ofw_pci.h> 67#include <sparc64/pci/psychoreg.h> 68#include <sparc64/pci/psychovar.h> 69 70#include "pcib_if.h" 71#include "sparcbus_if.h" 72 73static void psycho_get_ranges(phandle_t, struct upa_ranges **, int *); 74static void psycho_set_intr(struct psycho_softc *, int, device_t, bus_addr_t, 75 int, driver_intr_t); 76static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *, 77 bus_addr_t *, u_long *); 78static void psycho_intr_stub(void *); 79#ifdef PSYCHO_STRAY 80static void psycho_intr_stray(void *); 81#endif 82static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 83 84 85/* Interrupt handlers */ 86static void psycho_ue(void *); 87static void psycho_ce(void *); 88static void psycho_bus_a(void *); 89static void psycho_bus_b(void *); 90static void psycho_powerfail(void *); 91#ifdef PSYCHO_MAP_WAKEUP 92static void psycho_wakeup(void *); 93#endif 94 95/* IOMMU support */ 96static void psycho_iommu_init(struct psycho_softc *, int); 97 98/* 99 * bus space and bus dma support for UltraSPARC `psycho'. note that most 100 * of the bus dma support is provided by the iommu dvma controller. 101 */ 102static int psycho_dmamap_create(bus_dma_tag_t, bus_dma_tag_t, int, 103 bus_dmamap_t *); 104static int psycho_dmamap_destroy(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 105static int psycho_dmamap_load(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 106 void *, bus_size_t, bus_dmamap_callback_t *, void *, int); 107static void psycho_dmamap_unload(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 108static void psycho_dmamap_sync(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 109 bus_dmasync_op_t); 110static int psycho_dmamem_alloc(bus_dma_tag_t, bus_dma_tag_t, void **, int, 111 bus_dmamap_t *); 112static void psycho_dmamem_free(bus_dma_tag_t, bus_dma_tag_t, void *, 113 bus_dmamap_t); 114 115/* 116 * autoconfiguration 117 */ 118static int psycho_probe(device_t); 119static int psycho_attach(device_t); 120static int psycho_read_ivar(device_t, device_t, int, u_long *); 121static int psycho_setup_intr(device_t, device_t, struct resource *, int, 122 driver_intr_t *, void *, void **); 123static int psycho_teardown_intr(device_t, device_t, struct resource *, void *); 124static struct resource *psycho_alloc_resource(device_t, device_t, int, int *, 125 u_long, u_long, u_long, u_int); 126static int psycho_activate_resource(device_t, device_t, int, int, 127 struct resource *); 128static int psycho_deactivate_resource(device_t, device_t, int, int, 129 struct resource *); 130static int psycho_release_resource(device_t, device_t, int, int, 131 struct resource *); 132static int psycho_maxslots(device_t); 133static u_int32_t psycho_read_config(device_t, u_int, u_int, u_int, u_int, int); 134static void psycho_write_config(device_t, u_int, u_int, u_int, u_int, u_int32_t, 135 int); 136static int psycho_route_interrupt(device_t, device_t, int); 137static int psycho_intr_pending(device_t, int); 138static bus_space_handle_t psycho_get_bus_handle(device_t dev, enum sbbt_id id, 139 bus_space_handle_t childhdl, bus_space_tag_t *tag); 140 141static device_method_t psycho_methods[] = { 142 /* Device interface */ 143 DEVMETHOD(device_probe, psycho_probe), 144 DEVMETHOD(device_attach, psycho_attach), 145 146 /* Bus interface */ 147 DEVMETHOD(bus_print_child, bus_generic_print_child), 148 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 149 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 150 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 151 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 152 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 153 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 154 DEVMETHOD(bus_release_resource, psycho_release_resource), 155 156 /* pcib interface */ 157 DEVMETHOD(pcib_maxslots, psycho_maxslots), 158 DEVMETHOD(pcib_read_config, psycho_read_config), 159 DEVMETHOD(pcib_write_config, psycho_write_config), 160 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 161 162 /* sparcbus interface */ 163 DEVMETHOD(sparcbus_intr_pending, psycho_intr_pending), 164 DEVMETHOD(sparcbus_get_bus_handle, psycho_get_bus_handle), 165 166 { 0, 0 } 167}; 168 169static driver_t psycho_driver = { 170 "pcib", 171 psycho_methods, 172 sizeof(struct psycho_softc), 173}; 174 175static devclass_t psycho_devclass; 176 177DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 178 179static int psycho_ndevs; 180static struct psycho_softc *psycho_softcs[4]; 181 182struct psycho_clr { 183 struct psycho_softc *pci_sc; 184 bus_addr_t pci_clr; /* clear register */ 185 driver_intr_t *pci_handler; /* handler to call */ 186 void *pci_arg; /* argument for the handler */ 187 void *pci_cookie; /* interrupt cookie of parent bus */ 188}; 189 190struct psycho_strayclr { 191 struct psycho_softc *psc_sc; 192 bus_addr_t psc_clr; /* clear register */ 193}; 194 195#define PSYCHO_READ8(sc, off) \ 196 bus_space_read_8((sc)->sc_bustag, (sc)->sc_bushandle, (off)) 197#define PSYCHO_WRITE8(sc, off, v) \ 198 bus_space_write_8((sc)->sc_bustag, (sc)->sc_bushandle, (off), (v)) 199#define PCICTL_READ8(sc, off) \ 200 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 201#define PCICTL_WRITE8(sc, off, v) \ 202 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 203 204/* 205 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 206 * single PCI bus and does not have a streaming buffer. It often has an APB 207 * (advanced PCI bridge) connected to it, which was designed specifically for 208 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 209 * appears as two "simba"'s underneath the sabre. 210 * 211 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 212 * and manages two PCI buses. "psycho" has two 64-bit 33MHz buses, while 213 * "psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 214 * will usually find a "psycho+" since I don't think the original "psycho" 215 * ever shipped, and if it did it would be in the U30. 216 * 217 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 218 * both part of the same IC, they only have a single register space. As such, 219 * they need to be configured together, even though the autoconfiguration will 220 * attach them separately. 221 * 222 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 223 * as pci1 and pci2, although they have been implemented with other PCI bus 224 * numbers on some machines. 225 * 226 * On UltraII machines, there can be any number of "psycho+" ICs, each 227 * providing two PCI buses. 228 * 229 * 230 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 231 * the values of the following interrupts in this order: 232 * 233 * PCI Bus Error (30) 234 * DMA UE (2e) 235 * DMA CE (2f) 236 * Power Fail (25) 237 * 238 * We really should attach handlers for each. 239 */ 240#define OFW_PCI_TYPE "pci" 241#define OFW_SABRE_MODEL "SUNW,sabre" 242#define OFW_SABRE_COMPAT "pci108e,a001" 243#define OFW_SIMBA_MODEL "SUNW,simba" 244#define OFW_PSYCHO_MODEL "SUNW,psycho" 245 246static int 247psycho_probe(device_t dev) 248{ 249 phandle_t node; 250 char *dtype, *model; 251 static char compat[32]; 252 253 node = nexus_get_node(dev); 254 if (OF_getprop(node, "compatible", compat, sizeof(compat)) == -1) 255 compat[0] = '\0'; 256 257 dtype = nexus_get_device_type(dev); 258 model = nexus_get_model(dev); 259 /* match on a type of "pci" and a sabre or a psycho */ 260 if (nexus_get_reg(dev) != NULL && dtype != NULL && 261 strcmp(dtype, OFW_PCI_TYPE) == 0 && 262 ((model != NULL && (strcmp(model, OFW_SABRE_MODEL) == 0 || 263 strcmp(model, OFW_PSYCHO_MODEL) == 0)) || 264 strcmp(compat, OFW_SABRE_COMPAT) == 0)) { 265 device_set_desc(dev, "U2P UPA-PCI bridge"); 266 return (0); 267 } 268 269 return (ENXIO); 270} 271 272/* 273 * SUNW,psycho initialisation .. 274 * - find the per-psycho registers 275 * - figure out the IGN. 276 * - find our partner psycho 277 * - configure ourselves 278 * - bus range, bus, 279 * - interrupt map, 280 * - setup the chipsets. 281 * - if we're the first of the pair, initialise the IOMMU, otherwise 282 * just copy it's tags and addresses. 283 */ 284static int 285psycho_attach(device_t dev) 286{ 287 struct psycho_softc *sc; 288 struct psycho_softc *osc = NULL; 289 struct psycho_softc *asc; 290 struct upa_regs *reg; 291 char compat[32]; 292 char *model; 293 phandle_t node; 294 u_int64_t csr; 295 u_long pcictl_offs, mlen; 296 int psycho_br[2]; 297 int n, i, nreg, rid; 298#if defined(PSYCHO_DEBUG) || defined(PSYCHO_STRAY) 299 bus_addr_t map, clr; 300 u_int64_t mr; 301#endif 302#ifdef PSYCHO_STRAY 303 struct psycho_strayclr *sclr; 304#endif 305 306 node = nexus_get_node(dev); 307 sc = device_get_softc(dev); 308 if (OF_getprop(node, "compatible", compat, sizeof(compat)) == -1) 309 compat[0] = '\0'; 310 311 sc->sc_node = node; 312 sc->sc_dev = dev; 313 sc->sc_dmatag = nexus_get_dmatag(dev); 314 315 /* 316 * call the model-specific initialisation routine. 317 */ 318 model = nexus_get_model(dev); 319 if ((model != NULL && 320 strcmp(model, OFW_SABRE_MODEL) == 0) || 321 strcmp(compat, OFW_SABRE_COMPAT) == 0) { 322 sc->sc_mode = PSYCHO_MODE_SABRE; 323 if (model == NULL) 324 model = "sabre"; 325 } else if (model != NULL && 326 strcmp(model, OFW_PSYCHO_MODEL) == 0) 327 sc->sc_mode = PSYCHO_MODE_PSYCHO; 328 else 329 panic("psycho_attach: unknown model!"); 330 331 /* 332 * The psycho gets three register banks: 333 * (0) per-PBM configuration and status registers 334 * (1) per-PBM PCI configuration space, containing only the 335 * PBM 256-byte PCI header 336 * (2) the shared psycho configuration registers (struct psychoreg) 337 * 338 * XXX use the prom address for the psycho registers? we do so far. 339 */ 340 reg = nexus_get_reg(dev); 341 nreg = nexus_get_nreg(dev); 342 /* Register layouts are different. stuupid. */ 343 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 344 if (nreg <= 2) 345 panic("psycho_attach: %d not enough registers", nreg); 346 sc->sc_basepaddr = (vm_offset_t)UPA_REG_PHYS(®[2]); 347 mlen = UPA_REG_SIZE(®[2]); 348 pcictl_offs = UPA_REG_PHYS(®[0]); 349 } else { 350 if (nreg <= 0) 351 panic("psycho_attach: %d not enough registers", nreg); 352 sc->sc_basepaddr = (vm_offset_t)UPA_REG_PHYS(®[0]); 353 mlen = UPA_REG_SIZE(reg); 354 pcictl_offs = sc->sc_basepaddr + PSR_PCICTL0; 355 } 356 357 /* 358 * Match other psycho's that are already configured against 359 * the base physical address. This will be the same for a 360 * pair of devices that share register space. 361 */ 362 for (n = 0; n < psycho_ndevs && n < sizeof(psycho_softcs) / 363 sizeof(psycho_softcs[0]); n++) { 364 asc = (struct psycho_softc *)psycho_softcs[n]; 365 366 if (asc == NULL || asc == sc) 367 /* This entry is not there or it is me */ 368 continue; 369 370 if (asc->sc_basepaddr != sc->sc_basepaddr) 371 /* This is an unrelated psycho */ 372 continue; 373 374 /* Found partner */ 375 osc = asc; 376 break; 377 } 378 379 if (osc == NULL) { 380 rid = 0; 381 sc->sc_mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 382 sc->sc_basepaddr, sc->sc_basepaddr + mlen - 1, mlen, 383 RF_ACTIVE); 384 if (sc->sc_mem_res == NULL || 385 rman_get_start(sc->sc_mem_res) != sc->sc_basepaddr) 386 panic("psycho_attach: can't allocate device memory"); 387 sc->sc_bustag = rman_get_bustag(sc->sc_mem_res); 388 sc->sc_bushandle = rman_get_bushandle(sc->sc_mem_res); 389 } else { 390 /* 391 * There's another psycho using the same register space. Copy the 392 * relevant stuff. 393 */ 394 sc->sc_mem_res = NULL; 395 sc->sc_bustag = osc->sc_bustag; 396 sc->sc_bushandle = osc->sc_bushandle; 397 } 398 if (pcictl_offs < sc->sc_basepaddr) 399 panic("psycho_attach: bogus pci control register location"); 400 sc->sc_pcictl = pcictl_offs - sc->sc_basepaddr; 401 csr = PSYCHO_READ8(sc, PSR_CS); 402 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 403 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 404 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 405 406 device_printf(dev, "%s: impl %d, version %d: ign %x ", 407 model, (int)PSYCHO_GCSR_IMPL(csr), (int)PSYCHO_GCSR_VERS(csr), 408 sc->sc_ign); 409 410 /* 411 * Setup the PCI control register 412 */ 413 csr = PCICTL_READ8(sc, PCR_CS); 414 csr |= PCICTL_MRLM | PCICTL_ARB_PARK | PCICTL_ERRINTEN | PCICTL_4ENABLE; 415 csr &= ~(PCICTL_SERR | PCICTL_CPU_PRIO | PCICTL_ARB_PRIO | 416 PCICTL_RTRYWAIT); 417 PCICTL_WRITE8(sc, PCR_CS, csr); 418 419 /* grab the psycho ranges */ 420 psycho_get_ranges(sc->sc_node, &sc->sc_range, &sc->sc_nrange); 421 422 /* get the bus-range for the psycho */ 423 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br)); 424 if (n == -1) 425 panic("could not get psycho bus-range"); 426 if (n != sizeof(psycho_br)) 427 panic("broken psycho bus-range (%d)", n); 428 429 printf("bus range %u to %u; PCI bus %d\n", psycho_br[0], psycho_br[1], 430 psycho_br[0]); 431 432 sc->sc_busno = psycho_br[0]; 433 434 /* Initialize memory and i/o rmans */ 435 sc->sc_io_rman.rm_type = RMAN_ARRAY; 436 sc->sc_io_rman.rm_descr = "Psycho PCI I/O Ports"; 437 if (rman_init(&sc->sc_io_rman) != 0 || 438 rman_manage_region(&sc->sc_io_rman, 0, PSYCHO_IO_SIZE) != 0) 439 panic("psycho_probe: failed to set up i/o rman"); 440 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 441 sc->sc_mem_rman.rm_descr = "Psycho PCI Memory"; 442 if (rman_init(&sc->sc_mem_rman) != 0 || 443 rman_manage_region(&sc->sc_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 444 panic("psycho_probe: failed to set up memory rman"); 445 /* 446 * Find the addresses of the various bus spaces. 447 * There should not be multiple ones of one kind. 448 * The physical start addresses of the ranges are the configuration, 449 * memory and IO handles. 450 */ 451 for (n = 0; n < sc->sc_nrange; n++) { 452 i = UPA_RANGE_CS(&sc->sc_range[n]); 453 if (sc->sc_bh[i] != 0) 454 panic("psycho_attach: duplicate range for space %d", i); 455 sc->sc_bh[i] = UPA_RANGE_PHYS(&sc->sc_range[n]); 456 } 457 /* 458 * Check that all needed handles are present. The PCI_CS_MEM64 one is 459 * not currently used. 460 */ 461 for (n = 0; n < 3; n++) { 462 if (sc->sc_bh[n] == 0) 463 panic("psycho_attach: range %d missing", n); 464 } 465 466 /* allocate our tags */ 467 sc->sc_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 468 sc->sc_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 469 sc->sc_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 470 if (bus_dma_tag_create(sc->sc_dmatag, 8, 1, 0, 0x3ffffffff, NULL, NULL, 471 0x3ffffffff, 0xff, 0xffffffff, 0, &sc->sc_dmat) != 0) 472 panic("psycho_attach: bus_dma_tag_create failed"); 473 /* Customize the tag */ 474 sc->sc_dmat->cookie = sc; 475 sc->sc_dmat->dmamap_create = psycho_dmamap_create; 476 sc->sc_dmat->dmamap_destroy = psycho_dmamap_destroy; 477 sc->sc_dmat->dmamap_load = psycho_dmamap_load; 478 sc->sc_dmat->dmamap_unload = psycho_dmamap_unload; 479 sc->sc_dmat->dmamap_sync = psycho_dmamap_sync; 480 sc->sc_dmat->dmamem_alloc = psycho_dmamem_alloc; 481 sc->sc_dmat->dmamem_free = psycho_dmamem_free; 482 /* XXX: register as root dma tag (kluge). */ 483 sparc64_root_dma_tag = sc->sc_dmat; 484 485 /* Register the softc, this is needed for paired psychos. */ 486 if (psycho_ndevs < sizeof(psycho_softcs) / sizeof(psycho_softcs[0])) 487 psycho_softcs[psycho_ndevs] = sc; 488 else 489 device_printf(dev, "XXX: bump the number of psycho_softcs"); 490 psycho_ndevs++; 491 /* 492 * And finally, if we're a sabre or the first of a pair of psycho's to 493 * arrive here, start up the IOMMU and get a config space tag. 494 */ 495 if (osc == NULL) { 496 /* 497 * Establish handlers for interesting interrupts.... 498 * 499 * XXX We need to remember these and remove this to support 500 * hotplug on the UPA/FHC bus. 501 * 502 * XXX Not all controllers have these, but installing them 503 * is better than trying to sort through this mess. 504 */ 505 psycho_set_intr(sc, 0, dev, PSR_UE_INT_MAP, INTR_FAST, 506 psycho_ue); 507 psycho_set_intr(sc, 1, dev, PSR_CE_INT_MAP, 0, psycho_ce); 508 psycho_set_intr(sc, 2, dev, PSR_PCIAERR_INT_MAP, INTR_FAST, 509 psycho_bus_a); 510 psycho_set_intr(sc, 3, dev, PSR_PCIBERR_INT_MAP, INTR_FAST, 511 psycho_bus_b); 512 psycho_set_intr(sc, 4, dev, PSR_POWER_INT_MAP, INTR_FAST, 513 psycho_powerfail); 514#ifdef PSYCHO_MAP_WAKEUP 515 /* 516 * On some models, this is mapped to the same interrupt as 517 * pciberr by default, so leave it alone for now since 518 * psycho_wakeup() doesn't do anything useful anyway. 519 */ 520 psycho_set_intr(sc, 5, dev, PSR_PWRMGT_INT_MAP, 0, 521 psycho_wakeup); 522#endif /* PSYCHO_MAP_WAKEUP */ 523 524 525 /* Initialize the counter-timer if we handle a psycho. */ 526 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 527 sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, 528 PSR_TC0); 529 } 530 531 /* 532 * Setup IOMMU and PCI configuration if we're the first 533 * of a pair of psycho's to arrive here. 534 * 535 * We should calculate a TSB size based on amount of RAM 536 * and number of bus controllers and number an type of 537 * child devices. 538 * 539 * For the moment, 32KB should be more than enough. 540 */ 541 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 542 M_NOWAIT); 543 if (sc->sc_is == NULL) 544 panic("psycho_attach: malloc iommu_state failed"); 545 sc->sc_is->is_sb[0] = 0; 546 sc->sc_is->is_sb[1] = 0; 547 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 548 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 549 psycho_iommu_init(sc, 2); 550 } else { 551 /* Just copy IOMMU state, config tag and address */ 552 sc->sc_is = osc->sc_is; 553 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 554 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 555 iommu_reset(sc->sc_is); 556 } 557 558 /* 559 * Enable all interrupts, clear all interrupt states, and install an 560 * interrupt handler for OBIO interrupts, which can be ISA ones 561 * (to frob the interrupt clear registers). 562 * This aids the debugging of interrupt routing problems, and is needed 563 * for isa drivers that use isa_irq_pending (otherwise the registers 564 * will never be cleared). 565 */ 566#if defined(PSYCHO_DEBUG) || defined(PSYCHO_STRAY) 567 for (map = PSR_PCIA0_INT_MAP, clr = PSR_PCIA0_INT_CLR, n = 0; 568 map <= PSR_PCIB3_INT_MAP; map += 8, clr += 32, n++) { 569 mr = PSYCHO_READ8(sc, map); 570#ifdef PSYCHO_DEBUG 571 device_printf(dev, "intr map (pci) %d: %#lx\n", n, (u_long)mr); 572#endif 573 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 574 for (i = 0; i < 4; i++) 575 PCICTL_WRITE8(sc, clr + i * 8, 0); 576 PSYCHO_WRITE8(sc, map, mr | INTMAP_V); 577 } 578 for (map = PSR_SCSI_INT_MAP, clr = PSR_SCSI_INT_CLR, n = 0; 579 map <= PSR_FFB1_INT_MAP; map += 8, clr += 8, n++) { 580 mr = PSYCHO_READ8(sc, map); 581#ifdef PSYCHO_DEBUG 582 device_printf(dev, "intr map (obio) %d: %#lx, clr: %#lx\n", n, 583 (u_long)mr, (u_long)clr); 584#endif 585 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 586 PSYCHO_WRITE8(sc, clr, 0); 587#ifdef PSYCHO_STRAY 588 /* 589 * This can cause interrupt storms, and is therefore disabled 590 * by default. 591 * XXX: use intr_setup() to not confuse higher level code 592 */ 593 if (INTVEC(mr) != 0x7e6 && INTVEC(mr) != 0x7e7 && 594 INTVEC(mr) != 0) { 595 sclr = malloc(sizeof(*sclr), M_DEVBUF, M_WAITOK); 596 sclr->psc_sc = sc; 597 sclr->psc_clr = clr; 598 intr_setup(PIL_LOW, intr_dequeue, INTVEC(mr), 599 psycho_intr_stray, sclr); 600 } 601#endif 602 PSYCHO_WRITE8(sc, map, mr | INTMAP_V); 603 } 604#endif 605 606 /* 607 * Initialize the interrupt registers of all devices hanging from 608 * the host bridge directly or indirectly via PCI-PCI bridges. 609 * The MI code (and the PCI spec) assume that this is done during 610 * system initialization, however the firmware does not do this 611 * at least on some models, and we probably shouldn't trust that 612 * the firmware uses the same model as this driver if it does. 613 */ 614 ofw_pci_init_intr(dev, sc->sc_node); 615 616 device_add_child(dev, "pci", device_get_unit(dev)); 617 return (bus_generic_attach(dev)); 618} 619 620static void 621psycho_set_intr(struct psycho_softc *sc, int index, 622 device_t dev, bus_addr_t map, int iflags, driver_intr_t handler) 623{ 624 int rid, vec; 625 u_int64_t mr; 626 627 mr = PSYCHO_READ8(sc, map); 628 vec = INTVEC(mr); 629 sc->sc_irq_res[index] = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 630 vec, vec, 1, RF_ACTIVE); 631 if (sc->sc_irq_res[index] == NULL) 632 panic("psycho_set_intr: failed to get interrupt"); 633 bus_setup_intr(dev, sc->sc_irq_res[index], INTR_TYPE_MISC | iflags, 634 handler, sc, &sc->sc_ihand[index]); 635 PSYCHO_WRITE8(sc, map, mr | INTMAP_V); 636} 637 638static int 639psycho_find_intrmap(struct psycho_softc *sc, int ino, bus_addr_t *intrmapptr, 640 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 641{ 642 bus_addr_t intrmap, intrclr; 643 u_int64_t im; 644 u_long diag; 645 int found; 646 647 found = 0; 648 /* Hunt thru obio first */ 649 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 650 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 651 intrmap <= PSR_FFB1_INT_MAP; intrmap += 8, intrclr += 8, 652 diag >>= 2) { 653 im = PSYCHO_READ8(sc, intrmap); 654 if (INTINO(im) == ino) { 655 diag &= 2; 656 found = 1; 657 break; 658 } 659 } 660 661 if (!found) { 662 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 663 /* Now do PCI interrupts */ 664 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 665 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 666 diag >>= 8) { 667 im = PSYCHO_READ8(sc, intrmap); 668 if (((im ^ ino) & 0x3c) == 0) { 669 intrclr += 8 * (ino & 3); 670 diag = (diag >> ((ino & 3) * 2)) & 2; 671 found = 1; 672 break; 673 } 674 } 675 } 676 if (intrmapptr != NULL) 677 *intrmapptr = intrmap; 678 if (intrclrptr != NULL) 679 *intrclrptr = intrclr; 680 if (intrdiagptr != NULL) 681 *intrdiagptr = diag; 682 return (found); 683} 684 685/* grovel the OBP for various psycho properties */ 686static void 687psycho_get_ranges(phandle_t node, struct upa_ranges **rp, int *np) 688{ 689 690 *np = OF_getprop_alloc(node, "ranges", sizeof(**rp), (void **)rp); 691 if (*np == -1) 692 panic("could not get psycho ranges"); 693} 694 695/* 696 * Interrupt handlers. 697 */ 698static void 699psycho_ue(void *arg) 700{ 701 struct psycho_softc *sc = (struct psycho_softc *)arg; 702 u_int64_t afar, afsr; 703 704 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 705 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 706 /* 707 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 708 * the AFAR to be set to the physical address of the TTE entry that 709 * was invalid/write protected. Call into the iommu code to have 710 * them decoded to virtual IO addresses. 711 */ 712 if ((afsr & UEAFSR_P_DTE) != 0) 713 iommu_decode_fault(sc->sc_is, afar); 714 /* It's uncorrectable. Dump the regs and panic. */ 715 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx\n", 716 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 717} 718 719static void 720psycho_ce(void *arg) 721{ 722 struct psycho_softc *sc = (struct psycho_softc *)arg; 723 u_int64_t afar, afsr; 724 725 PSYCHO_WRITE8(sc, PSR_CE_INT_CLR, 0); 726 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 727 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 728 /* It's correctable. Dump the regs and continue. */ 729 printf("%s: correctable DMA error AFAR %#lx AFSR %#lx\n", 730 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 731} 732 733static void 734psycho_bus_a(void *arg) 735{ 736 struct psycho_softc *sc = (struct psycho_softc *)arg; 737 u_int64_t afar, afsr; 738 739 afar = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFA); 740 afsr = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFS); 741 /* It's uncorrectable. Dump the regs and panic. */ 742 panic("%s: PCI bus A error AFAR %#lx AFSR %#lx\n", 743 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 744} 745 746static void 747psycho_bus_b(void *arg) 748{ 749 struct psycho_softc *sc = (struct psycho_softc *)arg; 750 u_int64_t afar, afsr; 751 752 afar = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFA); 753 afsr = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFS); 754 /* It's uncorrectable. Dump the regs and panic. */ 755 panic("%s: PCI bus B error AFAR %#lx AFSR %#lx\n", 756 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 757} 758 759static void 760psycho_powerfail(void *arg) 761{ 762 763 /* We lost power. Try to shut down NOW. */ 764#ifdef DEBUGGER_ON_POWERFAIL 765 struct psycho_softc *sc = (struct psycho_softc *)arg; 766 767 Debugger("powerfail"); 768 PSYCHO_WRITE8(sc, PSR_POWER_INT_CLR, 0); 769#else 770 printf("Power Failure Detected: Shutting down NOW.\n"); 771 shutdown_nice(0); 772#endif 773} 774 775#ifdef PSYCHO_MAP_WAKEUP 776static void 777psycho_wakeup(void *arg) 778{ 779 struct psycho_softc *sc = (struct psycho_softc *)arg; 780 781 PSYCHO_WRITE8(sc, PSR_PWRMGT_INT_CLR, 0); 782 /* Gee, we don't really have a framework to deal with this properly. */ 783 printf("%s: power management wakeup\n", device_get_name(sc->sc_dev)); 784} 785#endif /* PSYCHO_MAP_WAKEUP */ 786 787/* initialise the IOMMU... */ 788void 789psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 790{ 791 char *name; 792 struct iommu_state *is = sc->sc_is; 793 u_int32_t iobase = -1; 794 int *vdma = NULL; 795 int nitem; 796 797 /* punch in our copies */ 798 is->is_bustag = sc->sc_bustag; 799 is->is_bushandle = sc->sc_bushandle; 800 is->is_iommu = PSR_IOMMU; 801 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 802 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 803 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 804 is->is_dva = PSR_IOMMU_SVADIAG; 805 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 806 807 /* 808 * Separate the men from the boys. Get the `virtual-dma' 809 * property for sabre and use that to make sure the damn 810 * iommu works. 811 * 812 * We could query the `#virtual-dma-size-cells' and 813 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 814 */ 815 nitem = OF_getprop_alloc(sc->sc_node, "virtual-dma", sizeof(vdma), 816 (void **)&vdma); 817 if (nitem > 0) { 818 iobase = vdma[0]; 819 tsbsize = ffs(vdma[1]); 820 if (tsbsize < 25 || tsbsize > 31 || 821 (vdma[1] & ~(1 << (tsbsize - 1))) != 0) { 822 printf("bogus tsb size %x, using 7\n", vdma[1]); 823 tsbsize = 31; 824 } 825 tsbsize -= 24; 826 free(vdma, M_OFWPROP); 827 } 828 829 /* give us a nice name.. */ 830 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 831 if (name == 0) 832 panic("couldn't malloc iommu name"); 833 snprintf(name, 32, "%s dvma", device_get_name(sc->sc_dev)); 834 835 iommu_init(name, is, tsbsize, iobase); 836} 837 838static int 839psycho_maxslots(device_t dev) 840{ 841 842 /* 843 * XXX: is this correct? At any rate, a number that is too high 844 * shouldn't do any harm, if only because of the way things are 845 * handled in psycho_read_config. 846 */ 847 return (31); 848} 849 850/* 851 * Keep a table of quirky PCI devices that need fixups before the MI PCI code 852 * creates the resource lists. This needs to be moved around once other bus 853 * drivers are added. Moving it to the MI code should maybe be reconsidered 854 * if one of these devices appear in non-sparc64 boxen. It's likely that not 855 * all BIOSes/firmwares can deal with them. 856 */ 857struct psycho_dquirk { 858 u_int32_t dq_devid; 859 int dq_quirk; 860}; 861 862/* Quirk types. May be or'ed together. */ 863#define DQT_BAD_INTPIN 1 /* Intpin reg 0, but intpin used */ 864 865static struct psycho_dquirk dquirks[] = { 866 { 0x1001108e, DQT_BAD_INTPIN }, /* Sun HME (PCIO func. 1) */ 867 { 0x1101108e, DQT_BAD_INTPIN }, /* Sun GEM (PCIO2 func. 1) */ 868 { 0x1102108e, DQT_BAD_INTPIN }, /* Sun FireWire ctl. (PCIO2 func. 2) */ 869 { 0x1103108e, DQT_BAD_INTPIN }, /* Sun USB ctl. (PCIO2 func. 3) */ 870}; 871 872#define NDQUIRKS (sizeof(dquirks) / sizeof(dquirks[0])) 873 874static u_int32_t 875psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 876 int width) 877{ 878 struct psycho_softc *sc; 879 bus_space_handle_t bh; 880 u_long offset = 0; 881 u_int32_t r, devid; 882 int i; 883 884 /* 885 * The psycho bridge does not tolerate accesses to unconfigured PCI 886 * devices' or function's config space, so look up the device in the 887 * firmware device tree first, and if it is not present, return a value 888 * that will make the detection code think that there is no device here. 889 * This is ugly... 890 */ 891 if (reg == 0 && ofw_pci_find_node(bus, slot, func) == 0) 892 return (0xffffffff); 893 sc = (struct psycho_softc *)device_get_softc(dev); 894 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 895 bh = sc->sc_bh[PCI_CS_CONFIG]; 896 switch (width) { 897 case 1: 898 r = bus_space_read_1(sc->sc_cfgt, bh, offset); 899 break; 900 case 2: 901 r = bus_space_read_2(sc->sc_cfgt, bh, offset); 902 break; 903 case 4: 904 r = bus_space_read_4(sc->sc_cfgt, bh, offset); 905 break; 906 default: 907 panic("psycho_read_config: bad width"); 908 } 909 if (reg == PCIR_INTPIN && r == 0) { 910 /* Check for DQT_BAD_INTPIN quirk. */ 911 devid = psycho_read_config(dev, bus, slot, func, 912 PCIR_DEVVENDOR, 4); 913 for (i = 0; i < NDQUIRKS; i++) { 914 if (dquirks[i].dq_devid == devid) { 915 /* 916 * Need to set the intpin to a value != 0 so 917 * that the MI code will think that this device 918 * has an interrupt. 919 * Just use 1 (intpin a) for now. This is, of 920 * course, bogus, but since interrupts are 921 * routed in advance, this does not really 922 * matter. 923 */ 924 if ((dquirks[i].dq_quirk & DQT_BAD_INTPIN) != 0) 925 r = 1; 926 break; 927 } 928 } 929 } 930 return (r); 931} 932 933static void 934psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, 935 u_int reg, u_int32_t val, int width) 936{ 937 struct psycho_softc *sc; 938 bus_space_handle_t bh; 939 u_long offset = 0; 940 941 sc = (struct psycho_softc *)device_get_softc(dev); 942 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 943 bh = sc->sc_bh[PCI_CS_CONFIG]; 944 switch (width) { 945 case 1: 946 bus_space_write_1(sc->sc_cfgt, bh, offset, val); 947 break; 948 case 2: 949 bus_space_write_2(sc->sc_cfgt, bh, offset, val); 950 break; 951 case 4: 952 bus_space_write_4(sc->sc_cfgt, bh, offset, val); 953 break; 954 default: 955 panic("psycho_write_config: bad width"); 956 } 957} 958 959static int 960psycho_route_interrupt(device_t bus, device_t dev, int pin) 961{ 962 int intline; 963 964 /* 965 * XXX: ugly loathsome hack: 966 * We can't use ofw_pci_route_intr() here; the device passed may be 967 * the one of a bridge, so the original device can't be recovered. 968 * 969 * We need to use the firmware to route interrupts, however it has 970 * no interface which could be used to interpret intpins; instead, 971 * all assignments are done by device. 972 * 973 * The MI pci code will try to reroute interrupts of 0, although they 974 * are correct; all other interrupts are preinitialized, so if we 975 * get here, the intline is either 0 (so return 0), or we hit a 976 * device which was not preinitialized (e.g. hotplugged stuff), in 977 * which case we are lost. 978 */ 979 return (0); 980} 981 982static int 983psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 984{ 985 struct psycho_softc *sc; 986 987 sc = (struct psycho_softc *)device_get_softc(dev); 988 switch (which) { 989 case PCIB_IVAR_BUS: 990 *result = sc->sc_busno; 991 return (0); 992 } 993 return (ENOENT); 994} 995 996/* Write to the correct clr register, and call the actual handler. */ 997static void 998psycho_intr_stub(void *arg) 999{ 1000 struct psycho_clr *pc; 1001 1002 pc = (struct psycho_clr *)arg; 1003 pc->pci_handler(pc->pci_arg); 1004 PSYCHO_WRITE8(pc->pci_sc, pc->pci_clr, 0); 1005} 1006 1007#ifdef PSYCHO_STRAY 1008/* 1009 * Write to the correct clr register and return. arg is the address of the clear 1010 * register to be used. 1011 * XXX: print a message? 1012 */ 1013static void 1014psycho_intr_stray(void *arg) 1015{ 1016 struct psycho_strayclr *sclr = arg; 1017 1018 PSYCHO_WRITE8(sclr->psc_sc, sclr->psc_clr, 0); 1019} 1020#endif 1021 1022static int 1023psycho_setup_intr(device_t dev, device_t child, 1024 struct resource *ires, int flags, driver_intr_t *intr, void *arg, 1025 void **cookiep) 1026{ 1027 struct psycho_softc *sc; 1028 struct psycho_clr *pc; 1029 bus_addr_t intrmapptr, intrclrptr; 1030 long vec = rman_get_start(ires); 1031 u_int64_t mr; 1032 int ino, error; 1033 1034 sc = (struct psycho_softc *)device_get_softc(dev); 1035 pc = (struct psycho_clr *)malloc(sizeof(*pc), M_DEVBUF, M_NOWAIT); 1036 if (pc == NULL) 1037 return (NULL); 1038 1039 /* 1040 * Hunt through all the interrupt mapping regs to look for our 1041 * interrupt vector. 1042 * 1043 * XXX We only compare INOs rather than IGNs since the firmware may 1044 * not provide the IGN and the IGN is constant for all device on that 1045 * PCI controller. This could cause problems for the FFB/external 1046 * interrupt which has a full vector that can be set arbitrarily. 1047 */ 1048 ino = INTINO(vec); 1049 1050 if (!psycho_find_intrmap(sc, ino, &intrmapptr, &intrclrptr, NULL)) { 1051 printf("Cannot find interrupt vector %lx\n", vec); 1052 free(pc, M_DEVBUF); 1053 return (NULL); 1054 } 1055 1056#ifdef PSYCHO_DEBUG 1057 device_printf(dev, "psycho_setup_intr: INO %d, map %#lx, clr %#lx\n", 1058 ino, (u_long)intrmapptr, (u_long)intrclrptr); 1059#endif 1060 pc->pci_sc = sc; 1061 pc->pci_arg = arg; 1062 pc->pci_handler = intr; 1063 pc->pci_clr = intrclrptr; 1064 /* Disable the interrupt while we fiddle with it */ 1065 mr = PSYCHO_READ8(sc, intrmapptr); 1066 PSYCHO_WRITE8(sc, intrmapptr, mr & ~INTMAP_V); 1067 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 1068 psycho_intr_stub, pc, cookiep); 1069 if (error != 0) { 1070 free(pc, M_DEVBUF); 1071 return (error); 1072 } 1073 pc->pci_cookie = *cookiep; 1074 *cookiep = pc; 1075 1076 /* 1077 * Clear the interrupt, it might have been triggered before it was 1078 * set up. 1079 */ 1080 PSYCHO_WRITE8(sc, intrclrptr, 0); 1081 /* 1082 * Enable the interrupt now we have the handler installed. 1083 * Read the current value as we can't change it besides the 1084 * valid bit so so make sure only this bit is changed. 1085 */ 1086 PSYCHO_WRITE8(sc, intrmapptr, mr | INTMAP_V); 1087 return (error); 1088} 1089 1090static int 1091psycho_teardown_intr(device_t dev, device_t child, 1092 struct resource *vec, void *cookie) 1093{ 1094 struct psycho_clr *pc; 1095 int error; 1096 1097 pc = (struct psycho_clr *)cookie; 1098 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 1099 pc->pci_cookie); 1100 /* 1101 * Don't disable the interrupt for now, so that stray interupts get 1102 * detected... 1103 */ 1104 if (error != 0) 1105 free(pc, M_DEVBUF); 1106 return (error); 1107} 1108 1109static struct resource * 1110psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1111 u_long start, u_long end, u_long count, u_int flags) 1112{ 1113 struct psycho_softc *sc; 1114 struct resource *rv; 1115 struct rman *rm; 1116 bus_space_tag_t bt; 1117 bus_space_handle_t bh; 1118 int needactivate = flags & RF_ACTIVE; 1119 1120 flags &= ~RF_ACTIVE; 1121 1122 sc = (struct psycho_softc *)device_get_softc(bus); 1123 if (type == SYS_RES_IRQ) { 1124 /* 1125 * XXX: Don't accept blank ranges for now, only single 1126 * interrupts. The other case should not happen with the MI pci 1127 * code... 1128 * XXX: This may return a resource that is out of the range 1129 * that was specified. Is this correct...? 1130 */ 1131 if (start != end) 1132 panic("psycho_alloc_resource: XXX: interrupt range"); 1133 start = end |= sc->sc_ign; 1134 return (bus_alloc_resource(bus, type, rid, start, end, 1135 count, flags)); 1136 } 1137 switch (type) { 1138 case SYS_RES_MEMORY: 1139 rm = &sc->sc_mem_rman; 1140 bt = sc->sc_memt; 1141 bh = sc->sc_bh[PCI_CS_MEM32]; 1142 break; 1143 case SYS_RES_IOPORT: 1144 rm = &sc->sc_io_rman; 1145 bt = sc->sc_iot; 1146 /* XXX: probably should use ranges property here. */ 1147 bh = sc->sc_bh[PCI_CS_IO]; 1148 break; 1149 default: 1150 return (NULL); 1151 } 1152 1153 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1154 if (rv == NULL) 1155 return (NULL); 1156 1157 bh += rman_get_start(rv); 1158 rman_set_bustag(rv, bt); 1159 rman_set_bushandle(rv, bh); 1160 1161 if (needactivate) { 1162 if (bus_activate_resource(child, type, *rid, rv)) { 1163 rman_release_resource(rv); 1164 return (NULL); 1165 } 1166 } 1167 1168 return (rv); 1169} 1170 1171static int 1172psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1173 struct resource *r) 1174{ 1175 void *p; 1176 int error; 1177 1178 if (type == SYS_RES_IRQ) 1179 return (bus_activate_resource(bus, type, rid, r)); 1180 if (type == SYS_RES_MEMORY) { 1181 /* 1182 * Need to memory-map the device space, as some drivers depend 1183 * on the virtual address being set and useable. 1184 */ 1185 error = sparc64_bus_mem_map(rman_get_bustag(r), 1186 rman_get_bushandle(r), rman_get_size(r), 0, NULL, &p); 1187 if (error != 0) 1188 return (error); 1189 rman_set_virtual(r, p); 1190 } 1191 return (rman_activate_resource(r)); 1192} 1193 1194static int 1195psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1196 struct resource *r) 1197{ 1198 1199 if (type == SYS_RES_IRQ) 1200 return (bus_deactivate_resource(bus, type, rid, r)); 1201 if (type == SYS_RES_MEMORY) { 1202 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1203 rman_set_virtual(r, NULL); 1204 } 1205 return (rman_deactivate_resource(r)); 1206} 1207 1208static int 1209psycho_release_resource(device_t bus, device_t child, int type, int rid, 1210 struct resource *r) 1211{ 1212 int error; 1213 1214 if (type == SYS_RES_IRQ) 1215 return (bus_release_resource(bus, type, rid, r)); 1216 if (rman_get_flags(r) & RF_ACTIVE) { 1217 error = bus_deactivate_resource(child, type, rid, r); 1218 if (error) 1219 return error; 1220 } 1221 return (rman_release_resource(r)); 1222} 1223 1224static int 1225psycho_intr_pending(device_t dev, int intr) 1226{ 1227 struct psycho_softc *sc; 1228 u_long diag; 1229 1230 sc = (struct psycho_softc *)device_get_softc(dev); 1231 if (!psycho_find_intrmap(sc, intr, NULL, NULL, &diag)) { 1232 printf("psycho_intr_pending: mapping not found for %d\n", intr); 1233 return (0); 1234 } 1235 return (diag != 0); 1236} 1237 1238static bus_space_handle_t 1239psycho_get_bus_handle(device_t dev, enum sbbt_id id, 1240 bus_space_handle_t childhdl, bus_space_tag_t *tag) 1241{ 1242 struct psycho_softc *sc; 1243 1244 sc = (struct psycho_softc *)device_get_softc(dev); 1245 switch(id) { 1246 case SBBT_IO: 1247 *tag = sc->sc_iot; 1248 return (sc->sc_bh[PCI_CS_IO] + childhdl); 1249 case SBBT_MEM: 1250 *tag = sc->sc_memt; 1251 return (sc->sc_bh[PCI_CS_MEM32] + childhdl); 1252 default: 1253 panic("psycho_get_bus_handle: illegal space\n"); 1254 } 1255} 1256 1257/* 1258 * below here is bus space and bus dma support 1259 */ 1260static bus_space_tag_t 1261psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1262{ 1263 bus_space_tag_t bt; 1264 1265 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1266 M_NOWAIT | M_ZERO); 1267 if (bt == NULL) 1268 panic("psycho_alloc_bus_tag: out of memory"); 1269 1270 bzero(bt, sizeof *bt); 1271 bt->cookie = sc; 1272 bt->parent = sc->sc_bustag; 1273 bt->type = type; 1274 return (bt); 1275} 1276 1277/* 1278 * hooks into the iommu dvma calls. 1279 */ 1280static int 1281psycho_dmamem_alloc(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void **vaddr, 1282 int flags, bus_dmamap_t *mapp) 1283{ 1284 struct psycho_softc *sc; 1285 1286 sc = (struct psycho_softc *)pdmat->cookie; 1287 return (iommu_dvmamem_alloc(pdmat, ddmat, sc->sc_is, vaddr, flags, 1288 mapp)); 1289} 1290 1291static void 1292psycho_dmamem_free(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void *vaddr, 1293 bus_dmamap_t map) 1294{ 1295 struct psycho_softc *sc; 1296 1297 sc = (struct psycho_softc *)pdmat->cookie; 1298 iommu_dvmamem_free(pdmat, ddmat, sc->sc_is, vaddr, map); 1299} 1300 1301static int 1302psycho_dmamap_create(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, int flags, 1303 bus_dmamap_t *mapp) 1304{ 1305 struct psycho_softc *sc; 1306 1307 sc = (struct psycho_softc *)pdmat->cookie; 1308 return (iommu_dvmamap_create(pdmat, ddmat, sc->sc_is, flags, mapp)); 1309 1310} 1311 1312static int 1313psycho_dmamap_destroy(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, 1314 bus_dmamap_t map) 1315{ 1316 struct psycho_softc *sc; 1317 1318 sc = (struct psycho_softc *)pdmat->cookie; 1319 return (iommu_dvmamap_destroy(pdmat, ddmat, sc->sc_is, map)); 1320} 1321 1322static int 1323psycho_dmamap_load(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map, 1324 void *buf, bus_size_t buflen, bus_dmamap_callback_t *callback, 1325 void *callback_arg, int flags) 1326{ 1327 struct psycho_softc *sc; 1328 1329 sc = (struct psycho_softc *)pdmat->cookie; 1330 return (iommu_dvmamap_load(pdmat, ddmat, sc->sc_is, map, buf, buflen, 1331 callback, callback_arg, flags)); 1332} 1333 1334static void 1335psycho_dmamap_unload(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map) 1336{ 1337 struct psycho_softc *sc; 1338 1339 sc = (struct psycho_softc *)pdmat->cookie; 1340 iommu_dvmamap_unload(pdmat, ddmat, sc->sc_is, map); 1341} 1342 1343static void 1344psycho_dmamap_sync(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map, 1345 bus_dmasync_op_t op) 1346{ 1347 struct psycho_softc *sc; 1348 1349 sc = (struct psycho_softc *)pdmat->cookie; 1350 iommu_dvmamap_sync(pdmat, ddmat, sc->sc_is, map, op); 1351} 1352