psycho.c revision 93067
1/* 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * All rights reserved. 4 * Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 30 * 31 * $FreeBSD: head/sys/sparc64/pci/psycho.c 93067 2002-03-24 02:11:06Z tmm $ 32 */ 33 34/* 35 * Support for `psycho' and `psycho+' UPA to PCI bridge and 36 * UltraSPARC IIi and IIe `sabre' PCI controllers. 37 */ 38 39#include "opt_psycho.h" 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/kernel.h> 45#include <sys/malloc.h> 46 47#include <ofw/openfirm.h> 48#include <ofw/ofw_pci.h> 49 50#include <machine/bus.h> 51#include <machine/iommureg.h> 52#include <machine/bus_common.h> 53#include <machine/frame.h> 54#include <machine/intr_machdep.h> 55#include <machine/nexusvar.h> 56#include <machine/ofw_upa.h> 57#include <machine/resource.h> 58 59#include <sys/rman.h> 60 61#include <machine/iommuvar.h> 62 63#include <pci/pcivar.h> 64#include <pci/pcireg.h> 65 66#include <sparc64/pci/ofw_pci.h> 67#include <sparc64/pci/psychoreg.h> 68#include <sparc64/pci/psychovar.h> 69 70#include "pcib_if.h" 71#include "sparcbus_if.h" 72 73static void psycho_get_ranges(phandle_t, struct upa_ranges **, int *); 74static void psycho_set_intr(struct psycho_softc *, int, device_t, bus_addr_t, 75 int, driver_intr_t); 76static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *, 77 bus_addr_t *, u_long *); 78static void psycho_intr_stub(void *); 79#ifdef PSYCHO_STRAY 80static void psycho_intr_stray(void *); 81#endif 82static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 83 84 85/* Interrupt handlers */ 86static void psycho_ue(void *); 87static void psycho_ce(void *); 88static void psycho_bus_a(void *); 89static void psycho_bus_b(void *); 90static void psycho_powerfail(void *); 91#ifdef PSYCHO_MAP_WAKEUP 92static void psycho_wakeup(void *); 93#endif 94 95/* IOMMU support */ 96static void psycho_iommu_init(struct psycho_softc *, int); 97 98/* 99 * bus space and bus dma support for UltraSPARC `psycho'. note that most 100 * of the bus dma support is provided by the iommu dvma controller. 101 */ 102static int psycho_dmamap_create(bus_dma_tag_t, int, bus_dmamap_t *); 103static int psycho_dmamap_destroy(bus_dma_tag_t, bus_dmamap_t); 104static int psycho_dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *, bus_size_t, 105 bus_dmamap_callback_t *, void *, int); 106static void psycho_dmamap_unload(bus_dma_tag_t, bus_dmamap_t); 107static void psycho_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_dmasync_op_t); 108static int psycho_dmamem_alloc(bus_dma_tag_t, void **, int, bus_dmamap_t *); 109static void psycho_dmamem_free(bus_dma_tag_t, void *, bus_dmamap_t); 110 111/* 112 * autoconfiguration 113 */ 114static int psycho_probe(device_t); 115static int psycho_attach(device_t); 116static int psycho_read_ivar(device_t, device_t, int, u_long *); 117static int psycho_setup_intr(device_t, device_t, struct resource *, int, 118 driver_intr_t *, void *, void **); 119static int psycho_teardown_intr(device_t, device_t, struct resource *, void *); 120static struct resource *psycho_alloc_resource(device_t, device_t, int, int *, 121 u_long, u_long, u_long, u_int); 122static int psycho_activate_resource(device_t, device_t, int, int, 123 struct resource *); 124static int psycho_deactivate_resource(device_t, device_t, int, int, 125 struct resource *); 126static int psycho_release_resource(device_t, device_t, int, int, 127 struct resource *); 128static int psycho_maxslots(device_t); 129static u_int32_t psycho_read_config(device_t, u_int, u_int, u_int, u_int, int); 130static void psycho_write_config(device_t, u_int, u_int, u_int, u_int, u_int32_t, 131 int); 132static int psycho_route_interrupt(device_t, device_t, int); 133static int psycho_intr_pending(device_t, int); 134static bus_space_handle_t psycho_get_bus_handle(device_t dev, enum sbbt_id id, 135 bus_space_handle_t childhdl, bus_space_tag_t *tag); 136 137static device_method_t psycho_methods[] = { 138 /* Device interface */ 139 DEVMETHOD(device_probe, psycho_probe), 140 DEVMETHOD(device_attach, psycho_attach), 141 142 /* Bus interface */ 143 DEVMETHOD(bus_print_child, bus_generic_print_child), 144 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 145 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 146 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 147 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 148 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 149 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 150 DEVMETHOD(bus_release_resource, psycho_release_resource), 151 152 /* pcib interface */ 153 DEVMETHOD(pcib_maxslots, psycho_maxslots), 154 DEVMETHOD(pcib_read_config, psycho_read_config), 155 DEVMETHOD(pcib_write_config, psycho_write_config), 156 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 157 158 /* sparcbus interface */ 159 DEVMETHOD(sparcbus_intr_pending, psycho_intr_pending), 160 DEVMETHOD(sparcbus_get_bus_handle, psycho_get_bus_handle), 161 162 { 0, 0 } 163}; 164 165static driver_t psycho_driver = { 166 "pcib", 167 psycho_methods, 168 sizeof(struct psycho_softc), 169}; 170 171static devclass_t psycho_devclass; 172 173DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 174 175static int psycho_ndevs; 176static struct psycho_softc *psycho_softcs[4]; 177 178struct psycho_clr { 179 struct psycho_softc *pci_sc; 180 bus_addr_t pci_clr; /* clear register */ 181 driver_intr_t *pci_handler; /* handler to call */ 182 void *pci_arg; /* argument for the handler */ 183 void *pci_cookie; /* interrupt cookie of parent bus */ 184}; 185 186struct psycho_strayclr { 187 struct psycho_softc *psc_sc; 188 bus_addr_t psc_clr; /* clear register */ 189}; 190 191#define PSYCHO_READ8(sc, off) \ 192 bus_space_read_8((sc)->sc_bustag, (sc)->sc_bushandle, (off)) 193#define PSYCHO_WRITE8(sc, off, v) \ 194 bus_space_write_8((sc)->sc_bustag, (sc)->sc_bushandle, (off), (v)) 195#define PCICTL_READ8(sc, off) \ 196 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 197#define PCICTL_WRITE8(sc, off, v) \ 198 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 199 200/* 201 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 202 * single PCI bus and does not have a streaming buffer. It often has an APB 203 * (advanced PCI bridge) connected to it, which was designed specifically for 204 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 205 * appears as two "simba"'s underneath the sabre. 206 * 207 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 208 * and manages two PCI buses. "psycho" has two 64-bit 33MHz buses, while 209 * "psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 210 * will usually find a "psycho+" since I don't think the original "psycho" 211 * ever shipped, and if it did it would be in the U30. 212 * 213 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 214 * both part of the same IC, they only have a single register space. As such, 215 * they need to be configured together, even though the autoconfiguration will 216 * attach them separately. 217 * 218 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 219 * as pci1 and pci2, although they have been implemented with other PCI bus 220 * numbers on some machines. 221 * 222 * On UltraII machines, there can be any number of "psycho+" ICs, each 223 * providing two PCI buses. 224 * 225 * 226 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 227 * the values of the following interrupts in this order: 228 * 229 * PCI Bus Error (30) 230 * DMA UE (2e) 231 * DMA CE (2f) 232 * Power Fail (25) 233 * 234 * We really should attach handlers for each. 235 */ 236#define OFW_PCI_TYPE "pci" 237#define OFW_SABRE_MODEL "SUNW,sabre" 238#define OFW_SABRE_COMPAT "pci108e,a001" 239#define OFW_SIMBA_MODEL "SUNW,simba" 240#define OFW_PSYCHO_MODEL "SUNW,psycho" 241 242static int 243psycho_probe(device_t dev) 244{ 245 phandle_t node; 246 char *dtype, *model; 247 static char compat[32]; 248 249 node = nexus_get_node(dev); 250 if (OF_getprop(node, "compatible", compat, sizeof(compat)) == -1) 251 compat[0] = '\0'; 252 253 dtype = nexus_get_device_type(dev); 254 model = nexus_get_model(dev); 255 /* match on a type of "pci" and a sabre or a psycho */ 256 if (nexus_get_reg(dev) != NULL && dtype != NULL && 257 strcmp(dtype, OFW_PCI_TYPE) == 0 && 258 ((model != NULL && (strcmp(model, OFW_SABRE_MODEL) == 0 || 259 strcmp(model, OFW_PSYCHO_MODEL) == 0)) || 260 strcmp(compat, OFW_SABRE_COMPAT) == 0)) { 261 device_set_desc(dev, "U2P UPA-PCI bridge"); 262 return (0); 263 } 264 265 return (ENXIO); 266} 267 268/* 269 * SUNW,psycho initialisation .. 270 * - find the per-psycho registers 271 * - figure out the IGN. 272 * - find our partner psycho 273 * - configure ourselves 274 * - bus range, bus, 275 * - interrupt map, 276 * - setup the chipsets. 277 * - if we're the first of the pair, initialise the IOMMU, otherwise 278 * just copy it's tags and addresses. 279 */ 280static int 281psycho_attach(device_t dev) 282{ 283 struct psycho_softc *sc; 284 struct psycho_softc *osc = NULL; 285 struct psycho_softc *asc; 286 struct upa_regs *reg; 287 char compat[32]; 288 char *model; 289 phandle_t node; 290 u_int64_t csr; 291 u_long pcictl_offs, mlen; 292 int psycho_br[2]; 293 int n, i, nreg, rid; 294#if defined(PSYCHO_DEBUG) || defined(PSYCHO_STRAY) 295 bus_addr_t map, clr; 296 u_int64_t mr; 297#endif 298#ifdef PSYCHO_STRAY 299 struct psycho_strayclr *sclr; 300#endif 301 302 node = nexus_get_node(dev); 303 sc = device_get_softc(dev); 304 if (OF_getprop(node, "compatible", compat, sizeof(compat)) == -1) 305 compat[0] = '\0'; 306 307 sc->sc_node = node; 308 sc->sc_dev = dev; 309 sc->sc_dmatag = nexus_get_dmatag(dev); 310 311 /* 312 * call the model-specific initialisation routine. 313 */ 314 model = nexus_get_model(dev); 315 if ((model != NULL && 316 strcmp(model, OFW_SABRE_MODEL) == 0) || 317 strcmp(compat, OFW_SABRE_COMPAT) == 0) { 318 sc->sc_mode = PSYCHO_MODE_SABRE; 319 if (model == NULL) 320 model = "sabre"; 321 } else if (model != NULL && 322 strcmp(model, OFW_PSYCHO_MODEL) == 0) 323 sc->sc_mode = PSYCHO_MODE_PSYCHO; 324 else 325 panic("psycho_attach: unknown model!"); 326 327 /* 328 * The psycho gets three register banks: 329 * (0) per-PBM configuration and status registers 330 * (1) per-PBM PCI configuration space, containing only the 331 * PBM 256-byte PCI header 332 * (2) the shared psycho configuration registers (struct psychoreg) 333 * 334 * XXX use the prom address for the psycho registers? we do so far. 335 */ 336 reg = nexus_get_reg(dev); 337 nreg = nexus_get_nreg(dev); 338 /* Register layouts are different. stuupid. */ 339 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 340 if (nreg <= 2) 341 panic("psycho_attach: %d not enough registers", nreg); 342 sc->sc_basepaddr = (vm_offset_t)UPA_REG_PHYS(®[2]); 343 mlen = UPA_REG_SIZE(®[2]); 344 pcictl_offs = UPA_REG_PHYS(®[0]); 345 } else { 346 if (nreg <= 0) 347 panic("psycho_attach: %d not enough registers", nreg); 348 sc->sc_basepaddr = (vm_offset_t)UPA_REG_PHYS(®[0]); 349 mlen = UPA_REG_SIZE(reg); 350 pcictl_offs = sc->sc_basepaddr + PSR_PCICTL0; 351 } 352 353 /* 354 * Match other psycho's that are already configured against 355 * the base physical address. This will be the same for a 356 * pair of devices that share register space. 357 */ 358 for (n = 0; n < psycho_ndevs && n < sizeof(psycho_softcs) / 359 sizeof(psycho_softcs[0]); n++) { 360 asc = (struct psycho_softc *)psycho_softcs[n]; 361 362 if (asc == NULL || asc == sc) 363 /* This entry is not there or it is me */ 364 continue; 365 366 if (asc->sc_basepaddr != sc->sc_basepaddr) 367 /* This is an unrelated psycho */ 368 continue; 369 370 /* Found partner */ 371 osc = asc; 372 break; 373 } 374 375 if (osc == NULL) { 376 rid = 0; 377 sc->sc_mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 378 sc->sc_basepaddr, sc->sc_basepaddr + mlen - 1, mlen, 379 RF_ACTIVE); 380 if (sc->sc_mem_res == NULL || 381 rman_get_start(sc->sc_mem_res) != sc->sc_basepaddr) 382 panic("psycho_attach: can't allocate device memory"); 383 sc->sc_bustag = rman_get_bustag(sc->sc_mem_res); 384 sc->sc_bushandle = rman_get_bushandle(sc->sc_mem_res); 385 } else { 386 /* 387 * There's another psycho using the same register space. Copy the 388 * relevant stuff. 389 */ 390 sc->sc_mem_res = NULL; 391 sc->sc_bustag = osc->sc_bustag; 392 sc->sc_bushandle = osc->sc_bushandle; 393 } 394 if (pcictl_offs < sc->sc_basepaddr) 395 panic("psycho_attach: bogus pci control register location"); 396 sc->sc_pcictl = pcictl_offs - sc->sc_basepaddr; 397 csr = PSYCHO_READ8(sc, PSR_CS); 398 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 399 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 400 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 401 402 device_printf(dev, "%s: impl %d, version %d: ign %x ", 403 model, (int)PSYCHO_GCSR_IMPL(csr), (int)PSYCHO_GCSR_VERS(csr), 404 sc->sc_ign); 405 406 /* 407 * Setup the PCI control register 408 */ 409 csr = PCICTL_READ8(sc, PCR_CS); 410 csr |= PCICTL_MRLM | PCICTL_ARB_PARK | PCICTL_ERRINTEN | PCICTL_4ENABLE; 411 csr &= ~(PCICTL_SERR | PCICTL_CPU_PRIO | PCICTL_ARB_PRIO | 412 PCICTL_RTRYWAIT); 413 PCICTL_WRITE8(sc, PCR_CS, csr); 414 415 /* grab the psycho ranges */ 416 psycho_get_ranges(sc->sc_node, &sc->sc_range, &sc->sc_nrange); 417 418 /* get the bus-range for the psycho */ 419 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br)); 420 if (n == -1) 421 panic("could not get psycho bus-range"); 422 if (n != sizeof(psycho_br)) 423 panic("broken psycho bus-range (%d)", n); 424 425 printf("bus range %u to %u; PCI bus %d\n", psycho_br[0], psycho_br[1], 426 psycho_br[0]); 427 428 sc->sc_busno = psycho_br[0]; 429 430 /* Initialize memory and i/o rmans */ 431 sc->sc_io_rman.rm_type = RMAN_ARRAY; 432 sc->sc_io_rman.rm_descr = "Psycho PCI I/O Ports"; 433 if (rman_init(&sc->sc_io_rman) != 0 || 434 rman_manage_region(&sc->sc_io_rman, 0, PSYCHO_IO_SIZE) != 0) 435 panic("psycho_probe: failed to set up i/o rman"); 436 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 437 sc->sc_mem_rman.rm_descr = "Psycho PCI Memory"; 438 if (rman_init(&sc->sc_mem_rman) != 0 || 439 rman_manage_region(&sc->sc_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 440 panic("psycho_probe: failed to set up memory rman"); 441 /* 442 * Find the addresses of the various bus spaces. 443 * There should not be multiple ones of one kind. 444 * The physical start addresses of the ranges are the configuration, 445 * memory and IO handles. 446 */ 447 for (n = 0; n < sc->sc_nrange; n++) { 448 i = UPA_RANGE_CS(&sc->sc_range[n]); 449 if (sc->sc_bh[i] != 0) 450 panic("psycho_attach: duplicate range for space %d", i); 451 sc->sc_bh[i] = UPA_RANGE_PHYS(&sc->sc_range[n]); 452 } 453 /* 454 * Check that all needed handles are present. The PCI_CS_MEM64 one is 455 * not currently used. 456 */ 457 for (n = 0; n < 3; n++) { 458 if (sc->sc_bh[n] == 0) 459 panic("psycho_attach: range %d missing", n); 460 } 461 462 /* allocate our tags */ 463 sc->sc_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 464 sc->sc_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 465 sc->sc_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 466 if (bus_dma_tag_create(sc->sc_dmatag, 8, 1, 0, 0x3ffffffff, NULL, NULL, 467 0x3ffffffff, 0xff, 0xffffffff, 0, &sc->sc_dmat) != 0) 468 panic("psycho_attach: bus_dma_tag_create failed"); 469 /* Customize the tag */ 470 sc->sc_dmat->cookie = sc; 471 sc->sc_dmat->dmamap_create = psycho_dmamap_create; 472 sc->sc_dmat->dmamap_destroy = psycho_dmamap_destroy; 473 sc->sc_dmat->dmamap_load = psycho_dmamap_load; 474 sc->sc_dmat->dmamap_unload = psycho_dmamap_unload; 475 sc->sc_dmat->dmamap_sync = psycho_dmamap_sync; 476 sc->sc_dmat->dmamem_alloc = psycho_dmamem_alloc; 477 sc->sc_dmat->dmamem_free = psycho_dmamem_free; 478 /* XXX: register as root dma tag (kluge). */ 479 sparc64_root_dma_tag = sc->sc_dmat; 480 481 /* Register the softc, this is needed for paired psychos. */ 482 if (psycho_ndevs < sizeof(psycho_softcs) / sizeof(psycho_softcs[0])) 483 psycho_softcs[psycho_ndevs] = sc; 484 else 485 device_printf(dev, "XXX: bump the number of psycho_softcs"); 486 psycho_ndevs++; 487 /* 488 * And finally, if we're a sabre or the first of a pair of psycho's to 489 * arrive here, start up the IOMMU and get a config space tag. 490 */ 491 if (osc == NULL) { 492 /* 493 * Establish handlers for interesting interrupts.... 494 * 495 * XXX We need to remember these and remove this to support 496 * hotplug on the UPA/FHC bus. 497 * 498 * XXX Not all controllers have these, but installing them 499 * is better than trying to sort through this mess. 500 */ 501 psycho_set_intr(sc, 0, dev, PSR_UE_INT_MAP, INTR_FAST, 502 psycho_ue); 503 psycho_set_intr(sc, 1, dev, PSR_CE_INT_MAP, 0, psycho_ce); 504 psycho_set_intr(sc, 2, dev, PSR_PCIAERR_INT_MAP, INTR_FAST, 505 psycho_bus_a); 506 psycho_set_intr(sc, 3, dev, PSR_PCIBERR_INT_MAP, INTR_FAST, 507 psycho_bus_b); 508 psycho_set_intr(sc, 4, dev, PSR_POWER_INT_MAP, INTR_FAST, 509 psycho_powerfail); 510#ifdef PSYCHO_MAP_WAKEUP 511 /* 512 * On some models, this is mapped to the same interrupt as 513 * pciberr by default, so leave it alone for now since 514 * psycho_wakeup() doesn't do anything useful anyway. 515 */ 516 psycho_set_intr(sc, 5, dev, PSR_PWRMGT_INT_MAP, 0, 517 psycho_wakeup); 518#endif /* PSYCHO_MAP_WAKEUP */ 519 520 521 /* Initialize the counter-timer if we handle a psycho. */ 522 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 523 sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, 524 PSR_TC0); 525 } 526 527 /* 528 * Setup IOMMU and PCI configuration if we're the first 529 * of a pair of psycho's to arrive here. 530 * 531 * We should calculate a TSB size based on amount of RAM 532 * and number of bus controllers and number an type of 533 * child devices. 534 * 535 * For the moment, 32KB should be more than enough. 536 */ 537 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 538 M_NOWAIT); 539 if (sc->sc_is == NULL) 540 panic("psycho_attach: malloc iommu_state failed"); 541 sc->sc_is->is_sb[0] = 0; 542 sc->sc_is->is_sb[1] = 0; 543 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 544 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 545 psycho_iommu_init(sc, 2); 546 } else { 547 /* Just copy IOMMU state, config tag and address */ 548 sc->sc_is = osc->sc_is; 549 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 550 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 551 iommu_reset(sc->sc_is); 552 } 553 554 /* 555 * Enable all interrupts, clear all interrupt states, and install an 556 * interrupt handler for OBIO interrupts, which can be ISA ones 557 * (to frob the interrupt clear registers). 558 * This aids the debugging of interrupt routing problems, and is needed 559 * for isa drivers that use isa_irq_pending (otherwise the registers 560 * will never be cleared). 561 */ 562#if defined(PSYCHO_DEBUG) || defined(PSYCHO_STRAY) 563 for (map = PSR_PCIA0_INT_MAP, clr = PSR_PCIA0_INT_CLR, n = 0; 564 map <= PSR_PCIB3_INT_MAP; map += 8, clr += 32, n++) { 565 mr = PSYCHO_READ8(sc, map); 566#ifdef PSYCHO_DEBUG 567 device_printf(dev, "intr map (pci) %d: %#lx\n", n, (u_long)mr); 568#endif 569 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 570 for (i = 0; i < 4; i++) 571 PCICTL_WRITE8(sc, clr + i * 8, 0); 572 PSYCHO_WRITE8(sc, map, mr | INTMAP_V); 573 } 574 for (map = PSR_SCSI_INT_MAP, clr = PSR_SCSI_INT_CLR, n = 0; 575 map <= PSR_FFB1_INT_MAP; map += 8, clr += 8, n++) { 576 mr = PSYCHO_READ8(sc, map); 577#ifdef PSYCHO_DEBUG 578 device_printf(dev, "intr map (obio) %d: %#lx, clr: %#lx\n", n, 579 (u_long)mr, (u_long)clr); 580#endif 581 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 582 PSYCHO_WRITE8(sc, clr, 0); 583#ifdef PSYCHO_STRAY 584 /* 585 * This can cause interrupt storms, and is therefore disabled 586 * by default. 587 * XXX: use intr_setup() to not confuse higher level code 588 */ 589 if (INTVEC(mr) != 0x7e6 && INTVEC(mr) != 0x7e7 && 590 INTVEC(mr) != 0) { 591 sclr = malloc(sizeof(*sclr), M_DEVBUF, M_WAITOK); 592 sclr->psc_sc = sc; 593 sclr->psc_clr = clr; 594 intr_setup(PIL_LOW, intr_dequeue, INTVEC(mr), 595 psycho_intr_stray, sclr); 596 } 597#endif 598 PSYCHO_WRITE8(sc, map, mr | INTMAP_V); 599 } 600#endif 601 602 /* 603 * Initialize the interrupt registers of all devices hanging from 604 * the host bridge directly or indirectly via PCI-PCI bridges. 605 * The MI code (and the PCI spec) assume that this is done during 606 * system initialization, however the firmware does not do this 607 * at least on some models, and we probably shouldn't trust that 608 * the firmware uses the same model as this driver if it does. 609 */ 610 ofw_pci_init_intr(dev, sc->sc_node); 611 612 device_add_child(dev, "pci", device_get_unit(dev)); 613 return (bus_generic_attach(dev)); 614} 615 616static void 617psycho_set_intr(struct psycho_softc *sc, int index, 618 device_t dev, bus_addr_t map, int iflags, driver_intr_t handler) 619{ 620 int rid, vec; 621 u_int64_t mr; 622 623 mr = PSYCHO_READ8(sc, map); 624 vec = INTVEC(mr); 625 sc->sc_irq_res[index] = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 626 vec, vec, 1, RF_ACTIVE); 627 if (sc->sc_irq_res[index] == NULL) 628 panic("psycho_set_intr: failed to get interrupt"); 629 bus_setup_intr(dev, sc->sc_irq_res[index], INTR_TYPE_MISC | iflags, 630 handler, sc, &sc->sc_ihand[index]); 631 PSYCHO_WRITE8(sc, map, mr | INTMAP_V); 632} 633 634static int 635psycho_find_intrmap(struct psycho_softc *sc, int ino, bus_addr_t *intrmapptr, 636 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 637{ 638 bus_addr_t intrmap, intrclr; 639 u_int64_t im; 640 u_long diag; 641 int found; 642 643 found = 0; 644 /* Hunt thru obio first */ 645 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 646 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 647 intrmap <= PSR_FFB1_INT_MAP; intrmap += 8, intrclr += 8, 648 diag >>= 2) { 649 im = PSYCHO_READ8(sc, intrmap); 650 if (INTINO(im) == ino) { 651 diag &= 2; 652 found = 1; 653 break; 654 } 655 } 656 657 if (!found) { 658 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 659 /* Now do PCI interrupts */ 660 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 661 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 662 diag >>= 8) { 663 im = PSYCHO_READ8(sc, intrmap); 664 if (((im ^ ino) & 0x3c) == 0) { 665 intrclr += 8 * (ino & 3); 666 diag = (diag >> ((ino & 3) * 2)) & 2; 667 found = 1; 668 break; 669 } 670 } 671 } 672 if (intrmapptr != NULL) 673 *intrmapptr = intrmap; 674 if (intrclrptr != NULL) 675 *intrclrptr = intrclr; 676 if (intrdiagptr != NULL) 677 *intrdiagptr = diag; 678 return (found); 679} 680 681/* grovel the OBP for various psycho properties */ 682static void 683psycho_get_ranges(phandle_t node, struct upa_ranges **rp, int *np) 684{ 685 686 *np = OF_getprop_alloc(node, "ranges", sizeof(**rp), (void **)rp); 687 if (*np == -1) 688 panic("could not get psycho ranges"); 689} 690 691/* 692 * Interrupt handlers. 693 */ 694static void 695psycho_ue(void *arg) 696{ 697 struct psycho_softc *sc = (struct psycho_softc *)arg; 698 u_int64_t afar, afsr; 699 700 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 701 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 702 /* 703 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 704 * the AFAR to be set to the physical address of the TTE entry that 705 * was invalid/write protected. Call into the iommu code to have 706 * them decoded to virtual IO addresses. 707 */ 708 if ((afsr & UEAFSR_P_DTE) != 0) 709 iommu_decode_fault(sc->sc_is, afar); 710 /* It's uncorrectable. Dump the regs and panic. */ 711 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx\n", 712 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 713} 714 715static void 716psycho_ce(void *arg) 717{ 718 struct psycho_softc *sc = (struct psycho_softc *)arg; 719 u_int64_t afar, afsr; 720 721 PSYCHO_WRITE8(sc, PSR_CE_INT_CLR, 0); 722 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 723 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 724 /* It's correctable. Dump the regs and continue. */ 725 printf("%s: correctable DMA error AFAR %#lx AFSR %#lx\n", 726 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 727} 728 729static void 730psycho_bus_a(void *arg) 731{ 732 struct psycho_softc *sc = (struct psycho_softc *)arg; 733 u_int64_t afar, afsr; 734 735 afar = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFA); 736 afsr = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFS); 737 /* It's uncorrectable. Dump the regs and panic. */ 738 panic("%s: PCI bus A error AFAR %#lx AFSR %#lx\n", 739 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 740} 741 742static void 743psycho_bus_b(void *arg) 744{ 745 struct psycho_softc *sc = (struct psycho_softc *)arg; 746 u_int64_t afar, afsr; 747 748 afar = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFA); 749 afsr = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFS); 750 /* It's uncorrectable. Dump the regs and panic. */ 751 panic("%s: PCI bus B error AFAR %#lx AFSR %#lx\n", 752 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 753} 754 755static void 756psycho_powerfail(void *arg) 757{ 758 759 /* We lost power. Try to shut down NOW. */ 760#ifdef DEBUGGER_ON_POWERFAIL 761 struct psycho_softc *sc = (struct psycho_softc *)arg; 762 763 Debugger("powerfail"); 764 PSYCHO_WRITE8(sc, PSR_POWER_INT_CLR, 0); 765#else 766 printf("Power Failure Detected: Shutting down NOW.\n"); 767 shutdown_nice(0); 768#endif 769} 770 771#ifdef PSYCHO_MAP_WAKEUP 772static void 773psycho_wakeup(void *arg) 774{ 775 struct psycho_softc *sc = (struct psycho_softc *)arg; 776 777 PSYCHO_WRITE8(sc, PSR_PWRMGT_INT_CLR, 0); 778 /* Gee, we don't really have a framework to deal with this properly. */ 779 printf("%s: power management wakeup\n", device_get_name(sc->sc_dev)); 780} 781#endif /* PSYCHO_MAP_WAKEUP */ 782 783/* initialise the IOMMU... */ 784void 785psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 786{ 787 char *name; 788 struct iommu_state *is = sc->sc_is; 789 u_int32_t iobase = -1; 790 int *vdma = NULL; 791 int nitem; 792 793 /* punch in our copies */ 794 is->is_bustag = sc->sc_bustag; 795 is->is_bushandle = sc->sc_bushandle; 796 is->is_iommu = PSR_IOMMU; 797 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 798 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 799 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 800 is->is_dva = PSR_IOMMU_SVADIAG; 801 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 802 803 /* 804 * Separate the men from the boys. Get the `virtual-dma' 805 * property for sabre and use that to make sure the damn 806 * iommu works. 807 * 808 * We could query the `#virtual-dma-size-cells' and 809 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 810 */ 811 nitem = OF_getprop_alloc(sc->sc_node, "virtual-dma", sizeof(vdma), 812 (void **)&vdma); 813 if (nitem > 0) { 814 iobase = vdma[0]; 815 tsbsize = ffs(vdma[1]); 816 if (tsbsize < 25 || tsbsize > 31 || 817 (vdma[1] & ~(1 << (tsbsize - 1))) != 0) { 818 printf("bogus tsb size %x, using 7\n", vdma[1]); 819 tsbsize = 31; 820 } 821 tsbsize -= 24; 822 free(vdma, M_OFWPROP); 823 } 824 825 /* give us a nice name.. */ 826 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 827 if (name == 0) 828 panic("couldn't malloc iommu name"); 829 snprintf(name, 32, "%s dvma", device_get_name(sc->sc_dev)); 830 831 iommu_init(name, is, tsbsize, iobase); 832} 833 834static int 835psycho_maxslots(device_t dev) 836{ 837 838 /* 839 * XXX: is this correct? At any rate, a number that is too high 840 * shouldn't do any harm, if only because of the way things are 841 * handled in psycho_read_config. 842 */ 843 return (31); 844} 845 846/* 847 * Keep a table of quirky PCI devices that need fixups before the MI PCI code 848 * creates the resource lists. This needs to be moved around once other bus 849 * drivers are added. Moving it to the MI code should maybe be reconsidered 850 * if one of these devices appear in non-sparc64 boxen. It's likely that not 851 * all BIOSes/firmwares can deal with them. 852 */ 853struct psycho_dquirk { 854 u_int32_t dq_devid; 855 int dq_quirk; 856}; 857 858/* Quirk types. May be or'ed together. */ 859#define DQT_BAD_INTPIN 1 /* Intpin reg 0, but intpin used */ 860 861static struct psycho_dquirk dquirks[] = { 862 { 0x1001108e, DQT_BAD_INTPIN }, /* Sun HME (PCIO func. 1) */ 863 { 0x1101108e, DQT_BAD_INTPIN }, /* Sun GEM (PCIO2 func. 1) */ 864 { 0x1102108e, DQT_BAD_INTPIN }, /* Sun FireWire ctl. (PCIO2 func. 2) */ 865 { 0x1103108e, DQT_BAD_INTPIN }, /* Sun USB ctl. (PCIO2 func. 3) */ 866}; 867 868#define NDQUIRKS (sizeof(dquirks) / sizeof(dquirks[0])) 869 870static u_int32_t 871psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 872 int width) 873{ 874 struct psycho_softc *sc; 875 bus_space_handle_t bh; 876 u_long offset = 0; 877 u_int32_t r, devid; 878 int i; 879 880 /* 881 * The psycho bridge does not tolerate accesses to unconfigured PCI 882 * devices' or function's config space, so look up the device in the 883 * firmware device tree first, and if it is not present, return a value 884 * that will make the detection code think that there is no device here. 885 * This is ugly... 886 */ 887 if (reg == 0 && ofw_pci_find_node(bus, slot, func) == 0) 888 return (0xffffffff); 889 sc = (struct psycho_softc *)device_get_softc(dev); 890 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 891 bh = sc->sc_bh[PCI_CS_CONFIG]; 892 switch (width) { 893 case 1: 894 r = bus_space_read_1(sc->sc_cfgt, bh, offset); 895 break; 896 case 2: 897 r = bus_space_read_2(sc->sc_cfgt, bh, offset); 898 break; 899 case 4: 900 r = bus_space_read_4(sc->sc_cfgt, bh, offset); 901 break; 902 default: 903 panic("psycho_read_config: bad width"); 904 } 905 if (reg == PCIR_INTPIN && r == 0) { 906 /* Check for DQT_BAD_INTPIN quirk. */ 907 devid = psycho_read_config(dev, bus, slot, func, 908 PCIR_DEVVENDOR, 4); 909 for (i = 0; i < NDQUIRKS; i++) { 910 if (dquirks[i].dq_devid == devid) { 911 /* 912 * Need to set the intpin to a value != 0 so 913 * that the MI code will think that this device 914 * has an interrupt. 915 * Just use 1 (intpin a) for now. This is, of 916 * course, bogus, but since interrupts are 917 * routed in advance, this does not really 918 * matter. 919 */ 920 if ((dquirks[i].dq_quirk & DQT_BAD_INTPIN) != 0) 921 r = 1; 922 break; 923 } 924 } 925 } 926 return (r); 927} 928 929static void 930psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, 931 u_int reg, u_int32_t val, int width) 932{ 933 struct psycho_softc *sc; 934 bus_space_handle_t bh; 935 u_long offset = 0; 936 937 sc = (struct psycho_softc *)device_get_softc(dev); 938 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 939 bh = sc->sc_bh[PCI_CS_CONFIG]; 940 switch (width) { 941 case 1: 942 bus_space_write_1(sc->sc_cfgt, bh, offset, val); 943 break; 944 case 2: 945 bus_space_write_2(sc->sc_cfgt, bh, offset, val); 946 break; 947 case 4: 948 bus_space_write_4(sc->sc_cfgt, bh, offset, val); 949 break; 950 default: 951 panic("psycho_write_config: bad width"); 952 } 953} 954 955static int 956psycho_route_interrupt(device_t bus, device_t dev, int pin) 957{ 958 int intline; 959 960 /* 961 * XXX: ugly loathsome hack: 962 * We can't use ofw_pci_route_intr() here; the device passed may be 963 * the one of a bridge, so the original device can't be recovered. 964 * 965 * We need to use the firmware to route interrupts, however it has 966 * no interface which could be used to interpret intpins; instead, 967 * all assignments are done by device. 968 * 969 * The MI pci code will try to reroute interrupts of 0, although they 970 * are correct; all other interrupts are preinitialized, so if we 971 * get here, the intline is either 0 (so return 0), or we hit a 972 * device which was not preinitialized (e.g. hotplugged stuff), in 973 * which case we are lost. 974 */ 975 return (0); 976} 977 978static int 979psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 980{ 981 struct psycho_softc *sc; 982 983 sc = (struct psycho_softc *)device_get_softc(dev); 984 switch (which) { 985 case PCIB_IVAR_BUS: 986 *result = sc->sc_busno; 987 return (0); 988 } 989 return (ENOENT); 990} 991 992/* Write to the correct clr register, and call the actual handler. */ 993static void 994psycho_intr_stub(void *arg) 995{ 996 struct psycho_clr *pc; 997 998 pc = (struct psycho_clr *)arg; 999 pc->pci_handler(pc->pci_arg); 1000 PSYCHO_WRITE8(pc->pci_sc, pc->pci_clr, 0); 1001} 1002 1003#ifdef PSYCHO_STRAY 1004/* 1005 * Write to the correct clr register and return. arg is the address of the clear 1006 * register to be used. 1007 * XXX: print a message? 1008 */ 1009static void 1010psycho_intr_stray(void *arg) 1011{ 1012 struct psycho_strayclr *sclr = arg; 1013 1014 PSYCHO_WRITE8(sclr->psc_sc, sclr->psc_clr, 0); 1015} 1016#endif 1017 1018static int 1019psycho_setup_intr(device_t dev, device_t child, 1020 struct resource *ires, int flags, driver_intr_t *intr, void *arg, 1021 void **cookiep) 1022{ 1023 struct psycho_softc *sc; 1024 struct psycho_clr *pc; 1025 bus_addr_t intrmapptr, intrclrptr; 1026 long vec = rman_get_start(ires); 1027 u_int64_t mr; 1028 int ino, error; 1029 1030 sc = (struct psycho_softc *)device_get_softc(dev); 1031 pc = (struct psycho_clr *)malloc(sizeof(*pc), M_DEVBUF, M_NOWAIT); 1032 if (pc == NULL) 1033 return (NULL); 1034 1035 /* 1036 * Hunt through all the interrupt mapping regs to look for our 1037 * interrupt vector. 1038 * 1039 * XXX We only compare INOs rather than IGNs since the firmware may 1040 * not provide the IGN and the IGN is constant for all device on that 1041 * PCI controller. This could cause problems for the FFB/external 1042 * interrupt which has a full vector that can be set arbitrarily. 1043 */ 1044 ino = INTINO(vec); 1045 1046 if (!psycho_find_intrmap(sc, ino, &intrmapptr, &intrclrptr, NULL)) { 1047 printf("Cannot find interrupt vector %lx\n", vec); 1048 free(pc, M_DEVBUF); 1049 return (NULL); 1050 } 1051 1052#ifdef PSYCHO_DEBUG 1053 device_printf(dev, "psycho_setup_intr: INO %d, map %#lx, clr %#lx\n", 1054 ino, (u_long)intrmapptr, (u_long)intrclrptr); 1055#endif 1056 pc->pci_sc = sc; 1057 pc->pci_arg = arg; 1058 pc->pci_handler = intr; 1059 pc->pci_clr = intrclrptr; 1060 /* Disable the interrupt while we fiddle with it */ 1061 mr = PSYCHO_READ8(sc, intrmapptr); 1062 PSYCHO_WRITE8(sc, intrmapptr, mr & ~INTMAP_V); 1063 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 1064 psycho_intr_stub, pc, cookiep); 1065 if (error != 0) { 1066 free(pc, M_DEVBUF); 1067 return (error); 1068 } 1069 pc->pci_cookie = *cookiep; 1070 *cookiep = pc; 1071 1072 /* 1073 * Clear the interrupt, it might have been triggered before it was 1074 * set up. 1075 */ 1076 PSYCHO_WRITE8(sc, intrclrptr, 0); 1077 /* 1078 * Enable the interrupt now we have the handler installed. 1079 * Read the current value as we can't change it besides the 1080 * valid bit so so make sure only this bit is changed. 1081 */ 1082 PSYCHO_WRITE8(sc, intrmapptr, mr | INTMAP_V); 1083 return (error); 1084} 1085 1086static int 1087psycho_teardown_intr(device_t dev, device_t child, 1088 struct resource *vec, void *cookie) 1089{ 1090 struct psycho_clr *pc; 1091 int error; 1092 1093 pc = (struct psycho_clr *)cookie; 1094 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 1095 pc->pci_cookie); 1096 /* 1097 * Don't disable the interrupt for now, so that stray interupts get 1098 * detected... 1099 */ 1100 if (error != 0) 1101 free(pc, M_DEVBUF); 1102 return (error); 1103} 1104 1105static struct resource * 1106psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1107 u_long start, u_long end, u_long count, u_int flags) 1108{ 1109 struct psycho_softc *sc; 1110 struct resource *rv; 1111 struct rman *rm; 1112 bus_space_tag_t bt; 1113 bus_space_handle_t bh; 1114 int needactivate = flags & RF_ACTIVE; 1115 1116 flags &= ~RF_ACTIVE; 1117 1118 sc = (struct psycho_softc *)device_get_softc(bus); 1119 if (type == SYS_RES_IRQ) { 1120 /* 1121 * XXX: Don't accept blank ranges for now, only single 1122 * interrupts. The other case should not happen with the MI pci 1123 * code... 1124 * XXX: This may return a resource that is out of the range 1125 * that was specified. Is this correct...? 1126 */ 1127 if (start != end) 1128 panic("psycho_alloc_resource: XXX: interrupt range"); 1129 start = end |= sc->sc_ign; 1130 return (bus_alloc_resource(bus, type, rid, start, end, 1131 count, flags)); 1132 } 1133 switch (type) { 1134 case SYS_RES_MEMORY: 1135 rm = &sc->sc_mem_rman; 1136 bt = sc->sc_memt; 1137 bh = sc->sc_bh[PCI_CS_MEM32]; 1138 break; 1139 case SYS_RES_IOPORT: 1140 rm = &sc->sc_io_rman; 1141 bt = sc->sc_iot; 1142 /* XXX: probably should use ranges property here. */ 1143 bh = sc->sc_bh[PCI_CS_IO]; 1144 break; 1145 default: 1146 return (NULL); 1147 } 1148 1149 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1150 if (rv == NULL) 1151 return (NULL); 1152 1153 bh += rman_get_start(rv); 1154 rman_set_bustag(rv, bt); 1155 rman_set_bushandle(rv, bh); 1156 1157 if (needactivate) { 1158 if (bus_activate_resource(child, type, *rid, rv)) { 1159 rman_release_resource(rv); 1160 return (NULL); 1161 } 1162 } 1163 1164 return (rv); 1165} 1166 1167static int 1168psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1169 struct resource *r) 1170{ 1171 void *p; 1172 int error; 1173 1174 if (type == SYS_RES_IRQ) 1175 return (bus_activate_resource(bus, type, rid, r)); 1176 if (type == SYS_RES_MEMORY) { 1177 /* 1178 * Need to memory-map the device space, as some drivers depend 1179 * on the virtual address being set and useable. 1180 */ 1181 error = sparc64_bus_mem_map(rman_get_bustag(r), 1182 rman_get_bushandle(r), rman_get_size(r), 0, NULL, &p); 1183 if (error != 0) 1184 return (error); 1185 rman_set_virtual(r, p); 1186 } 1187 return (rman_activate_resource(r)); 1188} 1189 1190static int 1191psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1192 struct resource *r) 1193{ 1194 1195 if (type == SYS_RES_IRQ) 1196 return (bus_deactivate_resource(bus, type, rid, r)); 1197 if (type == SYS_RES_MEMORY) { 1198 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1199 rman_set_virtual(r, NULL); 1200 } 1201 return (rman_deactivate_resource(r)); 1202} 1203 1204static int 1205psycho_release_resource(device_t bus, device_t child, int type, int rid, 1206 struct resource *r) 1207{ 1208 int error; 1209 1210 if (type == SYS_RES_IRQ) 1211 return (bus_release_resource(bus, type, rid, r)); 1212 if (rman_get_flags(r) & RF_ACTIVE) { 1213 error = bus_deactivate_resource(child, type, rid, r); 1214 if (error) 1215 return error; 1216 } 1217 return (rman_release_resource(r)); 1218} 1219 1220static int 1221psycho_intr_pending(device_t dev, int intr) 1222{ 1223 struct psycho_softc *sc; 1224 u_long diag; 1225 1226 sc = (struct psycho_softc *)device_get_softc(dev); 1227 if (!psycho_find_intrmap(sc, intr, NULL, NULL, &diag)) { 1228 printf("psycho_intr_pending: mapping not found for %d\n", intr); 1229 return (0); 1230 } 1231 return (diag != 0); 1232} 1233 1234static bus_space_handle_t 1235psycho_get_bus_handle(device_t dev, enum sbbt_id id, 1236 bus_space_handle_t childhdl, bus_space_tag_t *tag) 1237{ 1238 struct psycho_softc *sc; 1239 1240 sc = (struct psycho_softc *)device_get_softc(dev); 1241 switch(id) { 1242 case SBBT_IO: 1243 *tag = sc->sc_iot; 1244 return (sc->sc_bh[PCI_CS_IO] + childhdl); 1245 case SBBT_MEM: 1246 *tag = sc->sc_memt; 1247 return (sc->sc_bh[PCI_CS_MEM32] + childhdl); 1248 default: 1249 panic("psycho_get_bus_handle: illegal space\n"); 1250 } 1251} 1252 1253/* 1254 * below here is bus space and bus dma support 1255 */ 1256static bus_space_tag_t 1257psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1258{ 1259 bus_space_tag_t bt; 1260 1261 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1262 M_NOWAIT | M_ZERO); 1263 if (bt == NULL) 1264 panic("psycho_alloc_bus_tag: out of memory"); 1265 1266 bzero(bt, sizeof *bt); 1267 bt->cookie = sc; 1268 bt->parent = sc->sc_bustag; 1269 bt->type = type; 1270 return (bt); 1271} 1272 1273/* 1274 * hooks into the iommu dvma calls. 1275 */ 1276static int 1277psycho_dmamem_alloc(bus_dma_tag_t dmat, void **vaddr, int flags, bus_dmamap_t *mapp) 1278{ 1279 struct psycho_softc *sc; 1280 1281 sc = (struct psycho_softc *)dmat->cookie; 1282 return (iommu_dvmamem_alloc(dmat, sc->sc_is, vaddr, flags, mapp)); 1283} 1284 1285static void 1286psycho_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map) 1287{ 1288 struct psycho_softc *sc; 1289 1290 sc = (struct psycho_softc *)dmat->cookie; 1291 iommu_dvmamem_free(dmat, sc->sc_is, vaddr, map); 1292} 1293 1294static int 1295psycho_dmamap_create(bus_dma_tag_t dmat, int flags, bus_dmamap_t *mapp) 1296{ 1297 struct psycho_softc *sc; 1298 1299 sc = (struct psycho_softc *)dmat->cookie; 1300 return (iommu_dvmamap_create(dmat, sc->sc_is, flags, mapp)); 1301 1302} 1303 1304static int 1305psycho_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map) 1306{ 1307 struct psycho_softc *sc; 1308 1309 sc = (struct psycho_softc *)dmat->cookie; 1310 return (iommu_dvmamap_destroy(dmat, sc->sc_is, map)); 1311} 1312 1313static int 1314psycho_dmamap_load(bus_dma_tag_t dmat, bus_dmamap_t map, void *buf, 1315 bus_size_t buflen, bus_dmamap_callback_t *callback, void *callback_arg, 1316 int flags) 1317{ 1318 struct psycho_softc *sc; 1319 1320 sc = (struct psycho_softc *)dmat->cookie; 1321 return (iommu_dvmamap_load(dmat, sc->sc_is, map, buf, buflen, callback, 1322 callback_arg, flags)); 1323} 1324 1325static void 1326psycho_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t map) 1327{ 1328 struct psycho_softc *sc; 1329 1330 sc = (struct psycho_softc *)dmat->cookie; 1331 iommu_dvmamap_unload(dmat, sc->sc_is, map); 1332} 1333 1334static void 1335psycho_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, 1336 bus_dmasync_op_t op) 1337{ 1338 struct psycho_softc *sc; 1339 1340 sc = (struct psycho_softc *)dmat->cookie; 1341 iommu_dvmamap_sync(dmat, sc->sc_is, map, op); 1342} 1343