psycho.c revision 93053
1/* 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * All rights reserved. 4 * Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 30 * 31 * $FreeBSD: head/sys/sparc64/pci/psycho.c 93053 2002-03-23 20:42:23Z tmm $ 32 */ 33 34/* 35 * Support for `psycho' and `psycho+' UPA to PCI bridge and 36 * UltraSPARC IIi and IIe `sabre' PCI controllers. 37 */ 38 39#include "opt_psycho.h" 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/kernel.h> 45#include <sys/malloc.h> 46 47#include <ofw/openfirm.h> 48#include <ofw/ofw_pci.h> 49 50#include <machine/bus.h> 51#include <machine/iommureg.h> 52#include <machine/bus_common.h> 53#include <machine/frame.h> 54#include <machine/intr_machdep.h> 55#include <machine/nexusvar.h> 56#include <machine/ofw_upa.h> 57#include <machine/resource.h> 58 59#include <sys/rman.h> 60 61#include <machine/iommuvar.h> 62 63#include <pci/pcivar.h> 64#include <pci/pcireg.h> 65 66#include <sparc64/pci/ofw_pci.h> 67#include <sparc64/pci/psychoreg.h> 68#include <sparc64/pci/psychovar.h> 69 70#include "pcib_if.h" 71#include "sparcbus_if.h" 72 73static void psycho_get_ranges(phandle_t, struct upa_ranges **, int *); 74static void psycho_set_intr(struct psycho_softc *, int, device_t, bus_addr_t, 75 int, driver_intr_t); 76static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *, 77 bus_addr_t *, u_long *); 78static void psycho_intr_stub(void *); 79#ifdef PSYCHO_STRAY 80static void psycho_intr_stray(void *); 81#endif 82static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 83 84 85/* Interrupt handlers */ 86static void psycho_ue(void *); 87static void psycho_ce(void *); 88static void psycho_bus_a(void *); 89static void psycho_bus_b(void *); 90static void psycho_powerfail(void *); 91#ifdef PSYCHO_MAP_WAKEUP 92static void psycho_wakeup(void *); 93#endif 94 95/* IOMMU support */ 96static void psycho_iommu_init(struct psycho_softc *, int); 97 98/* 99 * bus space and bus dma support for UltraSPARC `psycho'. note that most 100 * of the bus dma support is provided by the iommu dvma controller. 101 */ 102static int psycho_dmamap_create(bus_dma_tag_t, int, bus_dmamap_t *); 103static int psycho_dmamap_destroy(bus_dma_tag_t, bus_dmamap_t); 104static int psycho_dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *, bus_size_t, 105 bus_dmamap_callback_t *, void *, int); 106static void psycho_dmamap_unload(bus_dma_tag_t, bus_dmamap_t); 107static void psycho_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_dmasync_op_t); 108static int psycho_dmamem_alloc(bus_dma_tag_t, void **, int, bus_dmamap_t *); 109static void psycho_dmamem_free(bus_dma_tag_t, void *, bus_dmamap_t); 110 111/* 112 * autoconfiguration 113 */ 114static int psycho_probe(device_t); 115static int psycho_attach(device_t); 116static int psycho_read_ivar(device_t, device_t, int, u_long *); 117static int psycho_setup_intr(device_t, device_t, struct resource *, int, 118 driver_intr_t *, void *, void **); 119static int psycho_teardown_intr(device_t, device_t, struct resource *, void *); 120static struct resource *psycho_alloc_resource(device_t, device_t, int, int *, 121 u_long, u_long, u_long, u_int); 122static int psycho_activate_resource(device_t, device_t, int, int, 123 struct resource *); 124static int psycho_deactivate_resource(device_t, device_t, int, int, 125 struct resource *); 126static int psycho_release_resource(device_t, device_t, int, int, 127 struct resource *); 128static int psycho_maxslots(device_t); 129static u_int32_t psycho_read_config(device_t, u_int, u_int, u_int, u_int, int); 130static void psycho_write_config(device_t, u_int, u_int, u_int, u_int, u_int32_t, 131 int); 132static int psycho_route_interrupt(device_t, device_t, int); 133static int psycho_intr_pending(device_t, int); 134static bus_space_handle_t psycho_get_bus_handle(device_t dev, enum sbbt_id id, 135 bus_space_handle_t childhdl, bus_space_tag_t *tag); 136 137static device_method_t psycho_methods[] = { 138 /* Device interface */ 139 DEVMETHOD(device_probe, psycho_probe), 140 DEVMETHOD(device_attach, psycho_attach), 141 142 /* Bus interface */ 143 DEVMETHOD(bus_print_child, bus_generic_print_child), 144 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 145 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 146 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 147 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 148 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 149 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 150 DEVMETHOD(bus_release_resource, psycho_release_resource), 151 152 /* pcib interface */ 153 DEVMETHOD(pcib_maxslots, psycho_maxslots), 154 DEVMETHOD(pcib_read_config, psycho_read_config), 155 DEVMETHOD(pcib_write_config, psycho_write_config), 156 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 157 158 /* sparcbus interface */ 159 DEVMETHOD(sparcbus_intr_pending, psycho_intr_pending), 160 DEVMETHOD(sparcbus_get_bus_handle, psycho_get_bus_handle), 161 162 { 0, 0 } 163}; 164 165static driver_t psycho_driver = { 166 "pcib", 167 psycho_methods, 168 sizeof(struct psycho_softc), 169}; 170 171static devclass_t psycho_devclass; 172 173DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 174 175static int psycho_ndevs; 176static struct psycho_softc *psycho_softcs[4]; 177 178struct psycho_clr { 179 struct psycho_softc *pci_sc; 180 bus_addr_t pci_clr; /* clear register */ 181 driver_intr_t *pci_handler; /* handler to call */ 182 void *pci_arg; /* argument for the handler */ 183 void *pci_cookie; /* interrupt cookie of parent bus */ 184}; 185 186struct psycho_strayclr { 187 struct psycho_softc *psc_sc; 188 bus_addr_t psc_clr; /* clear register */ 189}; 190 191#define PSYCHO_READ8(sc, off) \ 192 bus_space_read_8((sc)->sc_bustag, (sc)->sc_bushandle, (off)) 193#define PSYCHO_WRITE8(sc, off, v) \ 194 bus_space_write_8((sc)->sc_bustag, (sc)->sc_bushandle, (off), (v)) 195#define PCICTL_READ8(sc, off) \ 196 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 197#define PCICTL_WRITE8(sc, off, v) \ 198 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 199 200/* 201 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 202 * single PCI bus and does not have a streaming buffer. It often has an APB 203 * (advanced PCI bridge) connected to it, which was designed specifically for 204 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 205 * appears as two "simba"'s underneath the sabre. 206 * 207 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 208 * and manages two PCI buses. "psycho" has two 64-bit 33MHz buses, while 209 * "psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 210 * will usually find a "psycho+" since I don't think the original "psycho" 211 * ever shipped, and if it did it would be in the U30. 212 * 213 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 214 * both part of the same IC, they only have a single register space. As such, 215 * they need to be configured together, even though the autoconfiguration will 216 * attach them separately. 217 * 218 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 219 * as pci1 and pci2, although they have been implemented with other PCI bus 220 * numbers on some machines. 221 * 222 * On UltraII machines, there can be any number of "psycho+" ICs, each 223 * providing two PCI buses. 224 * 225 * 226 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 227 * the values of the following interrupts in this order: 228 * 229 * PCI Bus Error (30) 230 * DMA UE (2e) 231 * DMA CE (2f) 232 * Power Fail (25) 233 * 234 * We really should attach handlers for each. 235 */ 236#define OFW_PCI_TYPE "pci" 237#define OFW_SABRE_MODEL "SUNW,sabre" 238#define OFW_SABRE_COMPAT "pci108e,a001" 239#define OFW_SIMBA_MODEL "SUNW,simba" 240#define OFW_PSYCHO_MODEL "SUNW,psycho" 241 242static int 243psycho_probe(device_t dev) 244{ 245 phandle_t node; 246 char *dtype, *model; 247 static char compat[32]; 248 249 node = nexus_get_node(dev); 250 if (OF_getprop(node, "compatible", compat, sizeof(compat)) == -1) 251 compat[0] = '\0'; 252 253 dtype = nexus_get_device_type(dev); 254 model = nexus_get_model(dev); 255 /* match on a type of "pci" and a sabre or a psycho */ 256 if (nexus_get_reg(dev) != NULL && dtype != NULL && 257 strcmp(dtype, OFW_PCI_TYPE) == 0 && 258 ((model != NULL && (strcmp(model, OFW_SABRE_MODEL) == 0 || 259 strcmp(model, OFW_PSYCHO_MODEL) == 0)) || 260 strcmp(compat, OFW_SABRE_COMPAT) == 0)) { 261 device_set_desc(dev, "U2P UPA-PCI bridge"); 262 return (0); 263 } 264 265 return (ENXIO); 266} 267 268/* 269 * SUNW,psycho initialisation .. 270 * - find the per-psycho registers 271 * - figure out the IGN. 272 * - find our partner psycho 273 * - configure ourselves 274 * - bus range, bus, 275 * - interrupt map, 276 * - setup the chipsets. 277 * - if we're the first of the pair, initialise the IOMMU, otherwise 278 * just copy it's tags and addresses. 279 */ 280static int 281psycho_attach(device_t dev) 282{ 283 struct psycho_softc *sc; 284 struct psycho_softc *osc = NULL; 285 struct psycho_softc *asc; 286 struct upa_regs *reg; 287 char compat[32]; 288 char *model; 289 phandle_t node; 290 u_int64_t csr; 291 u_long pcictl_offs, mlen; 292 int psycho_br[2]; 293 int n, i, nreg, rid; 294#if defined(PSYCHO_DEBUG) || defined(PSYCHO_STRAY) 295 bus_addr_t map, clr; 296 u_int64_t mr; 297#endif 298#ifdef PSYCHO_STRAY 299 struct psycho_strayclr *sclr; 300#endif 301 302 node = nexus_get_node(dev); 303 sc = device_get_softc(dev); 304 if (OF_getprop(node, "compatible", compat, sizeof(compat)) == -1) 305 compat[0] = '\0'; 306 307 sc->sc_node = node; 308 sc->sc_dev = dev; 309 sc->sc_dmatag = nexus_get_dmatag(dev); 310 311 /* 312 * call the model-specific initialisation routine. 313 */ 314 model = nexus_get_model(dev); 315 if ((model != NULL && 316 strcmp(model, OFW_SABRE_MODEL) == 0) || 317 strcmp(compat, OFW_SABRE_COMPAT) == 0) { 318 sc->sc_mode = PSYCHO_MODE_SABRE; 319 if (model == NULL) 320 model = "sabre"; 321 } else if (model != NULL && 322 strcmp(model, OFW_PSYCHO_MODEL) == 0) 323 sc->sc_mode = PSYCHO_MODE_PSYCHO; 324 else 325 panic("psycho_attach: unknown model!"); 326 327 /* 328 * The psycho gets three register banks: 329 * (0) per-PBM configuration and status registers 330 * (1) per-PBM PCI configuration space, containing only the 331 * PBM 256-byte PCI header 332 * (2) the shared psycho configuration registers (struct psychoreg) 333 * 334 * XXX use the prom address for the psycho registers? we do so far. 335 */ 336 reg = nexus_get_reg(dev); 337 nreg = nexus_get_nreg(dev); 338 /* Register layouts are different. stuupid. */ 339 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 340 if (nreg <= 2) 341 panic("psycho_attach: %d not enough registers", nreg); 342 sc->sc_basepaddr = (vm_offset_t)UPA_REG_PHYS(®[2]); 343 mlen = UPA_REG_SIZE(®[2]); 344 pcictl_offs = UPA_REG_PHYS(®[0]); 345 } else { 346 if (nreg <= 0) 347 panic("psycho_attach: %d not enough registers", nreg); 348 sc->sc_basepaddr = (vm_offset_t)UPA_REG_PHYS(®[0]); 349 mlen = UPA_REG_SIZE(reg); 350 pcictl_offs = sc->sc_basepaddr + PSR_PCICTL0; 351 } 352 353 /* 354 * Match other psycho's that are already configured against 355 * the base physical address. This will be the same for a 356 * pair of devices that share register space. 357 */ 358 for (n = 0; n < psycho_ndevs && n < sizeof(psycho_softcs) / 359 sizeof(psycho_softcs[0]); n++) { 360 asc = (struct psycho_softc *)psycho_softcs[n]; 361 362 if (asc == NULL || asc == sc) 363 /* This entry is not there or it is me */ 364 continue; 365 366 if (asc->sc_basepaddr != sc->sc_basepaddr) 367 /* This is an unrelated psycho */ 368 continue; 369 370 /* Found partner */ 371 osc = asc; 372 break; 373 } 374 375 if (osc == NULL) { 376 rid = 0; 377 sc->sc_mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 378 sc->sc_basepaddr, sc->sc_basepaddr + mlen - 1, mlen, 379 RF_ACTIVE); 380 if (sc->sc_mem_res == NULL || 381 rman_get_start(sc->sc_mem_res) != sc->sc_basepaddr) 382 panic("psycho_attach: can't allocate device memory"); 383 sc->sc_bustag = rman_get_bustag(sc->sc_mem_res); 384 sc->sc_bushandle = rman_get_bushandle(sc->sc_mem_res); 385 } else { 386 /* 387 * There's another psycho using the same register space. Copy the 388 * relevant stuff. 389 */ 390 sc->sc_mem_res = NULL; 391 sc->sc_bustag = osc->sc_bustag; 392 sc->sc_bushandle = osc->sc_bushandle; 393 } 394 if (pcictl_offs < sc->sc_basepaddr) 395 panic("psycho_attach: bogus pci control register location"); 396 sc->sc_pcictl = pcictl_offs - sc->sc_basepaddr; 397 csr = PSYCHO_READ8(sc, PSR_CS); 398 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 399 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 400 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 401 402 device_printf(dev, "%s: impl %d, version %d: ign %x ", 403 model, (int)PSYCHO_GCSR_IMPL(csr), (int)PSYCHO_GCSR_VERS(csr), 404 sc->sc_ign); 405 406 /* 407 * Setup the PCI control register 408 */ 409 csr = PCICTL_READ8(sc, PCR_CS); 410 csr |= PCICTL_MRLM | PCICTL_ARB_PARK | PCICTL_ERRINTEN | PCICTL_4ENABLE; 411 csr &= ~(PCICTL_SERR | PCICTL_CPU_PRIO | PCICTL_ARB_PRIO | 412 PCICTL_RTRYWAIT); 413 PCICTL_WRITE8(sc, PCR_CS, csr); 414 415 /* grab the psycho ranges */ 416 psycho_get_ranges(sc->sc_node, &sc->sc_range, &sc->sc_nrange); 417 418 /* get the bus-range for the psycho */ 419 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br)); 420 if (n == -1) 421 panic("could not get psycho bus-range"); 422 if (n != sizeof(psycho_br)) 423 panic("broken psycho bus-range (%d)", n); 424 425 printf("bus range %u to %u; PCI bus %d\n", psycho_br[0], psycho_br[1], 426 psycho_br[0]); 427 428 sc->sc_busno = psycho_br[0]; 429 430 /* Initialize memory and i/o rmans */ 431 sc->sc_io_rman.rm_type = RMAN_ARRAY; 432 sc->sc_io_rman.rm_descr = "Psycho PCI I/O Ports"; 433 if (rman_init(&sc->sc_io_rman) != 0 || 434 rman_manage_region(&sc->sc_io_rman, 0, PSYCHO_IO_SIZE) != 0) 435 panic("psycho_probe: failed to set up i/o rman"); 436 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 437 sc->sc_mem_rman.rm_descr = "Psycho PCI Memory"; 438 if (rman_init(&sc->sc_mem_rman) != 0 || 439 rman_manage_region(&sc->sc_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 440 panic("psycho_probe: failed to set up memory rman"); 441 /* 442 * Find the addresses of the various bus spaces. 443 * There should not be multiple ones of one kind. 444 * The physical start addresses of the ranges are the configuration, 445 * memory and IO handles. 446 */ 447 for (n = 0; n < sc->sc_nrange; n++) { 448 i = UPA_RANGE_CS(&sc->sc_range[n]); 449 if (sc->sc_bh[i] != 0) 450 panic("psycho_attach: duplicate range for space %d", i); 451 sc->sc_bh[i] = UPA_RANGE_PHYS(&sc->sc_range[n]); 452 } 453 /* 454 * Check that all needed handles are present. The PCI_CS_MEM64 one is 455 * not currently used. 456 */ 457 for (n = 0; n < 3; n++) { 458 if (sc->sc_bh[n] == 0) 459 panic("psycho_attach: range %d missing", n); 460 } 461 462 /* allocate our tags */ 463 sc->sc_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 464 sc->sc_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 465 sc->sc_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 466 if (bus_dma_tag_create(sc->sc_dmatag, 8, 1, 0, 0x3ffffffff, NULL, NULL, 467 0x3ffffffff, 0xff, 0xffffffff, 0, &sc->sc_dmat) != 0) 468 panic("psycho_attach: bus_dma_tag_create failed"); 469 /* Customize the tag */ 470 sc->sc_dmat->cookie = sc; 471 sc->sc_dmat->dmamap_create = psycho_dmamap_create; 472 sc->sc_dmat->dmamap_destroy = psycho_dmamap_destroy; 473 sc->sc_dmat->dmamap_load = psycho_dmamap_load; 474 sc->sc_dmat->dmamap_unload = psycho_dmamap_unload; 475 sc->sc_dmat->dmamap_sync = psycho_dmamap_sync; 476 sc->sc_dmat->dmamem_alloc = psycho_dmamem_alloc; 477 sc->sc_dmat->dmamem_free = psycho_dmamem_free; 478 /* XXX: register as root dma tag (kluge). */ 479 sparc64_root_dma_tag = sc->sc_dmat; 480 481 if ((sc->sc_nintrmap = OF_getprop_alloc(sc->sc_node, "interrupt-map", 482 sizeof(*sc->sc_intrmap), (void **)&sc->sc_intrmap)) == -1 || 483 OF_getprop(sc->sc_node, "interrupt-map-mask", &sc->sc_intrmapmsk, 484 sizeof(sc->sc_intrmapmsk)) == -1) { 485 if (sc->sc_intrmap != NULL) { 486 free(sc->sc_intrmap, M_OFWPROP); 487 sc->sc_intrmap = NULL; 488 } 489 } 490 491 /* Register the softc, this is needed for paired psychos. */ 492 if (psycho_ndevs < sizeof(psycho_softcs) / sizeof(psycho_softcs[0])) 493 psycho_softcs[psycho_ndevs] = sc; 494 else 495 device_printf(dev, "XXX: bump the number of psycho_softcs"); 496 psycho_ndevs++; 497 /* 498 * And finally, if we're a sabre or the first of a pair of psycho's to 499 * arrive here, start up the IOMMU and get a config space tag. 500 */ 501 if (osc == NULL) { 502 /* 503 * Establish handlers for interesting interrupts.... 504 * 505 * XXX We need to remember these and remove this to support 506 * hotplug on the UPA/FHC bus. 507 * 508 * XXX Not all controllers have these, but installing them 509 * is better than trying to sort through this mess. 510 */ 511 psycho_set_intr(sc, 0, dev, PSR_UE_INT_MAP, INTR_FAST, 512 psycho_ue); 513 psycho_set_intr(sc, 1, dev, PSR_CE_INT_MAP, 0, psycho_ce); 514 psycho_set_intr(sc, 2, dev, PSR_PCIAERR_INT_MAP, INTR_FAST, 515 psycho_bus_a); 516 psycho_set_intr(sc, 3, dev, PSR_PCIBERR_INT_MAP, INTR_FAST, 517 psycho_bus_b); 518 psycho_set_intr(sc, 4, dev, PSR_POWER_INT_MAP, INTR_FAST, 519 psycho_powerfail); 520#ifdef PSYCHO_MAP_WAKEUP 521 /* 522 * On some models, this is mapped to the same interrupt as 523 * pciberr by default, so leave it alone for now since 524 * psycho_wakeup() doesn't do anything useful anyway. 525 */ 526 psycho_set_intr(sc, 5, dev, PSR_PWRMGT_INT_MAP, 0, 527 psycho_wakeup); 528#endif /* PSYCHO_MAP_WAKEUP */ 529 530 531 /* Initialize the counter-timer if we handle a psycho. */ 532 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 533 sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, 534 PSR_TC0); 535 } 536 537 /* 538 * Setup IOMMU and PCI configuration if we're the first 539 * of a pair of psycho's to arrive here. 540 * 541 * We should calculate a TSB size based on amount of RAM 542 * and number of bus controllers and number an type of 543 * child devices. 544 * 545 * For the moment, 32KB should be more than enough. 546 */ 547 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 548 M_NOWAIT); 549 if (sc->sc_is == NULL) 550 panic("psycho_attach: malloc iommu_state failed"); 551 sc->sc_is->is_sb[0] = 0; 552 sc->sc_is->is_sb[1] = 0; 553 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 554 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 555 psycho_iommu_init(sc, 2); 556 } else { 557 /* Just copy IOMMU state, config tag and address */ 558 sc->sc_is = osc->sc_is; 559 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 560 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 561 iommu_reset(sc->sc_is); 562 } 563 564 /* 565 * Enable all interrupts, clear all interrupt states, and install an 566 * interrupt handler for OBIO interrupts, which can be ISA ones 567 * (to frob the interrupt clear registers). 568 * This aids the debugging of interrupt routing problems, and is needed 569 * for isa drivers that use isa_irq_pending (otherwise the registers 570 * will never be cleared). 571 */ 572#if defined(PSYCHO_DEBUG) || defined(PSYCHO_STRAY) 573 for (map = PSR_PCIA0_INT_MAP, clr = PSR_PCIA0_INT_CLR, n = 0; 574 map <= PSR_PCIB3_INT_MAP; map += 8, clr += 32, n++) { 575 mr = PSYCHO_READ8(sc, map); 576#ifdef PSYCHO_DEBUG 577 device_printf(dev, "intr map (pci) %d: %#lx\n", n, (u_long)mr); 578#endif 579 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 580 for (i = 0; i < 4; i++) 581 PCICTL_WRITE8(sc, clr + i * 8, 0); 582 PSYCHO_WRITE8(sc, map, mr | INTMAP_V); 583 } 584 for (map = PSR_SCSI_INT_MAP, clr = PSR_SCSI_INT_CLR, n = 0; 585 map <= PSR_FFB1_INT_MAP; map += 8, clr += 8, n++) { 586 mr = PSYCHO_READ8(sc, map); 587#ifdef PSYCHO_DEBUG 588 device_printf(dev, "intr map (obio) %d: %#lx, clr: %#lx\n", n, 589 (u_long)mr, (u_long)clr); 590#endif 591 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 592 PSYCHO_WRITE8(sc, clr, 0); 593#ifdef PSYCHO_STRAY 594 /* 595 * This can cause interrupt storms, and is therefore disabled 596 * by default. 597 * XXX: use intr_setup() to not confuse higher level code 598 */ 599 if (INTVEC(mr) != 0x7e6 && INTVEC(mr) != 0x7e7 && 600 INTVEC(mr) != 0) { 601 sclr = malloc(sizeof(*sclr), M_DEVBUF, M_WAITOK); 602 sclr->psc_sc = sc; 603 sclr->psc_clr = clr; 604 intr_setup(PIL_LOW, intr_dequeue, INTVEC(mr), 605 psycho_intr_stray, sclr); 606 } 607#endif 608 PSYCHO_WRITE8(sc, map, mr | INTMAP_V); 609 } 610#endif 611 612 /* 613 * Initialize the interrupt registers of all devices hanging from 614 * the host bridge directly or indirectly via PCI-PCI bridges. 615 * The MI code (and the PCI spec) assume that this is done during 616 * system initialization, however the firmware does not do this 617 * at least on some models, and we probably shouldn't trust that 618 * the firmware uses the same model as this driver if it does. 619 */ 620 ofw_pci_init_intr(dev, sc->sc_node, sc->sc_intrmap, sc->sc_nintrmap, 621 &sc->sc_intrmapmsk); 622 623 device_add_child(dev, "pci", device_get_unit(dev)); 624 return (bus_generic_attach(dev)); 625} 626 627static void 628psycho_set_intr(struct psycho_softc *sc, int index, 629 device_t dev, bus_addr_t map, int iflags, driver_intr_t handler) 630{ 631 int rid, vec; 632 u_int64_t mr; 633 634 mr = PSYCHO_READ8(sc, map); 635 vec = INTVEC(mr); 636 sc->sc_irq_res[index] = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 637 vec, vec, 1, RF_ACTIVE); 638 if (sc->sc_irq_res[index] == NULL) 639 panic("psycho_set_intr: failed to get interrupt"); 640 bus_setup_intr(dev, sc->sc_irq_res[index], INTR_TYPE_MISC | iflags, 641 handler, sc, &sc->sc_ihand[index]); 642 PSYCHO_WRITE8(sc, map, mr | INTMAP_V); 643} 644 645static int 646psycho_find_intrmap(struct psycho_softc *sc, int ino, bus_addr_t *intrmapptr, 647 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 648{ 649 bus_addr_t intrmap, intrclr; 650 u_int64_t im; 651 u_long diag; 652 int found; 653 654 found = 0; 655 /* Hunt thru obio first */ 656 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 657 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 658 intrmap <= PSR_FFB1_INT_MAP; intrmap += 8, intrclr += 8, 659 diag >>= 2) { 660 im = PSYCHO_READ8(sc, intrmap); 661 if (INTINO(im) == ino) { 662 diag &= 2; 663 found = 1; 664 break; 665 } 666 } 667 668 if (!found) { 669 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 670 /* Now do PCI interrupts */ 671 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 672 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 673 diag >>= 8) { 674 im = PSYCHO_READ8(sc, intrmap); 675 if (((im ^ ino) & 0x3c) == 0) { 676 intrclr += 8 * (ino & 3); 677 diag = (diag >> ((ino & 3) * 2)) & 2; 678 found = 1; 679 break; 680 } 681 } 682 } 683 if (intrmapptr != NULL) 684 *intrmapptr = intrmap; 685 if (intrclrptr != NULL) 686 *intrclrptr = intrclr; 687 if (intrdiagptr != NULL) 688 *intrdiagptr = diag; 689 return (found); 690} 691 692/* grovel the OBP for various psycho properties */ 693static void 694psycho_get_ranges(phandle_t node, struct upa_ranges **rp, int *np) 695{ 696 697 *np = OF_getprop_alloc(node, "ranges", sizeof(**rp), (void **)rp); 698 if (*np == -1) 699 panic("could not get psycho ranges"); 700} 701 702/* 703 * Interrupt handlers. 704 */ 705static void 706psycho_ue(void *arg) 707{ 708 struct psycho_softc *sc = (struct psycho_softc *)arg; 709 u_int64_t afar, afsr; 710 711 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 712 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 713 /* 714 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 715 * the AFAR to be set to the physical address of the TTE entry that 716 * was invalid/write protected. Call into the iommu code to have 717 * them decoded to virtual IO addresses. 718 */ 719 if ((afsr & UEAFSR_P_DTE) != 0) 720 iommu_decode_fault(sc->sc_is, afar); 721 /* It's uncorrectable. Dump the regs and panic. */ 722 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx\n", 723 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 724} 725 726static void 727psycho_ce(void *arg) 728{ 729 struct psycho_softc *sc = (struct psycho_softc *)arg; 730 u_int64_t afar, afsr; 731 732 PSYCHO_WRITE8(sc, PSR_CE_INT_CLR, 0); 733 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 734 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 735 /* It's correctable. Dump the regs and continue. */ 736 printf("%s: correctable DMA error AFAR %#lx AFSR %#lx\n", 737 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 738} 739 740static void 741psycho_bus_a(void *arg) 742{ 743 struct psycho_softc *sc = (struct psycho_softc *)arg; 744 u_int64_t afar, afsr; 745 746 afar = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFA); 747 afsr = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFS); 748 /* It's uncorrectable. Dump the regs and panic. */ 749 panic("%s: PCI bus A error AFAR %#lx AFSR %#lx\n", 750 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 751} 752 753static void 754psycho_bus_b(void *arg) 755{ 756 struct psycho_softc *sc = (struct psycho_softc *)arg; 757 u_int64_t afar, afsr; 758 759 afar = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFA); 760 afsr = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFS); 761 /* It's uncorrectable. Dump the regs and panic. */ 762 panic("%s: PCI bus B error AFAR %#lx AFSR %#lx\n", 763 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 764} 765 766static void 767psycho_powerfail(void *arg) 768{ 769 770 /* We lost power. Try to shut down NOW. */ 771#ifdef DEBUGGER_ON_POWERFAIL 772 struct psycho_softc *sc = (struct psycho_softc *)arg; 773 774 Debugger("powerfail"); 775 PSYCHO_WRITE8(sc, PSR_POWER_INT_CLR, 0); 776#else 777 printf("Power Failure Detected: Shutting down NOW.\n"); 778 shutdown_nice(0); 779#endif 780} 781 782#ifdef PSYCHO_MAP_WAKEUP 783static void 784psycho_wakeup(void *arg) 785{ 786 struct psycho_softc *sc = (struct psycho_softc *)arg; 787 788 PSYCHO_WRITE8(sc, PSR_PWRMGT_INT_CLR, 0); 789 /* Gee, we don't really have a framework to deal with this properly. */ 790 printf("%s: power management wakeup\n", device_get_name(sc->sc_dev)); 791} 792#endif /* PSYCHO_MAP_WAKEUP */ 793 794/* initialise the IOMMU... */ 795void 796psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 797{ 798 char *name; 799 struct iommu_state *is = sc->sc_is; 800 u_int32_t iobase = -1; 801 int *vdma = NULL; 802 int nitem; 803 804 /* punch in our copies */ 805 is->is_bustag = sc->sc_bustag; 806 is->is_bushandle = sc->sc_bushandle; 807 is->is_iommu = PSR_IOMMU; 808 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 809 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 810 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 811 is->is_dva = PSR_IOMMU_SVADIAG; 812 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 813 814 /* 815 * Separate the men from the boys. Get the `virtual-dma' 816 * property for sabre and use that to make sure the damn 817 * iommu works. 818 * 819 * We could query the `#virtual-dma-size-cells' and 820 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 821 */ 822 nitem = OF_getprop_alloc(sc->sc_node, "virtual-dma", sizeof(vdma), 823 (void **)&vdma); 824 if (nitem > 0) { 825 iobase = vdma[0]; 826 tsbsize = ffs(vdma[1]); 827 if (tsbsize < 25 || tsbsize > 31 || 828 (vdma[1] & ~(1 << (tsbsize - 1))) != 0) { 829 printf("bogus tsb size %x, using 7\n", vdma[1]); 830 tsbsize = 31; 831 } 832 tsbsize -= 24; 833 free(vdma, M_OFWPROP); 834 } 835 836 /* give us a nice name.. */ 837 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 838 if (name == 0) 839 panic("couldn't malloc iommu name"); 840 snprintf(name, 32, "%s dvma", device_get_name(sc->sc_dev)); 841 842 iommu_init(name, is, tsbsize, iobase); 843} 844 845static int 846psycho_maxslots(device_t dev) 847{ 848 849 /* 850 * XXX: is this correct? At any rate, a number that is too high 851 * shouldn't do any harm, if only because of the way things are 852 * handled in psycho_read_config. 853 */ 854 return (31); 855} 856 857/* 858 * Keep a table of quirky PCI devices that need fixups before the MI PCI code 859 * creates the resource lists. This needs to be moved around once other bus 860 * drivers are added. Moving it to the MI code should maybe be reconsidered 861 * if one of these devices appear in non-sparc64 boxen. It's likely that not 862 * all BIOSes/firmwares can deal with them. 863 */ 864struct psycho_dquirk { 865 u_int32_t dq_devid; 866 int dq_quirk; 867}; 868 869/* Quirk types. May be or'ed together. */ 870#define DQT_BAD_INTPIN 1 /* Intpin reg 0, but intpin used */ 871 872static struct psycho_dquirk dquirks[] = { 873 { 0x1001108e, DQT_BAD_INTPIN }, /* Sun HME (PCIO func. 1) */ 874 { 0x1101108e, DQT_BAD_INTPIN }, /* Sun GEM (PCIO2 func. 1) */ 875 { 0x1102108e, DQT_BAD_INTPIN }, /* Sun FireWire ctl. (PCIO2 func. 2) */ 876 { 0x1103108e, DQT_BAD_INTPIN }, /* Sun USB ctl. (PCIO2 func. 3) */ 877}; 878 879#define NDQUIRKS (sizeof(dquirks) / sizeof(dquirks[0])) 880 881static u_int32_t 882psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 883 int width) 884{ 885 struct psycho_softc *sc; 886 bus_space_handle_t bh; 887 u_long offset = 0; 888 u_int32_t r, devid; 889 int i; 890 891 /* 892 * The psycho bridge does not tolerate accesses to unconfigured PCI 893 * devices' or function's config space, so look up the device in the 894 * firmware device tree first, and if it is not present, return a value 895 * that will make the detection code think that there is no device here. 896 * This is ugly... 897 */ 898 if (reg == 0 && ofw_pci_find_node(bus, slot, func) == 0) 899 return (0xffffffff); 900 sc = (struct psycho_softc *)device_get_softc(dev); 901 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 902 bh = sc->sc_bh[PCI_CS_CONFIG]; 903 switch (width) { 904 case 1: 905 r = bus_space_read_1(sc->sc_cfgt, bh, offset); 906 break; 907 case 2: 908 r = bus_space_read_2(sc->sc_cfgt, bh, offset); 909 break; 910 case 4: 911 r = bus_space_read_4(sc->sc_cfgt, bh, offset); 912 break; 913 default: 914 panic("psycho_read_config: bad width"); 915 } 916 if (reg == PCIR_INTPIN && r == 0) { 917 /* Check for DQT_BAD_INTPIN quirk. */ 918 devid = psycho_read_config(dev, bus, slot, func, 919 PCIR_DEVVENDOR, 4); 920 for (i = 0; i < NDQUIRKS; i++) { 921 if (dquirks[i].dq_devid == devid) { 922 /* 923 * Need to set the intpin to a value != 0 so 924 * that the MI code will think that this device 925 * has an interrupt. 926 * Just use 1 (intpin a) for now. This is, of 927 * course, bogus, but since interrupts are 928 * routed in advance, this does not really 929 * matter. 930 */ 931 if ((dquirks[i].dq_quirk & DQT_BAD_INTPIN) != 0) 932 r = 1; 933 break; 934 } 935 } 936 } 937 return (r); 938} 939 940static void 941psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, 942 u_int reg, u_int32_t val, int width) 943{ 944 struct psycho_softc *sc; 945 bus_space_handle_t bh; 946 u_long offset = 0; 947 948 sc = (struct psycho_softc *)device_get_softc(dev); 949 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 950 bh = sc->sc_bh[PCI_CS_CONFIG]; 951 switch (width) { 952 case 1: 953 bus_space_write_1(sc->sc_cfgt, bh, offset, val); 954 break; 955 case 2: 956 bus_space_write_2(sc->sc_cfgt, bh, offset, val); 957 break; 958 case 4: 959 bus_space_write_4(sc->sc_cfgt, bh, offset, val); 960 break; 961 default: 962 panic("psycho_write_config: bad width"); 963 } 964} 965 966static int 967psycho_route_interrupt(device_t bus, device_t dev, int pin) 968{ 969 970 /* 971 * Since we preinitialize all interrupt line registers, this should not 972 * happen for any built-in device. 973 * Devices on bridges that route interrupts cannot work now - the 974 * interrupt pin mappings are not known from the firmware... 975 */ 976 panic("psycho_route_interrupt"); 977} 978 979static int 980psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 981{ 982 struct psycho_softc *sc; 983 984 sc = (struct psycho_softc *)device_get_softc(dev); 985 switch (which) { 986 case PCIB_IVAR_BUS: 987 *result = sc->sc_busno; 988 return (0); 989 } 990 return (ENOENT); 991} 992 993/* Write to the correct clr register, and call the actual handler. */ 994static void 995psycho_intr_stub(void *arg) 996{ 997 struct psycho_clr *pc; 998 999 pc = (struct psycho_clr *)arg; 1000 pc->pci_handler(pc->pci_arg); 1001 PSYCHO_WRITE8(pc->pci_sc, pc->pci_clr, 0); 1002} 1003 1004#ifdef PSYCHO_STRAY 1005/* 1006 * Write to the correct clr register and return. arg is the address of the clear 1007 * register to be used. 1008 * XXX: print a message? 1009 */ 1010static void 1011psycho_intr_stray(void *arg) 1012{ 1013 struct psycho_strayclr *sclr = arg; 1014 1015 PSYCHO_WRITE8(sclr->psc_sc, sclr->psc_clr, 0); 1016} 1017#endif 1018 1019static int 1020psycho_setup_intr(device_t dev, device_t child, 1021 struct resource *ires, int flags, driver_intr_t *intr, void *arg, 1022 void **cookiep) 1023{ 1024 struct psycho_softc *sc; 1025 struct psycho_clr *pc; 1026 bus_addr_t intrmapptr, intrclrptr; 1027 long vec = rman_get_start(ires); 1028 u_int64_t mr; 1029 int ino, error; 1030 1031 sc = (struct psycho_softc *)device_get_softc(dev); 1032 pc = (struct psycho_clr *)malloc(sizeof(*pc), M_DEVBUF, M_NOWAIT); 1033 if (pc == NULL) 1034 return (NULL); 1035 1036 /* 1037 * Hunt through all the interrupt mapping regs to look for our 1038 * interrupt vector. 1039 * 1040 * XXX We only compare INOs rather than IGNs since the firmware may 1041 * not provide the IGN and the IGN is constant for all device on that 1042 * PCI controller. This could cause problems for the FFB/external 1043 * interrupt which has a full vector that can be set arbitrarily. 1044 */ 1045 ino = INTINO(vec); 1046 1047 if (!psycho_find_intrmap(sc, ino, &intrmapptr, &intrclrptr, NULL)) { 1048 printf("Cannot find interrupt vector %lx\n", vec); 1049 free(pc, M_DEVBUF); 1050 return (NULL); 1051 } 1052 1053#ifdef PSYCHO_DEBUG 1054 device_printf(dev, "psycho_setup_intr: INO %d, map %#lx, clr %#lx\n", 1055 ino, (u_long)intrmapptr, (u_long)intrclrptr); 1056#endif 1057 pc->pci_sc = sc; 1058 pc->pci_arg = arg; 1059 pc->pci_handler = intr; 1060 pc->pci_clr = intrclrptr; 1061 /* Disable the interrupt while we fiddle with it */ 1062 mr = PSYCHO_READ8(sc, intrmapptr); 1063 PSYCHO_WRITE8(sc, intrmapptr, mr & ~INTMAP_V); 1064 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 1065 psycho_intr_stub, pc, cookiep); 1066 if (error != 0) { 1067 free(pc, M_DEVBUF); 1068 return (error); 1069 } 1070 pc->pci_cookie = *cookiep; 1071 *cookiep = pc; 1072 1073 /* 1074 * Clear the interrupt, it might have been triggered before it was 1075 * set up. 1076 */ 1077 PSYCHO_WRITE8(sc, intrclrptr, 0); 1078 /* 1079 * Enable the interrupt now we have the handler installed. 1080 * Read the current value as we can't change it besides the 1081 * valid bit so so make sure only this bit is changed. 1082 */ 1083 PSYCHO_WRITE8(sc, intrmapptr, mr | INTMAP_V); 1084 return (error); 1085} 1086 1087static int 1088psycho_teardown_intr(device_t dev, device_t child, 1089 struct resource *vec, void *cookie) 1090{ 1091 struct psycho_clr *pc; 1092 int error; 1093 1094 pc = (struct psycho_clr *)cookie; 1095 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 1096 pc->pci_cookie); 1097 /* 1098 * Don't disable the interrupt for now, so that stray interupts get 1099 * detected... 1100 */ 1101 if (error != 0) 1102 free(pc, M_DEVBUF); 1103 return (error); 1104} 1105 1106static struct resource * 1107psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1108 u_long start, u_long end, u_long count, u_int flags) 1109{ 1110 struct psycho_softc *sc; 1111 struct resource *rv; 1112 struct rman *rm; 1113 bus_space_tag_t bt; 1114 bus_space_handle_t bh; 1115 int needactivate = flags & RF_ACTIVE; 1116 1117 flags &= ~RF_ACTIVE; 1118 1119 sc = (struct psycho_softc *)device_get_softc(bus); 1120 if (type == SYS_RES_IRQ) { 1121 /* 1122 * XXX: Don't accept blank ranges for now, only single 1123 * interrupts. The other case should not happen with the MI pci 1124 * code... 1125 * XXX: This may return a resource that is out of the range 1126 * that was specified. Is this correct...? 1127 */ 1128 if (start != end) 1129 panic("psycho_alloc_resource: XXX: interrupt range"); 1130 start = end |= sc->sc_ign; 1131 return (bus_alloc_resource(bus, type, rid, start, end, 1132 count, flags)); 1133 } 1134 switch (type) { 1135 case SYS_RES_MEMORY: 1136 rm = &sc->sc_mem_rman; 1137 bt = sc->sc_memt; 1138 bh = sc->sc_bh[PCI_CS_MEM32]; 1139 break; 1140 case SYS_RES_IOPORT: 1141 rm = &sc->sc_io_rman; 1142 bt = sc->sc_iot; 1143 /* XXX: probably should use ranges property here. */ 1144 bh = sc->sc_bh[PCI_CS_IO]; 1145 break; 1146 default: 1147 return (NULL); 1148 } 1149 1150 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1151 if (rv == NULL) 1152 return (NULL); 1153 1154 bh += rman_get_start(rv); 1155 rman_set_bustag(rv, bt); 1156 rman_set_bushandle(rv, bh); 1157 1158 if (needactivate) { 1159 if (bus_activate_resource(child, type, *rid, rv)) { 1160 rman_release_resource(rv); 1161 return (NULL); 1162 } 1163 } 1164 1165 return (rv); 1166} 1167 1168static int 1169psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1170 struct resource *r) 1171{ 1172 1173 if (type == SYS_RES_IRQ) 1174 return (bus_activate_resource(bus, type, rid, r)); 1175 return (rman_activate_resource(r)); 1176} 1177 1178static int 1179psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1180 struct resource *r) 1181{ 1182 1183 if (type == SYS_RES_IRQ) 1184 return (bus_deactivate_resource(bus, type, rid, r)); 1185 return (rman_deactivate_resource(r)); 1186} 1187 1188static int 1189psycho_release_resource(device_t bus, device_t child, int type, int rid, 1190 struct resource *r) 1191{ 1192 int error; 1193 1194 if (type == SYS_RES_IRQ) 1195 return (bus_release_resource(bus, type, rid, r)); 1196 if (rman_get_flags(r) & RF_ACTIVE) { 1197 error = bus_deactivate_resource(child, type, rid, r); 1198 if (error) 1199 return error; 1200 } 1201 return (rman_release_resource(r)); 1202} 1203 1204static int 1205psycho_intr_pending(device_t dev, int intr) 1206{ 1207 struct psycho_softc *sc; 1208 u_long diag; 1209 1210 sc = (struct psycho_softc *)device_get_softc(dev); 1211 if (!psycho_find_intrmap(sc, intr, NULL, NULL, &diag)) { 1212 printf("psycho_intr_pending: mapping not found for %d\n", intr); 1213 return (0); 1214 } 1215 return (diag != 0); 1216} 1217 1218static bus_space_handle_t 1219psycho_get_bus_handle(device_t dev, enum sbbt_id id, 1220 bus_space_handle_t childhdl, bus_space_tag_t *tag) 1221{ 1222 struct psycho_softc *sc; 1223 1224 sc = (struct psycho_softc *)device_get_softc(dev); 1225 switch(id) { 1226 case SBBT_IO: 1227 *tag = sc->sc_iot; 1228 return (sc->sc_bh[PCI_CS_IO] + childhdl); 1229 case SBBT_MEM: 1230 *tag = sc->sc_memt; 1231 return (sc->sc_bh[PCI_CS_MEM32] + childhdl); 1232 default: 1233 panic("psycho_get_bus_handle: illegal space\n"); 1234 } 1235} 1236 1237/* 1238 * below here is bus space and bus dma support 1239 */ 1240static bus_space_tag_t 1241psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1242{ 1243 bus_space_tag_t bt; 1244 1245 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1246 M_NOWAIT | M_ZERO); 1247 if (bt == NULL) 1248 panic("psycho_alloc_bus_tag: out of memory"); 1249 1250 bzero(bt, sizeof *bt); 1251 bt->cookie = sc; 1252 bt->parent = sc->sc_bustag; 1253 bt->type = type; 1254 return (bt); 1255} 1256 1257/* 1258 * hooks into the iommu dvma calls. 1259 */ 1260static int 1261psycho_dmamem_alloc(bus_dma_tag_t dmat, void **vaddr, int flags, bus_dmamap_t *mapp) 1262{ 1263 struct psycho_softc *sc; 1264 1265 sc = (struct psycho_softc *)dmat->cookie; 1266 return (iommu_dvmamem_alloc(dmat, sc->sc_is, vaddr, flags, mapp)); 1267} 1268 1269static void 1270psycho_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map) 1271{ 1272 struct psycho_softc *sc; 1273 1274 sc = (struct psycho_softc *)dmat->cookie; 1275 iommu_dvmamem_free(dmat, sc->sc_is, vaddr, map); 1276} 1277 1278static int 1279psycho_dmamap_create(bus_dma_tag_t dmat, int flags, bus_dmamap_t *mapp) 1280{ 1281 struct psycho_softc *sc; 1282 1283 sc = (struct psycho_softc *)dmat->cookie; 1284 return (iommu_dvmamap_create(dmat, sc->sc_is, flags, mapp)); 1285 1286} 1287 1288static int 1289psycho_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map) 1290{ 1291 struct psycho_softc *sc; 1292 1293 sc = (struct psycho_softc *)dmat->cookie; 1294 return (iommu_dvmamap_destroy(dmat, sc->sc_is, map)); 1295} 1296 1297static int 1298psycho_dmamap_load(bus_dma_tag_t dmat, bus_dmamap_t map, void *buf, 1299 bus_size_t buflen, bus_dmamap_callback_t *callback, void *callback_arg, 1300 int flags) 1301{ 1302 struct psycho_softc *sc; 1303 1304 sc = (struct psycho_softc *)dmat->cookie; 1305 return (iommu_dvmamap_load(dmat, sc->sc_is, map, buf, buflen, callback, 1306 callback_arg, flags)); 1307} 1308 1309static void 1310psycho_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t map) 1311{ 1312 struct psycho_softc *sc; 1313 1314 sc = (struct psycho_softc *)dmat->cookie; 1315 iommu_dvmamap_unload(dmat, sc->sc_is, map); 1316} 1317 1318static void 1319psycho_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, 1320 bus_dmasync_op_t op) 1321{ 1322 struct psycho_softc *sc; 1323 1324 sc = (struct psycho_softc *)dmat->cookie; 1325 iommu_dvmamap_sync(dmat, sc->sc_is, map, op); 1326} 1327