psycho.c revision 88371
1/* 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * All rights reserved. 4 * Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: psycho.c,v 1.35 2001/09/10 16:17:06 eeh Exp 30 * 31 * $FreeBSD: head/sys/sparc64/pci/psycho.c 88371 2001-12-21 21:35:47Z tmm $ 32 */ 33 34/* 35 * Support for `psycho' and `psycho+' UPA to PCI bridge and 36 * UltraSPARC IIi and IIe `sabre' PCI controllers. 37 */ 38 39#include "opt_psycho.h" 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/kernel.h> 45#include <sys/malloc.h> 46 47#include <ofw/openfirm.h> 48#include <ofw/ofw_pci.h> 49 50#include <machine/bus.h> 51#include <machine/cache.h> 52#include <machine/iommureg.h> 53#include <machine/bus_common.h> 54#include <machine/frame.h> 55#include <machine/intr_machdep.h> 56#include <machine/nexusvar.h> 57#include <machine/ofw_upa.h> 58#include <machine/resource.h> 59 60#include <sys/rman.h> 61 62#include <machine/iommuvar.h> 63 64#include <pci/pcivar.h> 65#include <pci/pcireg.h> 66 67#include <sparc64/pci/ofw_pci.h> 68#include <sparc64/pci/psychoreg.h> 69#include <sparc64/pci/psychovar.h> 70 71#include "pcib_if.h" 72#include "sparcbus_if.h" 73 74static void psycho_get_ranges(phandle_t, struct upa_ranges **, int *); 75static void psycho_set_intr(struct psycho_softc *, int, device_t, u_long *, 76 int, driver_intr_t); 77static int psycho_find_intrmap(struct psycho_softc *, int, u_long **, 78 u_long **, u_long *); 79static void psycho_intr_stub(void *); 80#ifdef PSYCHO_STRAY 81static void psycho_intr_stray(void *); 82#endif 83static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 84 85 86/* Interrupt handlers */ 87static void psycho_ue(void *); 88static void psycho_ce(void *); 89static void psycho_bus_a(void *); 90static void psycho_bus_b(void *); 91static void psycho_powerfail(void *); 92#ifdef PSYCHO_MAP_WAKEUP 93static void psycho_wakeup(void *); 94#endif 95 96/* IOMMU support */ 97static void psycho_iommu_init(struct psycho_softc *, int); 98 99/* 100 * bus space and bus dma support for UltraSPARC `psycho'. note that most 101 * of the bus dma support is provided by the iommu dvma controller. 102 */ 103static int psycho_dmamem_alloc(bus_dma_tag_t, void **, int, bus_dmamap_t *); 104static void psycho_dmamem_free(bus_dma_tag_t, void *, bus_dmamap_t); 105static int psycho_dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *, bus_size_t, 106 bus_dmamap_callback_t *, void *, int); 107static void psycho_dmamap_unload(bus_dma_tag_t, bus_dmamap_t); 108static void psycho_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_dmasync_op_t); 109 110/* 111 * autoconfiguration 112 */ 113static int psycho_probe(device_t); 114static int psycho_attach(device_t); 115static int psycho_read_ivar(device_t, device_t, int, u_long *); 116static int psycho_setup_intr(device_t, device_t, struct resource *, int, 117 driver_intr_t *, void *, void **); 118static int psycho_teardown_intr(device_t, device_t, struct resource *, void *); 119static struct resource *psycho_alloc_resource(device_t, device_t, int, int *, 120 u_long, u_long, u_long, u_int); 121static int psycho_activate_resource(device_t, device_t, int, int, 122 struct resource *); 123static int psycho_deactivate_resource(device_t, device_t, int, int, 124 struct resource *); 125static int psycho_release_resource(device_t, device_t, int, int, 126 struct resource *); 127static int psycho_maxslots(device_t); 128static u_int32_t psycho_read_config(device_t, u_int, u_int, u_int, u_int, int); 129static void psycho_write_config(device_t, u_int, u_int, u_int, u_int, u_int32_t, 130 int); 131static int psycho_route_interrupt(device_t, device_t, int); 132static int psycho_intr_pending(device_t, int); 133static bus_space_handle_t psycho_get_bus_handle(device_t dev, enum sbbt_id id, 134 bus_space_handle_t childhdl, bus_space_tag_t *tag); 135 136static device_method_t psycho_methods[] = { 137 /* Device interface */ 138 DEVMETHOD(device_probe, psycho_probe), 139 DEVMETHOD(device_attach, psycho_attach), 140 141 /* Bus interface */ 142 DEVMETHOD(bus_print_child, bus_generic_print_child), 143 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 144 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 145 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 146 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 147 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 148 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 149 DEVMETHOD(bus_release_resource, psycho_release_resource), 150 151 /* pcib interface */ 152 DEVMETHOD(pcib_maxslots, psycho_maxslots), 153 DEVMETHOD(pcib_read_config, psycho_read_config), 154 DEVMETHOD(pcib_write_config, psycho_write_config), 155 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 156 157 /* sparcbus interface */ 158 DEVMETHOD(sparcbus_intr_pending, psycho_intr_pending), 159 DEVMETHOD(sparcbus_get_bus_handle, psycho_get_bus_handle), 160 161 { 0, 0 } 162}; 163 164static driver_t psycho_driver = { 165 "pcib", 166 psycho_methods, 167 sizeof(struct psycho_softc), 168}; 169 170static devclass_t psycho_devclass; 171 172DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 173 174static int psycho_ndevs; 175static struct psycho_softc *psycho_softcs[4]; 176 177struct psycho_clr { 178 u_long *pci_clr; /* clear register */ 179 driver_intr_t *pci_handler; /* handler to call */ 180 void *pci_arg; /* argument for the handler */ 181 void *pci_cookie; /* interrupt cookie of parent bus */ 182}; 183 184/* 185 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 186 * single PCI bus and does not have a streaming buffer. It often has an APB 187 * (advanced PCI bridge) connected to it, which was designed specifically for 188 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 189 * appears as two "simba"'s underneath the sabre. 190 * 191 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 192 * and manages two PCI buses. "psycho" has two 64-bit 33MHz buses, while 193 * "psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 194 * will usually find a "psycho+" since I don't think the original "psycho" 195 * ever shipped, and if it did it would be in the U30. 196 * 197 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 198 * both part of the same IC, they only have a single register space. As such, 199 * they need to be configured together, even though the autoconfiguration will 200 * attach them separately. 201 * 202 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 203 * as pci1 and pci2, although they have been implemented with other PCI bus 204 * numbers on some machines. 205 * 206 * On UltraII machines, there can be any number of "psycho+" ICs, each 207 * providing two PCI buses. 208 * 209 * 210 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 211 * the values of the following interrupts in this order: 212 * 213 * PCI Bus Error (30) 214 * DMA UE (2e) 215 * DMA CE (2f) 216 * Power Fail (25) 217 * 218 * We really should attach handlers for each. 219 */ 220#define OFW_PCI_TYPE "pci" 221#define OFW_SABRE_MODEL "SUNW,sabre" 222#define OFW_SABRE_COMPAT "pci108e,a001" 223#define OFW_SIMBA_MODEL "SUNW,simba" 224#define OFW_PSYCHO_MODEL "SUNW,psycho" 225 226static int 227psycho_probe(device_t dev) 228{ 229 phandle_t node; 230 char *dtype, *model; 231 static char compat[32]; 232 233 node = nexus_get_node(dev); 234 if (OF_getprop(node, "compatible", compat, sizeof(compat)) == -1) 235 compat[0] = '\0'; 236 237 dtype = nexus_get_device_type(dev); 238 model = nexus_get_model(dev); 239 /* match on a type of "pci" and a sabre or a psycho */ 240 if (nexus_get_reg(dev) != NULL && dtype != NULL && 241 strcmp(dtype, OFW_PCI_TYPE) == 0 && 242 ((model != NULL && (strcmp(model, OFW_SABRE_MODEL) == 0 || 243 strcmp(model, OFW_PSYCHO_MODEL) == 0)) || 244 strcmp(compat, OFW_SABRE_COMPAT) == 0)) { 245 device_set_desc(dev, "U2P UPA-PCI bridge"); 246 return (0); 247 } 248 249 return (ENXIO); 250} 251 252/* 253 * SUNW,psycho initialisation .. 254 * - find the per-psycho registers 255 * - figure out the IGN. 256 * - find our partner psycho 257 * - configure ourselves 258 * - bus range, bus, 259 * - interrupt map, 260 * - setup the chipsets. 261 * - if we're the first of the pair, initialise the IOMMU, otherwise 262 * just copy it's tags and addresses. 263 */ 264static int 265psycho_attach(device_t dev) 266{ 267 struct psycho_softc *sc; 268 struct psycho_softc *osc = NULL; 269 struct psycho_softc *asc; 270 struct ofw_nexus_reg *reg; 271 char compat[32]; 272 char *model; 273 phandle_t node; 274 u_int64_t csr; 275 u_long pci_ctl; 276 int psycho_br[2]; 277 int n, i, nreg; 278#if defined(PSYCHO_DEBUG) || defined(PSYCHO_STRAY) 279 u_long *map, *clr; 280#endif 281 282 bootverbose = 1; 283 node = nexus_get_node(dev); 284 sc = device_get_softc(dev); 285 if (OF_getprop(node, "compatible", compat, sizeof(compat)) == -1) 286 compat[0] = '\0'; 287 288 sc->sc_node = node; 289 sc->sc_dev = dev; 290 sc->sc_bustag = nexus_get_bustag(dev); 291 sc->sc_dmatag = nexus_get_dmatag(dev); 292 293 /* 294 * call the model-specific initialisation routine. 295 */ 296 model = nexus_get_model(dev); 297 if ((model != NULL && 298 strcmp(model, OFW_SABRE_MODEL) == 0) || 299 strcmp(compat, OFW_SABRE_COMPAT) == 0) { 300 sc->sc_mode = PSYCHO_MODE_SABRE; 301 if (model == NULL) 302 model = "sabre"; 303 } else if (model != NULL && 304 strcmp(model, OFW_PSYCHO_MODEL) == 0) 305 sc->sc_mode = PSYCHO_MODE_PSYCHO; 306 else 307 panic("psycho_attach: unknown model!"); 308 309 /* 310 * The psycho gets three register banks: 311 * (0) per-PBM configuration and status registers 312 * (1) per-PBM PCI configuration space, containing only the 313 * PBM 256-byte PCI header 314 * (2) the shared psycho configuration registers (struct psychoreg) 315 * 316 * XXX use the prom address for the psycho registers? we do so far. 317 */ 318 reg = nexus_get_reg(dev); 319 nreg = nexus_get_nreg(dev); 320 /* Register layouts are different. stuupid. */ 321 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 322 sc->sc_basepaddr = (vm_offset_t)reg[2].or_paddr; 323 324 if (nreg <= 2) { 325 panic("psycho_attach: %d not enough registers", nreg); 326 } 327 if (sparc64_bus_mem_map(UPA_BUS_SPACE, reg[2].or_paddr, 328 reg[2].or_len, 0, NULL, (void **)&sc->sc_regs)) 329 panic("psycho_attach: cannot map regs"); 330 pci_ctl = reg[0].or_paddr; 331 } else { 332 sc->sc_basepaddr = (vm_offset_t)reg[0].or_paddr; 333 334 if (nreg <= 0) { 335 panic("psycho_attach: %d not enough registers", nreg); 336 } 337 if (sparc64_bus_mem_map(UPA_BUS_SPACE, reg[0].or_paddr, 338 reg[0].or_len, 0, NULL, (void **)&sc->sc_regs)) 339 panic("psycho_attach: cannot map regs"); 340 pci_ctl = reg[0].or_paddr + 341 offsetof(struct psychoreg, psy_pcictl[0]); 342 } 343 344 csr = sc->sc_regs->psy_csr; 345 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 346 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 347 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 348 349 device_printf(dev, "%s: impl %d, version %d: ign %x ", 350 model, PSYCHO_GCSR_IMPL(csr), PSYCHO_GCSR_VERS(csr), 351 sc->sc_ign); 352 353 /* 354 * Match other psycho's that are already configured against 355 * the base physical address. This will be the same for a 356 * pair of devices that share register space. 357 */ 358 for (n = 0; n < psycho_ndevs && n < sizeof(psycho_softcs) / 359 sizeof(psycho_softcs[0]); n++) { 360 asc = (struct psycho_softc *)psycho_softcs[n]; 361 362 if (asc == NULL || asc == sc) 363 /* This entry is not there or it is me */ 364 continue; 365 366 if (asc->sc_basepaddr != sc->sc_basepaddr) 367 /* This is an unrelated psycho */ 368 continue; 369 370 /* Found partner */ 371 osc = asc; 372 break; 373 } 374 375 /* 376 * Setup the PCI control register 377 */ 378 csr = bus_space_read_8(sc->sc_bustag, 379 (bus_space_handle_t)pci_ctl, offsetof(struct pci_ctl, pci_csr)); 380 csr |= PCICTL_MRLM | 381 PCICTL_ARB_PARK | 382 PCICTL_ERRINTEN | 383 PCICTL_4ENABLE; 384 csr &= ~(PCICTL_SERR | 385 PCICTL_CPU_PRIO | 386 PCICTL_ARB_PRIO | 387 PCICTL_RTRYWAIT); 388 bus_space_write_8(sc->sc_bustag, 389 (bus_space_handle_t)pci_ctl, offsetof(struct pci_ctl, pci_csr), 390 csr); 391 392 /* grab the psycho ranges */ 393 psycho_get_ranges(sc->sc_node, &sc->sc_range, &sc->sc_nrange); 394 395 /* get the bus-range for the psycho */ 396 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br)); 397 if (n == -1) 398 panic("could not get psycho bus-range"); 399 if (n != sizeof(psycho_br)) 400 panic("broken psycho bus-range (%d)", n); 401 402 printf("bus range %u to %u; PCI bus %d\n", psycho_br[0], psycho_br[1], 403 psycho_br[0]); 404 405 sc->sc_busno = psycho_br[0]; 406 407 /* Initialize memory and i/o rmans */ 408 sc->sc_io_rman.rm_type = RMAN_ARRAY; 409 sc->sc_io_rman.rm_descr = "Psycho PCI I/O Ports"; 410 if (rman_init(&sc->sc_io_rman) != 0 || 411 rman_manage_region(&sc->sc_io_rman, 0, PSYCHO_IO_SIZE) != 0) 412 panic("psycho_probe: failed to set up i/o rman"); 413 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 414 sc->sc_mem_rman.rm_descr = "Psycho PCI Memory"; 415 if (rman_init(&sc->sc_mem_rman) != 0 || 416 rman_manage_region(&sc->sc_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 417 panic("psycho_probe: failed to set up memory rman"); 418 /* 419 * Find the addresses of the various bus spaces. 420 * There should not be multiple ones of one kind. 421 * The physical start addresses of the ranges are the configuration, 422 * memory and IO handles. 423 */ 424 for (n = 0; n < sc->sc_nrange; n++) { 425 i = UPA_RANGE_CS(&sc->sc_range[n]); 426 if (sc->sc_bh[i] != 0) 427 panic("psycho_attach: duplicate range for space %d", i); 428 sc->sc_bh[i] = UPA_RANGE_PHYS(&sc->sc_range[n]); 429 } 430 /* 431 * Check that all needed handles are present. The PCI_CS_MEM64 one is 432 * not currently used. 433 */ 434 for (n = 0; n < 3; n++) { 435 if (sc->sc_bh[n] == 0) 436 panic("psycho_attach: range %d missing", n); 437 } 438 439 /* allocate our tags */ 440 sc->sc_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 441 sc->sc_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 442 sc->sc_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 443 if (bus_dma_tag_create(sc->sc_dmatag, 8, 1, 0, 0x3ffffffff, NULL, NULL, 444 0x3ffffffff, 0xff, 0xffffffff, 0, &sc->sc_dmat) != 0) 445 panic("bus_dma_tag_create failed"); 446 /* Customize the tag */ 447 sc->sc_dmat->cookie = sc; 448 sc->sc_dmat->dmamem_alloc = psycho_dmamem_alloc; 449 sc->sc_dmat->dmamem_free = psycho_dmamem_free; 450 sc->sc_dmat->dmamap_load = psycho_dmamap_load; 451 sc->sc_dmat->dmamap_unload = psycho_dmamap_unload; 452 sc->sc_dmat->dmamap_sync = psycho_dmamap_sync; 453 /* XXX: register as root dma tag (kluge). */ 454 sparc64_root_dma_tag = sc->sc_dmat; 455 456 if ((sc->sc_nintrmap = OF_getprop_alloc(sc->sc_node, "interrupt-map", 457 sizeof(*sc->sc_intrmap), (void **)&sc->sc_intrmap)) == -1 || 458 OF_getprop(sc->sc_node, "interrupt-map-mask", &sc->sc_intrmapmsk, 459 sizeof(sc->sc_intrmapmsk)) == -1) { 460 if (sc->sc_intrmap != NULL) { 461 free(sc->sc_intrmap, M_OFWPROP); 462 sc->sc_intrmap = NULL; 463 } 464 } 465 466 /* Register the softc, this is needed for paired psychos. */ 467 if (psycho_ndevs < sizeof(psycho_softcs) / sizeof(psycho_softcs[0])) 468 psycho_softcs[psycho_ndevs] = sc; 469 else 470 device_printf(dev, "XXX: bump the number of psycho_softcs"); 471 psycho_ndevs++; 472 /* 473 * And finally, if we're a sabre or the first of a pair of psycho's to 474 * arrive here, start up the IOMMU and get a config space tag. 475 */ 476 if (osc == NULL) { 477 /* 478 * Establish handlers for interesting interrupts.... 479 * 480 * XXX We need to remember these and remove this to support 481 * hotplug on the UPA/FHC bus. 482 * 483 * XXX Not all controllers have these, but installing them 484 * is better than trying to sort through this mess. 485 */ 486 psycho_set_intr(sc, 0, dev, &sc->sc_regs->ue_int_map, 487 INTR_TYPE_MISC | INTR_FAST, psycho_ue); 488 psycho_set_intr(sc, 1, dev, &sc->sc_regs->ce_int_map, 489 INTR_TYPE_MISC, psycho_ce); 490 psycho_set_intr(sc, 2, dev, 491 &sc->sc_regs->pciaerr_int_map, INTR_TYPE_MISC | INTR_FAST, 492 psycho_bus_a); 493 psycho_set_intr(sc, 3, dev, 494 &sc->sc_regs->pciberr_int_map, INTR_TYPE_MISC | INTR_FAST, 495 psycho_bus_b); 496 psycho_set_intr(sc, 4, dev, &sc->sc_regs->power_int_map, 497 INTR_TYPE_MISC | INTR_FAST, psycho_powerfail); 498#ifdef PSYCHO_MAP_WAKEUP 499 /* 500 * On some models, this is mapped to the same interrupt as 501 * pciberr by default, so leave it alone for now since 502 * psycho_wakeup() doesn't do anything useful anyway. 503 */ 504 psycho_set_intr(sc, 5, dev, &sc->sc_regs->pwrmgt_int_map, 505 INTR_TYPE_MISC, psycho_wakeup); 506#endif /* PSYCHO_MAP_WAKEUP */ 507 508 /* 509 * Setup IOMMU and PCI configuration if we're the first 510 * of a pair of psycho's to arrive here. 511 * 512 * We should calculate a TSB size based on amount of RAM 513 * and number of bus controllers and number an type of 514 * child devices. 515 * 516 * For the moment, 32KB should be more than enough. 517 */ 518 psycho_iommu_init(sc, 2); 519 } else { 520 /* Just copy IOMMU state, config tag and address */ 521 sc->sc_is = osc->sc_is; 522 } 523 524 /* 525 * Enable all interrupts, clear all interrupt states, and install an 526 * interrupt handler for OBIO interrupts, which can be ISA ones 527 * (to frob the interrupt clear registers). 528 * This aids the debugging of interrupt routing problems, and is needed 529 * for isa drivers that use isa_irq_pending (otherwise the registers 530 * will never be cleared). 531 */ 532#if defined(PSYCHO_DEBUG) || defined(PSYCHO_STRAY) 533 for (map = &sc->sc_regs->pcia0_int_map, 534 clr = &sc->sc_regs->pcia0_int_clr[0], n = 0; 535 map <= &sc->sc_regs->pcib3_int_map; map++, clr += 4, n++) { 536#ifdef PSYCHO_DEBUG 537 device_printf(dev, "intr map (pci) %d: %lx\n", n, *map); 538#endif 539 *map &= ~INTMAP_V; 540 membar(StoreStore); 541 for (i = 0; i < 4; i++) 542 clr[i] = 0; 543 membar(StoreStore); 544 *map |= INTMAP_V; 545 } 546 for (map = &sc->sc_regs->scsi_int_map, n = 0, 547 clr = &sc->sc_regs->scsi_int_clr, n = 0; 548 map <= &sc->sc_regs->ffb1_int_map; map++, clr++, n++) { 549#ifdef PSYCHO_DEBUG 550 device_printf(dev, "intr map (obio) %d: %lx, clr: %p\n", n, 551 *map, clr); 552#endif 553 *map &= ~INTMAP_V; 554 membar(StoreStore); 555 *clr = 0; 556#ifdef PSYCHO_STRAY 557 /* 558 * This can cause interrupt storms, and is therefore disabled 559 * by default. 560 * XXX: use intr_setup() to not confuse higher level code 561 */ 562 if (INTVEC(*map) != 0x7e6 && INTVEC(*map) != 0x7e7 && 563 INTVEC(*map) != 0) 564 intr_setup(PIL_LOW, intr_dequeue, INTVEC(*map), psycho_intr_stray, 565 (void *)clr); 566#endif 567 membar(StoreStore); 568 *map |= INTMAP_V; 569 } 570#endif 571 572 /* 573 * Initialize the interrupt registers of all devices hanging from 574 * the host bridge directly or indirectly via PCI-PCI bridges. 575 * The MI code (and the PCI spec) assume that this is done during 576 * system initialization, however the firmware does not do this 577 * at least on some models, and we probably shouldn't trust that 578 * the firmware uses the same model as this driver if it does. 579 */ 580 ofw_pci_init_intr(dev, sc->sc_node, sc->sc_intrmap, sc->sc_nintrmap, 581 &sc->sc_intrmapmsk); 582 583 device_add_child(dev, "pci", device_get_unit(dev)); 584 return (bus_generic_attach(dev)); 585} 586 587static void 588psycho_set_intr(struct psycho_softc *sc, int index, 589 device_t dev, u_long *map, int iflags, driver_intr_t handler) 590{ 591 int rid; 592 593 sc->sc_irq[index] = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 594 INTVEC(*map), INTVEC(*map), 1, RF_ACTIVE); 595 if (sc->sc_irq[index] == NULL) 596 panic("psycho_set_intr: failed to get interupt"); 597 bus_setup_intr(dev, sc->sc_irq[index], INTR_TYPE_MISC | iflags, 598 handler, sc, &sc->sc_ihand[index]); 599 *map |= INTMAP_V; 600} 601 602static int 603psycho_find_intrmap(struct psycho_softc *sc, int ino, u_long **intrmapptr, 604 u_long **intrclrptr, u_long *intrdiagptr) 605{ 606 u_long *intrmap, *intrclr, diag; 607 int found; 608 609 found = 0; 610 /* Hunt thru obio first */ 611 diag = sc->sc_regs->obio_int_diag; 612 for (intrmap = &sc->sc_regs->scsi_int_map, 613 intrclr = &sc->sc_regs->scsi_int_clr; 614 intrmap <= &sc->sc_regs->ffb1_int_map; 615 intrmap++, intrclr++, diag >>= 2) { 616 if (INTINO(*intrmap) == ino) { 617 diag &= 2; 618 found = 1; 619 break; 620 } 621 } 622 623 if (!found) { 624 diag = sc->sc_regs->pci_int_diag; 625 /* Now do PCI interrupts */ 626 for (intrmap = &sc->sc_regs->pcia0_int_map, 627 intrclr = &sc->sc_regs->pcia0_int_clr[0]; 628 intrmap <= &sc->sc_regs->pcib3_int_map; 629 intrmap++, intrclr += 4, diag >>= 8) { 630 if (((*intrmap ^ ino) & 0x3c) == 0) { 631 intrclr += ino & 3; 632 diag = (diag >> ((ino & 3) * 2)) & 2; 633 found = 1; 634 break; 635 } 636 } 637 } 638 if (intrmapptr != NULL) 639 *intrmapptr = intrmap; 640 if (intrclrptr != NULL) 641 *intrclrptr = intrclr; 642 if (intrdiagptr != NULL) 643 *intrdiagptr = diag; 644 return (found); 645} 646 647/* grovel the OBP for various psycho properties */ 648static void 649psycho_get_ranges(phandle_t node, struct upa_ranges **rp, int *np) 650{ 651 652 *np = OF_getprop_alloc(node, "ranges", sizeof(**rp), (void **)rp); 653 if (*np == -1) 654 panic("could not get psycho ranges"); 655} 656 657/* 658 * Interrupt handlers. 659 */ 660static void 661psycho_ue(void *arg) 662{ 663 struct psycho_softc *sc = (struct psycho_softc *)arg; 664 struct psychoreg *regs = sc->sc_regs; 665 666 sc->sc_regs->ue_int_clr = 0; 667 /* It's uncorrectable. Dump the regs and panic. */ 668 panic("%s: uncorrectable DMA error AFAR %llx AFSR %llx\n", 669 device_get_name(sc->sc_dev), 670 (long long)regs->psy_ue_afar, (long long)regs->psy_ue_afsr); 671} 672 673static void 674psycho_ce(void *arg) 675{ 676 struct psycho_softc *sc = (struct psycho_softc *)arg; 677 struct psychoreg *regs = sc->sc_regs; 678 679 sc->sc_regs->ce_int_clr = 0; 680 /* It's correctable. Dump the regs and continue. */ 681 printf("%s: correctable DMA error AFAR %llx AFSR %llx\n", 682 device_get_name(sc->sc_dev), 683 (long long)regs->psy_ce_afar, (long long)regs->psy_ce_afsr); 684} 685 686static void 687psycho_bus_a(void *arg) 688{ 689 struct psycho_softc *sc = (struct psycho_softc *)arg; 690 struct psychoreg *regs = sc->sc_regs; 691 692 sc->sc_regs->pciaerr_int_clr = 0; 693 /* It's uncorrectable. Dump the regs and panic. */ 694 panic("%s: PCI bus A error AFAR %lx AFSR %lx\n", 695 device_get_name(sc->sc_dev), 696 regs->psy_pcictl[0].pci_afar, regs->psy_pcictl[0].pci_afsr); 697} 698 699static void 700psycho_bus_b(void *arg) 701{ 702 struct psycho_softc *sc = (struct psycho_softc *)arg; 703 struct psychoreg *regs = sc->sc_regs; 704 705 sc->sc_regs->pciberr_int_clr = 0; 706 /* It's uncorrectable. Dump the regs and panic. */ 707 panic("%s: PCI bus B error AFAR %lx AFSR %lx\n", 708 device_get_name(sc->sc_dev), 709 regs->psy_pcictl[1].pci_afar, regs->psy_pcictl[1].pci_afsr); 710} 711 712static void 713psycho_powerfail(void *arg) 714{ 715 struct psycho_softc *sc = (struct psycho_softc *)arg; 716 717 sc->sc_regs->power_int_clr = 0; 718 /* We lost power. Try to shut down NOW. */ 719 printf("Power Failure Detected: Shutting down NOW.\n"); 720 shutdown_nice(0); 721} 722 723#ifdef PSYCHO_MAP_WAKEUP 724static void 725psycho_wakeup(void *arg) 726{ 727 struct psycho_softc *sc = (struct psycho_softc *)arg; 728 729 sc->sc_regs->pwrmgt_int_clr = 0; 730 /* Gee, we don't really have a framework to deal with this properly. */ 731 printf("%s: power management wakeup\n", device_get_name(sc->sc_dev)); 732} 733#endif /* PSYCHO_MAP_WAKEUP */ 734 735/* initialise the IOMMU... */ 736void 737psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 738{ 739 char *name; 740 struct iommu_state *is; 741 u_int32_t iobase = -1; 742 int *vdma = NULL; 743 int nitem; 744 745 is = malloc(sizeof(struct iommu_state), M_DEVBUF, M_NOWAIT); 746 if (is == NULL) 747 panic("psycho_iommu_init: malloc failed"); 748 749 sc->sc_is = is; 750 751 /* punch in our copies */ 752 is->is_bustag = sc->sc_bustag; 753 is->is_iommu = &sc->sc_regs->psy_iommu; 754 is->is_dtag = &sc->sc_regs->tlb_tag_diag[0]; 755 is->is_ddram = &sc->sc_regs->tlb_data_diag[0]; 756 is->is_dqueue = &sc->sc_regs->iommu_queue_diag[0]; 757 is->is_dva = &sc->sc_regs->iommu_svadiag; 758 is->is_dtcmp = &sc->sc_regs->iommu_tlb_comp_diag; 759 760 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 761 is->is_sb = 0; 762 else 763 is->is_sb = &sc->sc_regs->psy_iommu_strbuf; 764 765 /* 766 * Separate the men from the boys. Get the `virtual-dma' 767 * property for sabre and use that to make sure the damn 768 * iommu works. 769 * 770 * We could query the `#virtual-dma-size-cells' and 771 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 772 */ 773 nitem = OF_getprop_alloc(sc->sc_node, "virtual-dma", sizeof(vdma), 774 (void **)&vdma); 775 if (nitem > 0) { 776 iobase = vdma[0]; 777 tsbsize = ffs(vdma[1]); 778 if (tsbsize < 25 || tsbsize > 31 || 779 (vdma[1] & ~(1 << (tsbsize - 1))) != 0) { 780 printf("bogus tsb size %x, using 7\n", vdma[1]); 781 tsbsize = 31; 782 } 783 tsbsize -= 24; 784 free(vdma, M_OFWPROP); 785 } 786 787 /* give us a nice name.. */ 788 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 789 if (name == 0) 790 panic("couldn't malloc iommu name"); 791 snprintf(name, 32, "%s dvma", device_get_name(sc->sc_dev)); 792 793 iommu_init(name, is, tsbsize, iobase); 794} 795 796static int 797psycho_maxslots(device_t dev) 798{ 799 800 /* 801 * XXX: is this correct? At any rate, a number that is too high 802 * shouldn't do any harm, if only because of the way things are 803 * handled in psycho_read_config. 804 */ 805 return (31); 806} 807 808/* 809 * Keep a table of quirky PCI devices that need fixups before the MI PCI code 810 * creates the resource lists. This needs to be moved around once other bus 811 * drivers are added. Moving it to the MI code should maybe be reconsidered 812 * if one of these devices appear in non-sparc64 boxen. It's likely that not 813 * all BIOSes/firmwares can deal with them. 814 */ 815struct psycho_dquirk { 816 u_int32_t dq_devid; 817 int dq_quirk; 818}; 819 820/* Quirk types. May be or'ed together. */ 821#define DQT_BAD_INTPIN 1 /* Intpin reg 0, but intpin used */ 822 823static struct psycho_dquirk dquirks[] = { 824 { 0x1001108e, DQT_BAD_INTPIN }, /* Sun HME (PCIO func. 1) */ 825 { 0x1101108e, DQT_BAD_INTPIN }, /* Sun GEM (PCIO2 func. 1) */ 826}; 827 828#define NDQUIRKS (sizeof(dquirks) / sizeof(dquirks[0])) 829 830static u_int32_t 831psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 832 int width) 833{ 834 struct psycho_softc *sc; 835 bus_space_handle_t bh; 836 u_long offset = 0; 837 u_int32_t r, devid; 838 int i; 839 840 /* 841 * The psycho bridge does not tolerate accesses to unconfigured PCI 842 * devices' or function's config space, so look up the device in the 843 * firmware device tree first, and if it is not present, return a value 844 * that will make the detection code think that there is no device here. 845 * This is ugly... 846 */ 847 if (reg == 0 && ofw_pci_find_node(bus, slot, func) == 0) 848 return (0xffffffff); 849 sc = (struct psycho_softc *)device_get_softc(dev); 850 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 851 bh = sc->sc_bh[PCI_CS_CONFIG]; 852 switch (width) { 853 case 1: 854 r = bus_space_read_1(sc->sc_cfgt, bh, offset); 855 break; 856 case 2: 857 r = bus_space_read_2(sc->sc_cfgt, bh, offset); 858 break; 859 case 4: 860 r = bus_space_read_4(sc->sc_cfgt, bh, offset); 861 break; 862 default: 863 panic("psycho_read_config: bad width"); 864 } 865 if (reg == PCIR_INTPIN && r == 0) { 866 /* Check for DQT_BAD_INTPIN quirk. */ 867 devid = psycho_read_config(dev, bus, slot, func, 868 PCIR_DEVVENDOR, 4); 869 for (i = 0; i < NDQUIRKS; i++) { 870 if (dquirks[i].dq_devid == devid) { 871 /* 872 * Need to set the intpin to a value != 0 so 873 * that the MI code will think that this device 874 * has an interrupt. 875 * Just use 1 (intpin a) for now. This is, of 876 * course, bogus, but since interrupts are 877 * routed in advance, this does not really 878 * matter. 879 */ 880 if ((dquirks[i].dq_quirk & DQT_BAD_INTPIN) != 0) 881 r = 1; 882 break; 883 } 884 } 885 } 886 return (r); 887} 888 889static void 890psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, 891 u_int reg, u_int32_t val, int width) 892{ 893 struct psycho_softc *sc; 894 bus_space_handle_t bh; 895 u_long offset = 0; 896 897 sc = (struct psycho_softc *)device_get_softc(dev); 898 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 899 bh = sc->sc_bh[PCI_CS_CONFIG]; 900 switch (width) { 901 case 1: 902 bus_space_write_1(sc->sc_cfgt, bh, offset, val); 903 break; 904 case 2: 905 bus_space_write_2(sc->sc_cfgt, bh, offset, val); 906 break; 907 case 4: 908 bus_space_write_4(sc->sc_cfgt, bh, offset, val); 909 break; 910 default: 911 panic("psycho_write_config: bad width"); 912 } 913} 914 915static int 916psycho_route_interrupt(device_t bus, device_t dev, int pin) 917{ 918 919 /* 920 * Since we preinitialize all interrupt line registers, this should not 921 * happen for any built-in device. 922 * Devices on bridges that route interrupts cannot work now - the 923 * interrupt pin mappings are not known from the firmware... 924 */ 925 panic("psycho_route_interrupt"); 926} 927 928static int 929psycho_read_ivar(device_t dev, device_t child, int which, u_long *result) 930{ 931 struct psycho_softc *sc; 932 933 sc = (struct psycho_softc *)device_get_softc(dev); 934 switch (which) { 935 case PCIB_IVAR_BUS: 936 *result = sc->sc_busno; 937 return (0); 938 } 939 return (ENOENT); 940} 941 942/* Write to the correct clr register, and call the actual handler. */ 943static void 944psycho_intr_stub(void *arg) 945{ 946 struct psycho_clr *pc; 947 948 pc = (struct psycho_clr *)arg; 949 *pc->pci_clr = 0; 950 pc->pci_handler(pc->pci_arg); 951} 952 953#ifdef PSYCHO_STRAY 954/* 955 * Write to the correct clr register and return. arg is the address of the clear 956 * register to be used. 957 * XXX: print a message? 958 */ 959static void 960psycho_intr_stray(void *arg) 961{ 962 963 *((u_long *)arg) = 0; 964} 965#endif 966 967static int 968psycho_setup_intr(device_t dev, device_t child, 969 struct resource *ires, int flags, driver_intr_t *intr, void *arg, 970 void **cookiep) 971{ 972 struct psycho_softc *sc; 973 struct psycho_clr *pc; 974 u_long *intrmapptr, *intrclrptr; 975 int ino; 976 int error; 977 long vec = rman_get_start(ires); 978 979 sc = (struct psycho_softc *)device_get_softc(dev); 980 pc = (struct psycho_clr *) 981 malloc(sizeof(*pc), M_DEVBUF, M_NOWAIT); 982 if (pc == NULL) 983 return (NULL); 984 985 /* 986 * Hunt through all the interrupt mapping regs to look for our 987 * interrupt vector. 988 * 989 * XXX We only compare INOs rather than IGNs since the firmware may 990 * not provide the IGN and the IGN is constant for all device on that 991 * PCI controller. This could cause problems for the FFB/external 992 * interrupt which has a full vector that can be set arbitrarily. 993 */ 994 ino = INTINO(vec); 995 996 if (!psycho_find_intrmap(sc, ino, &intrmapptr, &intrclrptr, NULL)) { 997 printf("Cannot find interrupt vector %lx\n", vec); 998 free(pc, M_DEVBUF); 999 return (NULL); 1000 } 1001 1002#ifdef PSYCHO_DEBUG 1003 device_printf(dev, "psycho_setup_intr: INO %d, map %p, clr %p\n", ino, 1004 intrmapptr, intrclrptr); 1005#endif 1006 pc->pci_arg = arg; 1007 pc->pci_handler = intr; 1008 pc->pci_clr = intrclrptr; 1009 /* Disable the interrupt while we fiddle with it */ 1010 *intrmapptr &= ~INTMAP_V; 1011 membar(Sync); 1012 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 1013 psycho_intr_stub, pc, cookiep); 1014 if (error != 0) { 1015 free(pc, M_DEVBUF); 1016 return (error); 1017 } 1018 pc->pci_cookie = *cookiep; 1019 *cookiep = pc; 1020 1021 /* 1022 * Clear the interrupt, it might have been triggered before it was 1023 * set up. 1024 */ 1025 *intrclrptr = 0; 1026 membar(StoreStore); 1027 /* 1028 * Enable the interrupt now we have the handler installed. 1029 * Read the current value as we can't change it besides the 1030 * valid bit so so make sure only this bit is changed. 1031 */ 1032 *intrmapptr |= INTMAP_V; 1033 return (error); 1034} 1035 1036static int 1037psycho_teardown_intr(device_t dev, device_t child, 1038 struct resource *vec, void *cookie) 1039{ 1040 struct psycho_clr *pc; 1041 int error; 1042 1043 pc = (struct psycho_clr *)cookie; 1044 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 1045 pc->pci_cookie); 1046 /* 1047 * Don't disable the interrupt for now, so that stray interupts get 1048 * detected... 1049 */ 1050 if (error != 0) 1051 free(pc, M_DEVBUF); 1052 return (error); 1053} 1054 1055static struct resource * 1056psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1057 u_long start, u_long end, u_long count, u_int flags) 1058{ 1059 struct psycho_softc *sc; 1060 struct resource *rv; 1061 struct rman *rm; 1062 bus_space_tag_t bt; 1063 bus_space_handle_t bh; 1064 int needactivate = flags & RF_ACTIVE; 1065 1066 flags &= ~RF_ACTIVE; 1067 1068 sc = (struct psycho_softc *)device_get_softc(bus); 1069 if (type == SYS_RES_IRQ) { 1070 /* 1071 * XXX: Don't accept blank ranges for now, only single 1072 * interrupts. The other case should not happen with the MI pci 1073 * code... 1074 * XXX: This may return a resource that is out of the range 1075 * that was specified. Is this correct...? 1076 */ 1077 if (start != end) 1078 panic("psycho_alloc_resource: XXX: interrupt range"); 1079 start = end |= sc->sc_ign; 1080 return (bus_alloc_resource(bus, type, rid, start, end, 1081 count, flags)); 1082 } 1083 switch (type) { 1084 case SYS_RES_MEMORY: 1085 rm = &sc->sc_mem_rman; 1086 bt = sc->sc_memt; 1087 bh = sc->sc_bh[PCI_CS_MEM32]; 1088 break; 1089 case SYS_RES_IOPORT: 1090 rm = &sc->sc_io_rman; 1091 bt = sc->sc_iot; 1092 /* XXX: probably should use ranges property here. */ 1093 bh = sc->sc_bh[PCI_CS_IO]; 1094 break; 1095 default: 1096 return (NULL); 1097 } 1098 1099 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1100 if (rv == NULL) 1101 return (NULL); 1102 1103 bh += rman_get_start(rv); 1104 rman_set_bustag(rv, bt); 1105 rman_set_bushandle(rv, bh); 1106 1107 if (needactivate) { 1108 if (bus_activate_resource(child, type, *rid, rv)) { 1109 rman_release_resource(rv); 1110 return (NULL); 1111 } 1112 } 1113 1114 return (rv); 1115} 1116 1117static int 1118psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1119 struct resource *r) 1120{ 1121 1122 if (type == SYS_RES_IRQ) 1123 return (bus_activate_resource(bus, type, rid, r)); 1124 return (rman_activate_resource(r)); 1125} 1126 1127static int 1128psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1129 struct resource *r) 1130{ 1131 1132 if (type == SYS_RES_IRQ) 1133 return (bus_deactivate_resource(bus, type, rid, r)); 1134 return (rman_deactivate_resource(r)); 1135} 1136 1137static int 1138psycho_release_resource(device_t bus, device_t child, int type, int rid, 1139 struct resource *r) 1140{ 1141 int error; 1142 1143 if (type == SYS_RES_IRQ) 1144 return (bus_release_resource(bus, type, rid, r)); 1145 if (rman_get_flags(r) & RF_ACTIVE) { 1146 error = bus_deactivate_resource(child, type, rid, r); 1147 if (error) 1148 return error; 1149 } 1150 return (rman_release_resource(r)); 1151} 1152 1153static int 1154psycho_intr_pending(device_t dev, int intr) 1155{ 1156 struct psycho_softc *sc; 1157 u_long diag; 1158 1159 sc = (struct psycho_softc *)device_get_softc(dev); 1160 if (!psycho_find_intrmap(sc, intr, NULL, NULL, &diag)) { 1161 printf("psycho_intr_pending: mapping not found for %d\n", intr); 1162 return (0); 1163 } 1164 return (diag != 0); 1165} 1166 1167static bus_space_handle_t 1168psycho_get_bus_handle(device_t dev, enum sbbt_id id, 1169 bus_space_handle_t childhdl, bus_space_tag_t *tag) 1170{ 1171 struct psycho_softc *sc; 1172 1173 sc = (struct psycho_softc *)device_get_softc(dev); 1174 switch(id) { 1175 case SBBT_IO: 1176 *tag = sc->sc_iot; 1177 return (sc->sc_bh[PCI_CS_IO] + childhdl); 1178 case SBBT_MEM: 1179 *tag = sc->sc_memt; 1180 return (sc->sc_bh[PCI_CS_MEM32] + childhdl); 1181 default: 1182 panic("psycho_get_bus_handle: illegal space\n"); 1183 } 1184} 1185 1186/* 1187 * below here is bus space and bus dma support 1188 */ 1189static bus_space_tag_t 1190psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1191{ 1192 bus_space_tag_t bt; 1193 1194 bt = (bus_space_tag_t) 1195 malloc(sizeof(struct bus_space_tag), M_DEVBUF, M_NOWAIT); 1196 if (bt == NULL) 1197 panic("could not allocate psycho bus tag"); 1198 1199 bzero(bt, sizeof *bt); 1200 bt->cookie = sc; 1201 bt->parent = sc->sc_bustag; 1202 bt->type = type; 1203 return (bt); 1204} 1205 1206/* 1207 * hooks into the iommu dvma calls. 1208 */ 1209static int 1210psycho_dmamem_alloc(bus_dma_tag_t dmat, void **vaddr, int flags, bus_dmamap_t *mapp) 1211{ 1212 struct psycho_softc *sc; 1213 1214 sc = (struct psycho_softc *)dmat->cookie; 1215 return (iommu_dvmamem_alloc(dmat, sc->sc_is, vaddr, flags, mapp)); 1216} 1217 1218static void 1219psycho_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map) 1220{ 1221 struct psycho_softc *sc; 1222 1223 sc = (struct psycho_softc *)dmat->cookie; 1224 return (iommu_dvmamem_free(dmat, sc->sc_is, vaddr, map)); 1225} 1226 1227static int 1228psycho_dmamap_load(bus_dma_tag_t dmat, bus_dmamap_t map, void *buf, 1229 bus_size_t buflen, bus_dmamap_callback_t *callback, void *callback_arg, 1230 int flags) 1231{ 1232 struct psycho_softc *sc; 1233 1234 sc = (struct psycho_softc *)dmat->cookie; 1235 return (iommu_dvmamap_load(dmat, sc->sc_is, map, buf, buflen, callback, 1236 callback_arg, flags)); 1237} 1238 1239static void 1240psycho_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t map) 1241{ 1242 struct psycho_softc *sc; 1243 1244 sc = (struct psycho_softc *)dmat->cookie; 1245 iommu_dvmamap_unload(dmat, sc->sc_is, map); 1246} 1247 1248static void 1249psycho_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, 1250 bus_dmasync_op_t op) 1251{ 1252 struct psycho_softc *sc; 1253 1254 sc = (struct psycho_softc *)dmat->cookie; 1255 iommu_dvmamap_sync(dmat, sc->sc_is, map, op); 1256} 1257