psycho.c revision 215349
1/*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/sparc64/pci/psycho.c 215349 2010-11-15 21:58:10Z marius $"); 35 36/* 37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+' 38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges. 39 */ 40 41#include "opt_ofw_pci.h" 42#include "opt_psycho.h" 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/bus.h> 47#include <sys/endian.h> 48#include <sys/kdb.h> 49#include <sys/kernel.h> 50#include <sys/lock.h> 51#include <sys/malloc.h> 52#include <sys/module.h> 53#include <sys/mutex.h> 54#include <sys/pcpu.h> 55#include <sys/reboot.h> 56#include <sys/rman.h> 57 58#include <dev/ofw/ofw_bus.h> 59#include <dev/ofw/ofw_pci.h> 60#include <dev/ofw/openfirm.h> 61 62#include <machine/bus.h> 63#include <machine/bus_common.h> 64#include <machine/bus_private.h> 65#include <machine/iommureg.h> 66#include <machine/iommuvar.h> 67#include <machine/resource.h> 68#include <machine/ver.h> 69 70#include <dev/pci/pcireg.h> 71#include <dev/pci/pcivar.h> 72 73#include <sparc64/pci/ofw_pci.h> 74#include <sparc64/pci/psychoreg.h> 75#include <sparc64/pci/psychovar.h> 76 77#include "pcib_if.h" 78 79static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *, 80 const char *); 81static const struct psycho_desc *psycho_get_desc(device_t); 82static void psycho_set_intr(struct psycho_softc *, u_int, bus_addr_t, 83 driver_filter_t, driver_intr_t); 84static int psycho_find_intrmap(struct psycho_softc *, u_int, bus_addr_t *, 85 bus_addr_t *, u_long *); 86static driver_filter_t psycho_dma_sync_stub; 87static void psycho_intr_enable(void *); 88static void psycho_intr_disable(void *); 89static void psycho_intr_assign(void *); 90static void psycho_intr_clear(void *); 91static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 92 93/* Interrupt handlers */ 94static driver_filter_t psycho_ue; 95static driver_filter_t psycho_ce; 96static driver_filter_t psycho_pci_bus; 97static driver_filter_t psycho_powerfail; 98static driver_intr_t psycho_overtemp; 99#ifdef PSYCHO_MAP_WAKEUP 100static driver_filter_t psycho_wakeup; 101#endif 102 103/* IOMMU support */ 104static void psycho_iommu_init(struct psycho_softc *, int, uint32_t); 105 106/* 107 * Methods 108 */ 109static device_probe_t psycho_probe; 110static device_attach_t psycho_attach; 111static bus_read_ivar_t psycho_read_ivar; 112static bus_setup_intr_t psycho_setup_intr; 113static bus_teardown_intr_t psycho_teardown_intr; 114static bus_alloc_resource_t psycho_alloc_resource; 115static bus_activate_resource_t psycho_activate_resource; 116static bus_deactivate_resource_t psycho_deactivate_resource; 117static bus_release_resource_t psycho_release_resource; 118static bus_describe_intr_t psycho_describe_intr; 119static bus_get_dma_tag_t psycho_get_dma_tag; 120static pcib_maxslots_t psycho_maxslots; 121static pcib_read_config_t psycho_read_config; 122static pcib_write_config_t psycho_write_config; 123static pcib_route_interrupt_t psycho_route_interrupt; 124static ofw_bus_get_node_t psycho_get_node; 125 126static device_method_t psycho_methods[] = { 127 /* Device interface */ 128 DEVMETHOD(device_probe, psycho_probe), 129 DEVMETHOD(device_attach, psycho_attach), 130 DEVMETHOD(device_shutdown, bus_generic_shutdown), 131 DEVMETHOD(device_suspend, bus_generic_suspend), 132 DEVMETHOD(device_resume, bus_generic_resume), 133 134 /* Bus interface */ 135 DEVMETHOD(bus_print_child, bus_generic_print_child), 136 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 137 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 138 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 139 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 140 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 141 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 142 DEVMETHOD(bus_release_resource, psycho_release_resource), 143 DEVMETHOD(bus_describe_intr, psycho_describe_intr), 144 DEVMETHOD(bus_get_dma_tag, psycho_get_dma_tag), 145 146 /* pcib interface */ 147 DEVMETHOD(pcib_maxslots, psycho_maxslots), 148 DEVMETHOD(pcib_read_config, psycho_read_config), 149 DEVMETHOD(pcib_write_config, psycho_write_config), 150 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 151 152 /* ofw_bus interface */ 153 DEVMETHOD(ofw_bus_get_node, psycho_get_node), 154 155 KOBJMETHOD_END 156}; 157 158static devclass_t psycho_devclass; 159 160DEFINE_CLASS_0(pcib, psycho_driver, psycho_methods, 161 sizeof(struct psycho_softc)); 162EARLY_DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0, 163 BUS_PASS_BUS); 164 165static SLIST_HEAD(, psycho_softc) psycho_softcs = 166 SLIST_HEAD_INITIALIZER(psycho_softcs); 167 168static const struct intr_controller psycho_ic = { 169 psycho_intr_enable, 170 psycho_intr_disable, 171 psycho_intr_assign, 172 psycho_intr_clear 173}; 174 175struct psycho_icarg { 176 struct psycho_softc *pica_sc; 177 bus_addr_t pica_map; 178 bus_addr_t pica_clr; 179}; 180 181struct psycho_dma_sync { 182 struct psycho_softc *pds_sc; 183 driver_filter_t *pds_handler; /* handler to call */ 184 void *pds_arg; /* argument for the handler */ 185 void *pds_cookie; /* parent bus int. cookie */ 186 device_t pds_ppb; /* farest PCI-PCI bridge */ 187 uint8_t pds_bus; /* bus of farest PCI dev. */ 188 uint8_t pds_slot; /* slot of farest PCI dev. */ 189 uint8_t pds_func; /* func. of farest PCI dev. */ 190}; 191 192#define PSYCHO_READ8(sc, off) \ 193 bus_read_8((sc)->sc_mem_res, (off)) 194#define PSYCHO_WRITE8(sc, off, v) \ 195 bus_write_8((sc)->sc_mem_res, (off), (v)) 196#define PCICTL_READ8(sc, off) \ 197 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 198#define PCICTL_WRITE8(sc, off, v) \ 199 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 200 201/* 202 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 203 * single PCI bus and does not have a streaming buffer. It often has an APB 204 * (advanced PCI bridge) connected to it, which was designed specifically for 205 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 206 * appears as two "Simba"'s underneath the Sabre. 207 * 208 * "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's 209 * basically the same as Sabre but without an APB underneath it. 210 * 211 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA 212 * bus and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while 213 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 214 * will usually find a "Psycho+" since I don't think the original "Psycho" 215 * ever shipped, and if it did it would be in the U30. 216 * 217 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are 218 * both part of the same IC, they only have a single register space. As such, 219 * they need to be configured together, even though the autoconfiguration will 220 * attach them separately. 221 * 222 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often 223 * as pci1 and pci2, although they have been implemented with other PCI bus 224 * numbers on some machines. 225 * 226 * On UltraII machines, there can be any number of "Psycho+" ICs, each 227 * providing two PCI buses. 228 */ 229 230struct psycho_desc { 231 const char *pd_string; 232 int pd_mode; 233 const char *pd_name; 234}; 235 236static const struct psycho_desc const psycho_compats[] = { 237 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 238 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" }, 239 { "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" }, 240 { NULL, 0, NULL } 241}; 242 243static const struct psycho_desc const psycho_models[] = { 244 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 245 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 246 { NULL, 0, NULL } 247}; 248 249static const struct psycho_desc * 250psycho_find_desc(const struct psycho_desc *table, const char *string) 251{ 252 const struct psycho_desc *desc; 253 254 if (string == NULL) 255 return (NULL); 256 for (desc = table; desc->pd_string != NULL; desc++) 257 if (strcmp(desc->pd_string, string) == 0) 258 return (desc); 259 return (NULL); 260} 261 262static const struct psycho_desc * 263psycho_get_desc(device_t dev) 264{ 265 const struct psycho_desc *rv; 266 267 rv = psycho_find_desc(psycho_models, ofw_bus_get_model(dev)); 268 if (rv == NULL) 269 rv = psycho_find_desc(psycho_compats, 270 ofw_bus_get_compat(dev)); 271 return (rv); 272} 273 274static int 275psycho_probe(device_t dev) 276{ 277 const char *dtype; 278 279 dtype = ofw_bus_get_type(dev); 280 if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 && 281 psycho_get_desc(dev) != NULL) { 282 device_set_desc(dev, "U2P UPA-PCI bridge"); 283 return (0); 284 } 285 return (ENXIO); 286} 287 288static int 289psycho_attach(device_t dev) 290{ 291 char name[sizeof("pci108e,1000")]; 292 struct psycho_icarg *pica; 293 struct psycho_softc *asc, *sc, *osc; 294 struct ofw_pci_ranges *range; 295 const struct psycho_desc *desc; 296 bus_addr_t intrclr, intrmap; 297 uint64_t csr, dr; 298 phandle_t child, node; 299 uint32_t dvmabase, prop, prop_array[2]; 300 int32_t rev; 301 u_int rerun, ver; 302 int i, j; 303 304 node = ofw_bus_get_node(dev); 305 sc = device_get_softc(dev); 306 desc = psycho_get_desc(dev); 307 308 sc->sc_node = node; 309 sc->sc_dev = dev; 310 sc->sc_mode = desc->pd_mode; 311 312 /* 313 * The Psycho gets three register banks: 314 * (0) per-PBM configuration and status registers 315 * (1) per-PBM PCI configuration space, containing only the 316 * PBM 256-byte PCI header 317 * (2) the shared Psycho configuration registers 318 */ 319 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 320 i = 2; 321 sc->sc_pcictl = 322 bus_get_resource_start(dev, SYS_RES_MEMORY, 0) - 323 bus_get_resource_start(dev, SYS_RES_MEMORY, 2); 324 switch (sc->sc_pcictl) { 325 case PSR_PCICTL0: 326 sc->sc_half = 0; 327 break; 328 case PSR_PCICTL1: 329 sc->sc_half = 1; 330 break; 331 default: 332 panic("%s: bogus PCI control register location", 333 __func__); 334 /* NOTREACHED */ 335 } 336 } else { 337 i = 0; 338 sc->sc_pcictl = PSR_PCICTL0; 339 sc->sc_half = 0; 340 } 341 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i, 342 (sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) | 343 RF_ACTIVE); 344 if (sc->sc_mem_res == NULL) 345 panic("%s: could not allocate registers", __func__); 346 347 /* 348 * Match other Psychos that are already configured against 349 * the base physical address. This will be the same for a 350 * pair of devices that share register space. 351 */ 352 osc = NULL; 353 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 354 if (rman_get_start(asc->sc_mem_res) == 355 rman_get_start(sc->sc_mem_res)) { 356 /* Found partner. */ 357 osc = asc; 358 break; 359 } 360 } 361 if (osc == NULL) { 362 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 363 M_NOWAIT | M_ZERO); 364 if (sc->sc_mtx == NULL) 365 panic("%s: could not malloc mutex", __func__); 366 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 367 } else { 368 if (sc->sc_mode != PSYCHO_MODE_PSYCHO) 369 panic("%s: no partner expected", __func__); 370 if (mtx_initialized(osc->sc_mtx) == 0) 371 panic("%s: mutex not initialized", __func__); 372 sc->sc_mtx = osc->sc_mtx; 373 } 374 375 csr = PSYCHO_READ8(sc, PSR_CS); 376 ver = PSYCHO_GCSR_VERS(csr); 377 sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */ 378 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 379 sc->sc_ign = PSYCHO_GCSR_IGN(csr); 380 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 381 prop = 33000000; 382 383 device_printf(dev, 384 "%s, impl %d, version %d, IGN %#x, bus %c, %dMHz\n", 385 desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign, 386 'A' + sc->sc_half, prop / 1000 / 1000); 387 388 /* Set up the PCI control and PCI diagnostic registers. */ 389 390 /* 391 * Revision 0 EBus bridges have a bug which prevents them from 392 * working when bus parking is enabled. 393 */ 394 rev = -1; 395 csr = PCICTL_READ8(sc, PCR_CS); 396 csr &= ~PCICTL_ARB_PARK; 397 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 398 if (OF_getprop(child, "name", name, sizeof(name)) == -1) 399 continue; 400 if ((strcmp(name, "ebus") == 0 || 401 strcmp(name, "pci108e,1000") == 0) && 402 OF_getprop(child, "revision-id", &rev, sizeof(rev)) > 0 && 403 rev == 0) 404 break; 405 } 406 if (rev != 0 && OF_getproplen(node, "no-bus-parking") < 0) 407 csr |= PCICTL_ARB_PARK; 408 409 /* Workarounds for version specific bugs. */ 410 dr = PCICTL_READ8(sc, PCR_DIAG); 411 switch (ver) { 412 case 0: 413 dr |= DIAG_RTRY_DIS; 414 dr &= ~DIAG_DWSYNC_DIS; 415 rerun = 0; 416 break; 417 case 1: 418 csr &= ~PCICTL_ARB_PARK; 419 dr |= DIAG_RTRY_DIS | DIAG_DWSYNC_DIS; 420 rerun = 0; 421 break; 422 default: 423 dr |= DIAG_DWSYNC_DIS; 424 dr &= ~DIAG_RTRY_DIS; 425 rerun = 1; 426 break; 427 } 428 429 csr |= PCICTL_ERRINTEN | PCICTL_ARB_4; 430 csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN); 431#ifdef PSYCHO_DEBUG 432 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 433 (unsigned long long)PCICTL_READ8(sc, PCR_CS), 434 (unsigned long long)csr); 435#endif 436 PCICTL_WRITE8(sc, PCR_CS, csr); 437 438 dr &= ~DIAG_ISYNC_DIS; 439#ifdef PSYCHO_DEBUG 440 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 441 (unsigned long long)PCICTL_READ8(sc, PCR_DIAG), 442 (unsigned long long)dr); 443#endif 444 PCICTL_WRITE8(sc, PCR_DIAG, dr); 445 446 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 447 /* Use the PROM preset for now. */ 448 csr = PCICTL_READ8(sc, PCR_TAS); 449 if (csr == 0) 450 panic("%s: Hummingbird/Sabre TAS not initialized.", 451 __func__); 452 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT; 453 } else 454 dvmabase = -1; 455 456 /* Initialize memory and I/O rmans. */ 457 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 458 sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports"; 459 if (rman_init(&sc->sc_pci_io_rman) != 0 || 460 rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0) 461 panic("%s: failed to set up I/O rman", __func__); 462 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 463 sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory"; 464 if (rman_init(&sc->sc_pci_mem_rman) != 0 || 465 rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 466 panic("%s: failed to set up memory rman", __func__); 467 468 i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range); 469 /* 470 * Make sure that the expected ranges are present. The 471 * OFW_PCI_CS_MEM64 one is not currently used though. 472 */ 473 if (i != PSYCHO_NRANGE) 474 panic("%s: unsupported number of ranges", __func__); 475 /* 476 * Find the addresses of the various bus spaces. 477 * There should not be multiple ones of one kind. 478 * The physical start addresses of the ranges are the configuration, 479 * memory and I/O handles. 480 */ 481 for (i = 0; i < PSYCHO_NRANGE; i++) { 482 j = OFW_PCI_RANGE_CS(&range[i]); 483 if (sc->sc_pci_bh[j] != 0) 484 panic("%s: duplicate range for space %d", 485 __func__, j); 486 sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]); 487 } 488 free(range, M_OFWPROP); 489 490 /* Register the softc, this is needed for paired Psychos. */ 491 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 492 493 /* 494 * If we're a Hummingbird/Sabre or the first of a pair of Psychos 495 * to arrive here, do the interrupt setup and start up the IOMMU. 496 */ 497 if (osc == NULL) { 498 /* 499 * Hunt through all the interrupt mapping regs and register 500 * our interrupt controller for the corresponding interrupt 501 * vectors. We do this early in order to be able to catch 502 * stray interrupts. 503 */ 504 for (i = 0; i <= PSYCHO_MAX_INO; i++) { 505 if (psycho_find_intrmap(sc, i, &intrmap, &intrclr, 506 NULL) == 0) 507 continue; 508 pica = malloc(sizeof(*pica), M_DEVBUF, M_NOWAIT); 509 if (pica == NULL) 510 panic("%s: could not allocate interrupt " 511 "controller argument", __func__); 512 pica->pica_sc = sc; 513 pica->pica_map = intrmap; 514 pica->pica_clr = intrclr; 515#ifdef PSYCHO_DEBUG 516 /* 517 * Enable all interrupts and clear all interrupt 518 * states. This aids the debugging of interrupt 519 * routing problems. 520 */ 521 device_printf(dev, 522 "intr map (INO %d, %s) %#lx: %#lx, clr: %#lx\n", 523 i, intrmap <= PSR_PCIB3_INT_MAP ? "PCI" : "OBIO", 524 (u_long)intrmap, (u_long)PSYCHO_READ8(sc, 525 intrmap), (u_long)intrclr); 526 PSYCHO_WRITE8(sc, intrmap, INTMAP_VEC(sc->sc_ign, i)); 527 PSYCHO_WRITE8(sc, intrclr, INTCLR_IDLE); 528 PSYCHO_WRITE8(sc, intrmap, 529 INTMAP_ENABLE(INTMAP_VEC(sc->sc_ign, i), 530 PCPU_GET(mid))); 531#endif 532 j = intr_controller_register(INTMAP_VEC(sc->sc_ign, 533 i), &psycho_ic, pica); 534 if (j != 0) 535 device_printf(dev, "could not register " 536 "interrupt controller for INO %d (%d)\n", 537 i, j); 538 } 539 540 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 541 sparc64_counter_init(device_get_nameunit(dev), 542 rman_get_bustag(sc->sc_mem_res), 543 rman_get_bushandle(sc->sc_mem_res), PSR_TC0); 544 545 /* 546 * Set up IOMMU and PCI configuration if we're the first 547 * of a pair of Psychos to arrive here or a Hummingbird 548 * or Sabre. 549 * 550 * We should calculate a TSB size based on amount of RAM 551 * and number of bus controllers and number and type of 552 * child devices. 553 * 554 * For the moment, 32KB should be more than enough. 555 */ 556 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 557 M_NOWAIT | M_ZERO); 558 if (sc->sc_is == NULL) 559 panic("%s: malloc iommu_state failed", __func__); 560 sc->sc_is->is_flags = IOMMU_PRESERVE_PROM; 561 if (sc->sc_mode == PSYCHO_MODE_SABRE) 562 sc->sc_is->is_pmaxaddr = 563 IOMMU_MAXADDR(SABRE_IOMMU_BITS); 564 else 565 sc->sc_is->is_pmaxaddr = 566 IOMMU_MAXADDR(PSYCHO_IOMMU_BITS); 567 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = 0; 568 if (OF_getproplen(node, "no-streaming-cache") < 0) 569 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 570 sc->sc_is->is_flags |= (rerun != 1) ? IOMMU_RERUN_DISABLE : 0; 571 psycho_iommu_init(sc, 3, dvmabase); 572 } else { 573 /* Just copy IOMMU state, config tag and address. */ 574 sc->sc_is = osc->sc_is; 575 if (OF_getproplen(node, "no-streaming-cache") < 0) 576 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 577 iommu_reset(sc->sc_is); 578 } 579 580 /* Allocate our tags. */ 581 sc->sc_pci_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 582 sc->sc_pci_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 583 sc->sc_pci_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 584 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 585 sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr, 586 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0) 587 panic("%s: bus_dma_tag_create failed", __func__); 588 /* Customize the tag. */ 589 sc->sc_pci_dmat->dt_cookie = sc->sc_is; 590 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 591 592 i = OF_getprop(node, "bus-range", (void *)prop_array, 593 sizeof(prop_array)); 594 if (i == -1) 595 panic("%s: could not get bus-range", __func__); 596 if (i != sizeof(prop_array)) 597 panic("%s: broken bus-range (%d)", __func__, i); 598 sc->sc_pci_secbus = prop_array[0]; 599 sc->sc_pci_subbus = prop_array[1]; 600 if (bootverbose) 601 device_printf(dev, "bus range %u to %u; PCI bus %d\n", 602 sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus); 603 604 /* Clear any pending PCI error bits. */ 605 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, 606 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 607 PCS_DEVICE, PCS_FUNC, PCIR_STATUS, 2), 2); 608 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS)); 609 PCICTL_WRITE8(sc, PCR_AFS, PCICTL_READ8(sc, PCR_AFS)); 610 611 if (osc == NULL) { 612 /* 613 * Establish handlers for interesting interrupts... 614 * 615 * XXX We need to remember these and remove this to support 616 * hotplug on the UPA/FHC bus. 617 * 618 * XXX Not all controllers have these, but installing them 619 * is better than trying to sort through this mess. 620 */ 621 psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL); 622 psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL); 623#ifdef DEBUGGER_ON_POWERFAIL 624 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, psycho_powerfail, 625 NULL); 626#else 627 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL, 628 (driver_intr_t *)psycho_powerfail); 629#endif 630 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 631 /* 632 * Hummingbirds/Sabres do not have the following two 633 * interrupts. 634 */ 635 636 /* 637 * The spare hardware interrupt is used for the 638 * over-temperature interrupt. 639 */ 640 psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP, 641 NULL, psycho_overtemp); 642#ifdef PSYCHO_MAP_WAKEUP 643 /* 644 * psycho_wakeup() doesn't do anything useful right 645 * now. 646 */ 647 psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP, 648 psycho_wakeup, NULL); 649#endif /* PSYCHO_MAP_WAKEUP */ 650 } 651 } 652 /* 653 * Register a PCI bus error interrupt handler according to which 654 * half this is. Hummingbird/Sabre don't have a PCI bus B error 655 * interrupt but they are also only used for PCI bus A. 656 */ 657 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP : 658 PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL); 659 660 /* 661 * Set the latency timer register as this isn't always done by the 662 * firmware. 663 */ 664 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, 665 PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 666 667 for (i = PCIR_VENDOR; i < PCIR_STATUS; i += sizeof(uint16_t)) 668 le16enc(&sc->sc_pci_hpbcfg[i], bus_space_read_2( 669 sc->sc_pci_cfgt, sc->sc_pci_bh[OFW_PCI_CS_CONFIG], 670 PSYCHO_CONF_OFF(sc->sc_pci_secbus, PCS_DEVICE, 671 PCS_FUNC, i))); 672 for (i = PCIR_REVID; i <= PCIR_BIST; i += sizeof(uint8_t)) 673 sc->sc_pci_hpbcfg[i] = bus_space_read_1(sc->sc_pci_cfgt, 674 sc->sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF( 675 sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, i)); 676 677 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 678 /* 679 * On E250 the interrupt map entry for the EBus bridge is wrong, 680 * causing incorrect interrupts to be assigned to some devices on 681 * the EBus. Work around it by changing our copy of the interrupt 682 * map mask to perform a full comparison of the INO. That way 683 * the interrupt map entry for the EBus bridge won't match at all 684 * and the INOs specified in the "interrupts" properties of the 685 * EBus devices will be used directly instead. 686 */ 687 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 && 688 sc->sc_pci_iinfo.opi_imapmsk != NULL) 689 *(ofw_pci_intr_t *)(&sc->sc_pci_iinfo.opi_imapmsk[ 690 sc->sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK; 691 692 device_add_child(dev, "pci", -1); 693 return (bus_generic_attach(dev)); 694} 695 696static void 697psycho_set_intr(struct psycho_softc *sc, u_int index, bus_addr_t intrmap, 698 driver_filter_t filt, driver_intr_t intr) 699{ 700 u_long vec; 701 int rid; 702 703 rid = index; 704 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, 705 SYS_RES_IRQ, &rid, RF_ACTIVE); 706 if (sc->sc_irq_res[index] == NULL && intrmap >= PSR_POWER_INT_MAP) { 707 /* 708 * These interrupts aren't mandatory and not available 709 * with all controllers (not even Psychos). 710 */ 711 return; 712 } 713 if (sc->sc_irq_res[index] == NULL || 714 INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) != 715 sc->sc_ign || 716 INTVEC(PSYCHO_READ8(sc, intrmap)) != vec || 717 intr_vectors[vec].iv_ic != &psycho_ic || 718 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 719 INTR_TYPE_MISC | INTR_FAST, filt, intr, sc, 720 &sc->sc_ihand[index]) != 0) 721 panic("%s: failed to set up interrupt %d", __func__, index); 722} 723 724static int 725psycho_find_intrmap(struct psycho_softc *sc, u_int ino, 726 bus_addr_t *intrmapptr, bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 727{ 728 bus_addr_t intrclr, intrmap; 729 uint64_t diag; 730 int found; 731 732 /* 733 * XXX we only compare INOs rather than INRs since the firmware may 734 * not provide the IGN and the IGN is constant for all devices on 735 * that PCI controller. 736 * This could cause problems for the FFB/external interrupt which 737 * has a full vector that can be set arbitrarily. 738 */ 739 740 if (ino > PSYCHO_MAX_INO) { 741 device_printf(sc->sc_dev, "out of range INO %d requested\n", 742 ino); 743 return (0); 744 } 745 746 found = 0; 747 /* Hunt through OBIO first. */ 748 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 749 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 750 intrmap <= PSR_PWRMGT_INT_MAP; intrmap += 8, intrclr += 8, 751 diag >>= 2) { 752 if (sc->sc_mode == PSYCHO_MODE_SABRE && 753 (intrmap == PSR_TIMER0_INT_MAP || 754 intrmap == PSR_TIMER1_INT_MAP || 755 intrmap == PSR_PCIBERR_INT_MAP || 756 intrmap == PSR_PWRMGT_INT_MAP)) 757 continue; 758 if (INTINO(PSYCHO_READ8(sc, intrmap)) == ino) { 759 diag &= 2; 760 found = 1; 761 break; 762 } 763 } 764 765 if (!found) { 766 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 767 /* Now do PCI interrupts. */ 768 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 769 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 770 diag >>= 8) { 771 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 772 (intrmap == PSR_PCIA2_INT_MAP || 773 intrmap == PSR_PCIA3_INT_MAP)) 774 continue; 775 if (((PSYCHO_READ8(sc, intrmap) ^ ino) & 0x3c) == 0) { 776 intrclr += 8 * (ino & 3); 777 diag = (diag >> ((ino & 3) * 2)) & 2; 778 found = 1; 779 break; 780 } 781 } 782 } 783 if (intrmapptr != NULL) 784 *intrmapptr = intrmap; 785 if (intrclrptr != NULL) 786 *intrclrptr = intrclr; 787 if (intrdiagptr != NULL) 788 *intrdiagptr = diag; 789 return (found); 790} 791 792/* 793 * Interrupt handlers 794 */ 795static int 796psycho_ue(void *arg) 797{ 798 struct psycho_softc *sc = arg; 799 uint64_t afar, afsr; 800 801 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 802 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 803 /* 804 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 805 * the AFAR to be set to the physical address of the TTE entry that 806 * was invalid/write protected. Call into the IOMMU code to have 807 * them decoded to virtual I/O addresses. 808 */ 809 if ((afsr & UEAFSR_P_DTE) != 0) 810 iommu_decode_fault(sc->sc_is, afar); 811 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx", 812 device_get_nameunit(sc->sc_dev), (u_long)afar, (u_long)afsr); 813 return (FILTER_HANDLED); 814} 815 816static int 817psycho_ce(void *arg) 818{ 819 struct psycho_softc *sc = arg; 820 uint64_t afar, afsr; 821 822 mtx_lock_spin(sc->sc_mtx); 823 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 824 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 825 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx " 826 "AFSR %#lx\n", (u_long)afar, (u_long)afsr); 827 /* Clear the error bits that we caught. */ 828 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr); 829 mtx_unlock_spin(sc->sc_mtx); 830 return (FILTER_HANDLED); 831} 832 833static int 834psycho_pci_bus(void *arg) 835{ 836 struct psycho_softc *sc = arg; 837 uint64_t afar, afsr; 838 839 afar = PCICTL_READ8(sc, PCR_AFA); 840 afsr = PCICTL_READ8(sc, PCR_AFS); 841 panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx", 842 device_get_nameunit(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar, 843 (u_long)afsr); 844 return (FILTER_HANDLED); 845} 846 847static int 848psycho_powerfail(void *arg) 849{ 850#ifdef DEBUGGER_ON_POWERFAIL 851 struct psycho_softc *sc = arg; 852 853 kdb_enter(KDB_WHY_POWERFAIL, "powerfail"); 854#else 855 static int shutdown; 856 857 /* As the interrupt is cleared we may be called multiple times. */ 858 if (shutdown != 0) 859 return (FILTER_HANDLED); 860 shutdown++; 861 printf("Power Failure Detected: Shutting down NOW.\n"); 862 shutdown_nice(0); 863#endif 864 return (FILTER_HANDLED); 865} 866 867static void 868psycho_overtemp(void *arg) 869{ 870 static int shutdown; 871 872 /* As the interrupt is cleared we may be called multiple times. */ 873 if (shutdown != 0) 874 return; 875 shutdown++; 876 printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n"); 877 shutdown_nice(RB_POWEROFF); 878} 879 880#ifdef PSYCHO_MAP_WAKEUP 881static int 882psycho_wakeup(void *arg) 883{ 884 struct psycho_softc *sc = arg; 885 886 /* We don't really have a framework to deal with this properly. */ 887 device_printf(sc->sc_dev, "power management wakeup\n"); 888 return (FILTER_HANDLED); 889} 890#endif /* PSYCHO_MAP_WAKEUP */ 891 892static void 893psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase) 894{ 895 struct iommu_state *is = sc->sc_is; 896 897 /* Punch in our copies. */ 898 is->is_bustag = rman_get_bustag(sc->sc_mem_res); 899 is->is_bushandle = rman_get_bushandle(sc->sc_mem_res); 900 is->is_iommu = PSR_IOMMU; 901 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 902 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 903 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 904 is->is_dva = PSR_IOMMU_SVADIAG; 905 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 906 907 iommu_init(device_get_nameunit(sc->sc_dev), is, tsbsize, dvmabase, 0); 908} 909 910static int 911psycho_maxslots(device_t dev) 912{ 913 914 /* XXX: is this correct? */ 915 return (PCI_SLOTMAX); 916} 917 918static uint32_t 919psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 920 int width) 921{ 922 struct psycho_softc *sc; 923 bus_space_handle_t bh; 924 u_long offset = 0; 925 uint8_t byte; 926 uint16_t shrt; 927 uint32_t r, wrd; 928 int i; 929 930 sc = device_get_softc(dev); 931 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 932 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 933 return (-1); 934 935 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 936 937 /* 938 * The Hummingbird and Sabre bridges are picky in that they 939 * only allow their config space to be accessed using the 940 * "native" width of the respective register being accessed 941 * and return semi-random other content of their config space 942 * otherwise. Given that the PCI specs don't say anything 943 * about such a (unusual) limitation and lots of stuff expects 944 * to be able to access the contents of the config space at 945 * any width we allow just that. We do this by using a copy 946 * of the header of the bridge (the rest is all zero anyway) 947 * read during attach (expect for PCIR_STATUS) in order to 948 * simplify things. 949 * The Psycho bridges contain a dupe of their header at 0x80 950 * which we nullify that way also. 951 */ 952 if (bus == sc->sc_pci_secbus && slot == PCS_DEVICE && 953 func == PCS_FUNC) { 954 if (offset % width != 0) 955 return (-1); 956 957 if (reg >= sizeof(sc->sc_pci_hpbcfg)) 958 return (0); 959 960 if ((reg < PCIR_STATUS && reg + width > PCIR_STATUS) || 961 reg == PCIR_STATUS || reg == PCIR_STATUS + 1) 962 le16enc(&sc->sc_pci_hpbcfg[PCIR_STATUS], 963 bus_space_read_2(sc->sc_pci_cfgt, bh, 964 PSYCHO_CONF_OFF(sc->sc_pci_secbus, 965 PCS_DEVICE, PCS_FUNC, PCIR_STATUS))); 966 967 switch (width) { 968 case 1: 969 return (sc->sc_pci_hpbcfg[reg]); 970 case 2: 971 return (le16dec(&sc->sc_pci_hpbcfg[reg])); 972 case 4: 973 return (le32dec(&sc->sc_pci_hpbcfg[reg])); 974 } 975 } 976 977 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 978 switch (width) { 979 case 1: 980 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 981 r = byte; 982 break; 983 case 2: 984 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 985 r = shrt; 986 break; 987 case 4: 988 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 989 r = wrd; 990 break; 991 default: 992 panic("%s: bad width", __func__); 993 /* NOTREACHED */ 994 } 995 996 if (i) { 997#ifdef PSYCHO_DEBUG 998 printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 999 __func__, bus, slot, func, reg); 1000#endif 1001 r = -1; 1002 } 1003 return (r); 1004} 1005 1006static void 1007psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, 1008 u_int reg, uint32_t val, int width) 1009{ 1010 struct psycho_softc *sc; 1011 bus_space_handle_t bh; 1012 u_long offset = 0; 1013 1014 sc = device_get_softc(dev); 1015 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 1016 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 1017 return; 1018 1019 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 1020 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1021 switch (width) { 1022 case 1: 1023 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 1024 break; 1025 case 2: 1026 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 1027 break; 1028 case 4: 1029 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 1030 break; 1031 default: 1032 panic("%s: bad width", __func__); 1033 /* NOTREACHED */ 1034 } 1035} 1036 1037static int 1038psycho_route_interrupt(device_t bridge, device_t dev, int pin) 1039{ 1040 struct psycho_softc *sc; 1041 struct ofw_pci_register reg; 1042 bus_addr_t intrmap; 1043 ofw_pci_intr_t pintr, mintr; 1044 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 1045 1046 sc = device_get_softc(bridge); 1047 pintr = pin; 1048 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, 1049 ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), 1050 NULL, maskbuf)) 1051 return (mintr); 1052 /* 1053 * If this is outside of the range for an intpin, it's likely a full 1054 * INO, and no mapping is required at all; this happens on the U30, 1055 * where there's no interrupt map at the Psycho node. Fortunately, 1056 * there seem to be no INOs in the intpin range on this boxen, so 1057 * this easy heuristics will do. 1058 */ 1059 if (pin > 4) 1060 return (pin); 1061 /* 1062 * Guess the INO; we always assume that this is a non-OBIO 1063 * device, and that pin is a "real" intpin number. Determine 1064 * the mapping register to be used by the slot number. 1065 * We only need to do this on E450s, it seems; here, the slot numbers 1066 * for bus A are one-based, while those for bus B seemingly have an 1067 * offset of 2 (hence the factor of 3 below). 1068 */ 1069 intrmap = PSR_PCIA0_INT_MAP + 1070 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half); 1071 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1; 1072 device_printf(bridge, 1073 "guessing interrupt %d for device %d.%d pin %d\n", 1074 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin); 1075 return (mintr); 1076} 1077 1078static int 1079psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1080{ 1081 struct psycho_softc *sc; 1082 1083 sc = device_get_softc(dev); 1084 switch (which) { 1085 case PCIB_IVAR_DOMAIN: 1086 *result = device_get_unit(dev); 1087 return (0); 1088 case PCIB_IVAR_BUS: 1089 *result = sc->sc_pci_secbus; 1090 return (0); 1091 } 1092 return (ENOENT); 1093} 1094 1095static int 1096psycho_dma_sync_stub(void *arg) 1097{ 1098 struct psycho_dma_sync *pds = arg; 1099 1100 (void)PCIB_READ_CONFIG(pds->pds_ppb, pds->pds_bus, pds->pds_slot, 1101 pds->pds_func, PCIR_VENDOR, 2); 1102 (void)PSYCHO_READ8(pds->pds_sc, PSR_DMA_WRITE_SYNC); 1103 return (pds->pds_handler(pds->pds_arg)); 1104} 1105 1106static void 1107psycho_intr_enable(void *arg) 1108{ 1109 struct intr_vector *iv = arg; 1110 struct psycho_icarg *pica = iv->iv_icarg; 1111 1112 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, 1113 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1114} 1115 1116static void 1117psycho_intr_disable(void *arg) 1118{ 1119 struct intr_vector *iv = arg; 1120 struct psycho_icarg *pica = iv->iv_icarg; 1121 1122 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, iv->iv_vec); 1123} 1124 1125static void 1126psycho_intr_assign(void *arg) 1127{ 1128 struct intr_vector *iv = arg; 1129 struct psycho_icarg *pica = iv->iv_icarg; 1130 1131 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, INTMAP_TID( 1132 PSYCHO_READ8(pica->pica_sc, pica->pica_map), iv->iv_mid)); 1133} 1134 1135static void 1136psycho_intr_clear(void *arg) 1137{ 1138 struct intr_vector *iv = arg; 1139 struct psycho_icarg *pica = iv->iv_icarg; 1140 1141 PSYCHO_WRITE8(pica->pica_sc, pica->pica_clr, INTCLR_IDLE); 1142} 1143 1144static int 1145psycho_setup_intr(device_t dev, device_t child, struct resource *ires, 1146 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1147 void **cookiep) 1148{ 1149 struct { 1150 int apb:1; 1151 int ppb:1; 1152 } found; 1153 devclass_t pci_devclass; 1154 device_t cdev, pdev, pcidev; 1155 struct psycho_softc *sc; 1156 struct psycho_dma_sync *pds; 1157 u_long vec; 1158 int error; 1159 1160 sc = device_get_softc(dev); 1161 /* 1162 * Make sure the vector is fully specified and we registered 1163 * our interrupt controller for it. 1164 */ 1165 vec = rman_get_start(ires); 1166 if (INTIGN(vec) != sc->sc_ign || 1167 intr_vectors[vec].iv_ic != &psycho_ic) { 1168 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1169 return (EINVAL); 1170 } 1171 1172 /* 1173 * The Sabre-APB-combination does not automatically flush DMA 1174 * write data for devices behind additional PCI-PCI bridges 1175 * underneath the APB PCI-PCI bridge. The procedure for a 1176 * manual flush is to do a PIO read on the far side of the 1177 * farthest PCI-PCI bridge followed by a read of the PCI DMA 1178 * write sync register of the Sabre. 1179 */ 1180 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 1181 pds = malloc(sizeof(*pds), M_DEVBUF, M_NOWAIT | M_ZERO); 1182 if (pds == NULL) 1183 return (ENOMEM); 1184 pcidev = NULL; 1185 found.apb = found.ppb = 0; 1186 pci_devclass = devclass_find("pci"); 1187 for (cdev = child; cdev != dev; cdev = pdev) { 1188 pdev = device_get_parent(cdev); 1189 if (pcidev == NULL) { 1190 if (device_get_devclass(pdev) != pci_devclass) 1191 continue; 1192 pcidev = cdev; 1193 continue; 1194 } 1195 /* 1196 * NB: APB would also match as PCI-PCI bridges. 1197 */ 1198 if (pci_get_vendor(cdev) == 0x108e && 1199 pci_get_device(cdev) == 0x5000) { 1200 found.apb = 1; 1201 break; 1202 } 1203 if (pci_get_class(cdev) == PCIC_BRIDGE && 1204 pci_get_subclass(cdev) == PCIS_BRIDGE_PCI) 1205 found.ppb = 1; 1206 } 1207 if (found.apb && found.ppb && pcidev != NULL) { 1208 pds->pds_sc = sc; 1209 pds->pds_arg = arg; 1210 pds->pds_ppb = 1211 device_get_parent(device_get_parent(pcidev)); 1212 pds->pds_bus = pci_get_bus(pcidev); 1213 pds->pds_slot = pci_get_slot(pcidev); 1214 pds->pds_func = pci_get_function(pcidev); 1215 if (bootverbose) 1216 device_printf(dev, "installed DMA sync " 1217 "wrapper for device %d.%d on bus %d\n", 1218 pds->pds_slot, pds->pds_func, 1219 pds->pds_bus); 1220 if (intr == NULL) { 1221 pds->pds_handler = filt; 1222 error = bus_generic_setup_intr(dev, child, 1223 ires, flags, psycho_dma_sync_stub, intr, 1224 pds, cookiep); 1225 } else { 1226 pds->pds_handler = (driver_filter_t *)intr; 1227 error = bus_generic_setup_intr(dev, child, 1228 ires, flags, filt, 1229 (driver_intr_t *)psycho_dma_sync_stub, 1230 pds, cookiep); 1231 } 1232 } else 1233 error = bus_generic_setup_intr(dev, child, ires, 1234 flags, filt, intr, arg, cookiep); 1235 if (error != 0) { 1236 free(pds, M_DEVBUF); 1237 return (error); 1238 } 1239 pds->pds_cookie = *cookiep; 1240 *cookiep = pds; 1241 return (error); 1242 } 1243 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1244 arg, cookiep)); 1245} 1246 1247static int 1248psycho_teardown_intr(device_t dev, device_t child, struct resource *vec, 1249 void *cookie) 1250{ 1251 struct psycho_softc *sc; 1252 struct psycho_dma_sync *pds; 1253 int error; 1254 1255 sc = device_get_softc(dev); 1256 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 1257 pds = cookie; 1258 error = bus_generic_teardown_intr(dev, child, vec, 1259 pds->pds_cookie); 1260 if (error == 0) 1261 free(pds, M_DEVBUF); 1262 return (error); 1263 } 1264 return (bus_generic_teardown_intr(dev, child, vec, cookie)); 1265} 1266 1267static int 1268psycho_describe_intr(device_t dev, device_t child, struct resource *vec, 1269 void *cookie, const char *descr) 1270{ 1271 struct psycho_softc *sc; 1272 1273 sc = device_get_softc(dev); 1274 if (sc->sc_mode == PSYCHO_MODE_SABRE) 1275 cookie = ((struct psycho_dma_sync *)cookie)->pds_cookie; 1276 return (bus_generic_describe_intr(dev, child, vec, cookie, descr)); 1277} 1278 1279static struct resource * 1280psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1281 u_long start, u_long end, u_long count, u_int flags) 1282{ 1283 struct psycho_softc *sc; 1284 struct resource *rv; 1285 struct rman *rm; 1286 bus_space_tag_t bt; 1287 bus_space_handle_t bh; 1288 int needactivate = flags & RF_ACTIVE; 1289 1290 flags &= ~RF_ACTIVE; 1291 1292 sc = device_get_softc(bus); 1293 if (type == SYS_RES_IRQ) { 1294 /* 1295 * XXX: Don't accept blank ranges for now, only single 1296 * interrupts. The other case should not happen with 1297 * the MI PCI code... 1298 * XXX: This may return a resource that is out of the 1299 * range that was specified. Is this correct...? 1300 */ 1301 if (start != end) 1302 panic("%s: XXX: interrupt range", __func__); 1303 start = end = INTMAP_VEC(sc->sc_ign, end); 1304 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, 1305 type, rid, start, end, count, flags)); 1306 } 1307 switch (type) { 1308 case SYS_RES_MEMORY: 1309 rm = &sc->sc_pci_mem_rman; 1310 bt = sc->sc_pci_memt; 1311 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1312 break; 1313 case SYS_RES_IOPORT: 1314 rm = &sc->sc_pci_io_rman; 1315 bt = sc->sc_pci_iot; 1316 bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1317 break; 1318 default: 1319 return (NULL); 1320 /* NOTREACHED */ 1321 } 1322 1323 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1324 if (rv == NULL) 1325 return (NULL); 1326 rman_set_rid(rv, *rid); 1327 bh += rman_get_start(rv); 1328 rman_set_bustag(rv, bt); 1329 rman_set_bushandle(rv, bh); 1330 1331 if (needactivate) { 1332 if (bus_activate_resource(child, type, *rid, rv)) { 1333 rman_release_resource(rv); 1334 return (NULL); 1335 } 1336 } 1337 return (rv); 1338} 1339 1340static int 1341psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1342 struct resource *r) 1343{ 1344 void *p; 1345 int error; 1346 1347 if (type == SYS_RES_IRQ) 1348 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1349 type, rid, r)); 1350 if (type == SYS_RES_MEMORY) { 1351 /* 1352 * Need to memory-map the device space, as some drivers 1353 * depend on the virtual address being set and usable. 1354 */ 1355 error = sparc64_bus_mem_map(rman_get_bustag(r), 1356 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1357 if (error != 0) 1358 return (error); 1359 rman_set_virtual(r, p); 1360 } 1361 return (rman_activate_resource(r)); 1362} 1363 1364static int 1365psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1366 struct resource *r) 1367{ 1368 1369 if (type == SYS_RES_IRQ) 1370 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1371 type, rid, r)); 1372 if (type == SYS_RES_MEMORY) { 1373 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1374 rman_set_virtual(r, NULL); 1375 } 1376 return (rman_deactivate_resource(r)); 1377} 1378 1379static int 1380psycho_release_resource(device_t bus, device_t child, int type, int rid, 1381 struct resource *r) 1382{ 1383 int error; 1384 1385 if (type == SYS_RES_IRQ) 1386 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1387 type, rid, r)); 1388 if (rman_get_flags(r) & RF_ACTIVE) { 1389 error = bus_deactivate_resource(child, type, rid, r); 1390 if (error) 1391 return (error); 1392 } 1393 return (rman_release_resource(r)); 1394} 1395 1396static bus_dma_tag_t 1397psycho_get_dma_tag(device_t bus, device_t child) 1398{ 1399 struct psycho_softc *sc; 1400 1401 sc = device_get_softc(bus); 1402 return (sc->sc_pci_dmat); 1403} 1404 1405static phandle_t 1406psycho_get_node(device_t bus, device_t dev) 1407{ 1408 struct psycho_softc *sc; 1409 1410 sc = device_get_softc(bus); 1411 /* We only have one child, the PCI bus, which needs our own node. */ 1412 return (sc->sc_node); 1413} 1414 1415static bus_space_tag_t 1416psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1417{ 1418 bus_space_tag_t bt; 1419 1420 bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1421 M_NOWAIT | M_ZERO); 1422 if (bt == NULL) 1423 panic("%s: out of memory", __func__); 1424 1425 bt->bst_cookie = sc; 1426 bt->bst_parent = rman_get_bustag(sc->sc_mem_res); 1427 bt->bst_type = type; 1428 return (bt); 1429} 1430