psycho.c revision 197164
1/*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/sparc64/pci/psycho.c 197164 2009-09-13 14:47:31Z marius $"); 35 36/* 37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+' 38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges. 39 */ 40 41#include "opt_ofw_pci.h" 42#include "opt_psycho.h" 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/bus.h> 47#include <sys/endian.h> 48#include <sys/kdb.h> 49#include <sys/kernel.h> 50#include <sys/lock.h> 51#include <sys/malloc.h> 52#include <sys/module.h> 53#include <sys/mutex.h> 54#include <sys/pcpu.h> 55#include <sys/reboot.h> 56#include <sys/rman.h> 57 58#include <dev/ofw/ofw_bus.h> 59#include <dev/ofw/ofw_pci.h> 60#include <dev/ofw/openfirm.h> 61 62#include <machine/bus.h> 63#include <machine/bus_common.h> 64#include <machine/bus_private.h> 65#include <machine/iommureg.h> 66#include <machine/iommuvar.h> 67#include <machine/resource.h> 68#include <machine/ver.h> 69 70#include <dev/pci/pcireg.h> 71#include <dev/pci/pcivar.h> 72 73#include <sparc64/pci/ofw_pci.h> 74#include <sparc64/pci/psychoreg.h> 75#include <sparc64/pci/psychovar.h> 76 77#include "pcib_if.h" 78 79static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *, 80 const char *); 81static const struct psycho_desc *psycho_get_desc(device_t); 82static void psycho_set_intr(struct psycho_softc *, u_int, bus_addr_t, 83 driver_filter_t, driver_intr_t); 84static int psycho_find_intrmap(struct psycho_softc *, u_int, bus_addr_t *, 85 bus_addr_t *, u_long *); 86static driver_filter_t psycho_dma_sync_stub; 87static void psycho_intr_enable(void *); 88static void psycho_intr_disable(void *); 89static void psycho_intr_assign(void *); 90static void psycho_intr_clear(void *); 91static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 92 93/* Interrupt handlers */ 94static driver_filter_t psycho_ue; 95static driver_filter_t psycho_ce; 96static driver_filter_t psycho_pci_bus; 97static driver_filter_t psycho_powerfail; 98static driver_intr_t psycho_overtemp; 99#ifdef PSYCHO_MAP_WAKEUP 100static driver_filter_t psycho_wakeup; 101#endif 102 103/* IOMMU support */ 104static void psycho_iommu_init(struct psycho_softc *, int, uint32_t); 105 106/* 107 * Methods 108 */ 109static device_probe_t psycho_probe; 110static device_attach_t psycho_attach; 111static bus_read_ivar_t psycho_read_ivar; 112static bus_setup_intr_t psycho_setup_intr; 113static bus_teardown_intr_t psycho_teardown_intr; 114static bus_alloc_resource_t psycho_alloc_resource; 115static bus_activate_resource_t psycho_activate_resource; 116static bus_deactivate_resource_t psycho_deactivate_resource; 117static bus_release_resource_t psycho_release_resource; 118static bus_get_dma_tag_t psycho_get_dma_tag; 119static pcib_maxslots_t psycho_maxslots; 120static pcib_read_config_t psycho_read_config; 121static pcib_write_config_t psycho_write_config; 122static pcib_route_interrupt_t psycho_route_interrupt; 123static ofw_bus_get_node_t psycho_get_node; 124 125static device_method_t psycho_methods[] = { 126 /* Device interface */ 127 DEVMETHOD(device_probe, psycho_probe), 128 DEVMETHOD(device_attach, psycho_attach), 129 DEVMETHOD(device_shutdown, bus_generic_shutdown), 130 DEVMETHOD(device_suspend, bus_generic_suspend), 131 DEVMETHOD(device_resume, bus_generic_resume), 132 133 /* Bus interface */ 134 DEVMETHOD(bus_print_child, bus_generic_print_child), 135 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 136 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 137 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 138 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 139 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 140 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 141 DEVMETHOD(bus_release_resource, psycho_release_resource), 142 DEVMETHOD(bus_get_dma_tag, psycho_get_dma_tag), 143 144 /* pcib interface */ 145 DEVMETHOD(pcib_maxslots, psycho_maxslots), 146 DEVMETHOD(pcib_read_config, psycho_read_config), 147 DEVMETHOD(pcib_write_config, psycho_write_config), 148 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 149 150 /* ofw_bus interface */ 151 DEVMETHOD(ofw_bus_get_node, psycho_get_node), 152 153 KOBJMETHOD_END 154}; 155 156static devclass_t psycho_devclass; 157 158DEFINE_CLASS_0(pcib, psycho_driver, psycho_methods, 159 sizeof(struct psycho_softc)); 160DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 161 162static SLIST_HEAD(, psycho_softc) psycho_softcs = 163 SLIST_HEAD_INITIALIZER(psycho_softcs); 164 165static const struct intr_controller psycho_ic = { 166 psycho_intr_enable, 167 psycho_intr_disable, 168 psycho_intr_assign, 169 psycho_intr_clear 170}; 171 172struct psycho_icarg { 173 struct psycho_softc *pica_sc; 174 bus_addr_t pica_map; 175 bus_addr_t pica_clr; 176}; 177 178struct psycho_dma_sync { 179 struct psycho_softc *pds_sc; 180 driver_filter_t *pds_handler; /* handler to call */ 181 void *pds_arg; /* argument for the handler */ 182 void *pds_cookie; /* parent bus int. cookie */ 183 device_t pds_ppb; /* farest PCI-PCI bridge */ 184 uint8_t pds_bus; /* bus of farest PCI device */ 185 uint8_t pds_slot; /* slot of farest PCI device */ 186 uint8_t pds_func; /* func. of farest PCI device */ 187}; 188 189#define PSYCHO_READ8(sc, off) \ 190 bus_read_8((sc)->sc_mem_res, (off)) 191#define PSYCHO_WRITE8(sc, off, v) \ 192 bus_write_8((sc)->sc_mem_res, (off), (v)) 193#define PCICTL_READ8(sc, off) \ 194 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 195#define PCICTL_WRITE8(sc, off, v) \ 196 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 197 198/* 199 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 200 * single PCI bus and does not have a streaming buffer. It often has an APB 201 * (advanced PCI bridge) connected to it, which was designed specifically for 202 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 203 * appears as two "Simba"'s underneath the Sabre. 204 * 205 * "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's 206 * basically the same as Sabre but without an APB underneath it. 207 * 208 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA bus 209 * and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while 210 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 211 * will usually find a "Psycho+" since I don't think the original "Psycho" 212 * ever shipped, and if it did it would be in the U30. 213 * 214 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are 215 * both part of the same IC, they only have a single register space. As such, 216 * they need to be configured together, even though the autoconfiguration will 217 * attach them separately. 218 * 219 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often 220 * as pci1 and pci2, although they have been implemented with other PCI bus 221 * numbers on some machines. 222 * 223 * On UltraII machines, there can be any number of "Psycho+" ICs, each 224 * providing two PCI buses. 225 */ 226 227struct psycho_desc { 228 const char *pd_string; 229 int pd_mode; 230 const char *pd_name; 231}; 232 233static const struct psycho_desc const psycho_compats[] = { 234 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 235 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" }, 236 { "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" }, 237 { NULL, 0, NULL } 238}; 239 240static const struct psycho_desc const psycho_models[] = { 241 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 242 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 243 { NULL, 0, NULL } 244}; 245 246static const struct psycho_desc * 247psycho_find_desc(const struct psycho_desc *table, const char *string) 248{ 249 const struct psycho_desc *desc; 250 251 if (string == NULL) 252 return (NULL); 253 for (desc = table; desc->pd_string != NULL; desc++) 254 if (strcmp(desc->pd_string, string) == 0) 255 return (desc); 256 return (NULL); 257} 258 259static const struct psycho_desc * 260psycho_get_desc(device_t dev) 261{ 262 const struct psycho_desc *rv; 263 264 rv = psycho_find_desc(psycho_models, ofw_bus_get_model(dev)); 265 if (rv == NULL) 266 rv = psycho_find_desc(psycho_compats, ofw_bus_get_compat(dev)); 267 return (rv); 268} 269 270static int 271psycho_probe(device_t dev) 272{ 273 const char *dtype; 274 275 dtype = ofw_bus_get_type(dev); 276 if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 && 277 psycho_get_desc(dev) != NULL) { 278 device_set_desc(dev, "U2P UPA-PCI bridge"); 279 return (0); 280 } 281 return (ENXIO); 282} 283 284static int 285psycho_attach(device_t dev) 286{ 287 char name[sizeof("pci108e,1000")]; 288 struct psycho_icarg *pica; 289 struct psycho_softc *asc, *sc, *osc; 290 struct ofw_pci_ranges *range; 291 const struct psycho_desc *desc; 292 bus_addr_t intrclr, intrmap; 293 uint64_t csr, dr; 294 phandle_t child, node; 295 uint32_t dvmabase, prop, prop_array[2]; 296 int32_t rev; 297 u_int rerun, ver; 298 int i, n; 299 300 node = ofw_bus_get_node(dev); 301 sc = device_get_softc(dev); 302 desc = psycho_get_desc(dev); 303 304 sc->sc_node = node; 305 sc->sc_dev = dev; 306 sc->sc_mode = desc->pd_mode; 307 308 /* 309 * The Psycho gets three register banks: 310 * (0) per-PBM configuration and status registers 311 * (1) per-PBM PCI configuration space, containing only the 312 * PBM 256-byte PCI header 313 * (2) the shared Psycho configuration registers 314 */ 315 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 316 i = 2; 317 sc->sc_pcictl = 318 bus_get_resource_start(dev, SYS_RES_MEMORY, 0) - 319 bus_get_resource_start(dev, SYS_RES_MEMORY, 2); 320 switch (sc->sc_pcictl) { 321 case PSR_PCICTL0: 322 sc->sc_half = 0; 323 break; 324 case PSR_PCICTL1: 325 sc->sc_half = 1; 326 break; 327 default: 328 panic("%s: bogus PCI control register location", 329 __func__); 330 /* NOTREACHED */ 331 } 332 } else { 333 i = 0; 334 sc->sc_pcictl = PSR_PCICTL0; 335 sc->sc_half = 0; 336 } 337 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i, 338 (sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) | 339 RF_ACTIVE); 340 if (sc->sc_mem_res == NULL) 341 panic("%s: could not allocate registers", __func__); 342 343 /* 344 * Match other Psychos that are already configured against 345 * the base physical address. This will be the same for a 346 * pair of devices that share register space. 347 */ 348 osc = NULL; 349 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 350 if (rman_get_start(asc->sc_mem_res) == 351 rman_get_start(sc->sc_mem_res)) { 352 /* Found partner. */ 353 osc = asc; 354 break; 355 } 356 } 357 if (osc == NULL) { 358 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 359 M_NOWAIT | M_ZERO); 360 if (sc->sc_mtx == NULL) 361 panic("%s: could not malloc mutex", __func__); 362 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 363 } else { 364 if (sc->sc_mode != PSYCHO_MODE_PSYCHO) 365 panic("%s: no partner expected", __func__); 366 if (mtx_initialized(osc->sc_mtx) == 0) 367 panic("%s: mutex not initialized", __func__); 368 sc->sc_mtx = osc->sc_mtx; 369 } 370 371 csr = PSYCHO_READ8(sc, PSR_CS); 372 ver = PSYCHO_GCSR_VERS(csr); 373 sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */ 374 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 375 sc->sc_ign = PSYCHO_GCSR_IGN(csr); 376 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 377 prop = 33000000; 378 379 device_printf(dev, 380 "%s, impl %d, version %d, IGN %#x, bus %c, %dMHz\n", 381 desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign, 382 'A' + sc->sc_half, prop / 1000 / 1000); 383 384 /* Set up the PCI control and PCI diagnostic registers. */ 385 386 /* 387 * Revision 0 EBus bridges have a bug which prevents them from 388 * working when bus parking is enabled. 389 */ 390 rev = -1; 391 csr = PCICTL_READ8(sc, PCR_CS); 392 csr &= ~PCICTL_ARB_PARK; 393 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 394 if (OF_getprop(child, "name", name, sizeof(name)) == -1) 395 continue; 396 if ((strcmp(name, "ebus") == 0 || 397 strcmp(name, "pci108e,1000") == 0) && 398 OF_getprop(child, "revision-id", &rev, sizeof(rev)) > 0 && 399 rev == 0) 400 break; 401 } 402 if (rev != 0 && OF_getproplen(node, "no-bus-parking") < 0) 403 csr |= PCICTL_ARB_PARK; 404 405 /* Workarounds for version specific bugs. */ 406 dr = PCICTL_READ8(sc, PCR_DIAG); 407 switch (ver) { 408 case 0: 409 dr |= DIAG_RTRY_DIS; 410 dr &= ~DIAG_DWSYNC_DIS; 411 rerun = 0; 412 break; 413 case 1: 414 csr &= ~PCICTL_ARB_PARK; 415 dr |= DIAG_RTRY_DIS | DIAG_DWSYNC_DIS; 416 rerun = 0; 417 break; 418 default: 419 dr |= DIAG_DWSYNC_DIS; 420 dr &= ~DIAG_RTRY_DIS; 421 rerun = 1; 422 break; 423 } 424 425 csr |= PCICTL_ERRINTEN | PCICTL_ARB_4; 426 csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN); 427#ifdef PSYCHO_DEBUG 428 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 429 (unsigned long long)PCICTL_READ8(sc, PCR_CS), 430 (unsigned long long)csr); 431#endif 432 PCICTL_WRITE8(sc, PCR_CS, csr); 433 434 dr &= ~DIAG_ISYNC_DIS; 435#ifdef PSYCHO_DEBUG 436 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 437 (unsigned long long)PCICTL_READ8(sc, PCR_DIAG), 438 (unsigned long long)dr); 439#endif 440 PCICTL_WRITE8(sc, PCR_DIAG, dr); 441 442 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 443 /* Use the PROM preset for now. */ 444 csr = PCICTL_READ8(sc, PCR_TAS); 445 if (csr == 0) 446 panic("%s: Hummingbird/Sabre TAS not initialized.", 447 __func__); 448 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT; 449 } else 450 dvmabase = -1; 451 452 /* Initialize memory and I/O rmans. */ 453 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 454 sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports"; 455 if (rman_init(&sc->sc_pci_io_rman) != 0 || 456 rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0) 457 panic("%s: failed to set up I/O rman", __func__); 458 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 459 sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory"; 460 if (rman_init(&sc->sc_pci_mem_rman) != 0 || 461 rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 462 panic("%s: failed to set up memory rman", __func__); 463 464 n = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range); 465 /* 466 * Make sure that the expected ranges are present. The 467 * OFW_PCI_CS_MEM64 one is not currently used though. 468 */ 469 if (n != PSYCHO_NRANGE) 470 panic("%s: unsupported number of ranges", __func__); 471 /* 472 * Find the addresses of the various bus spaces. 473 * There should not be multiple ones of one kind. 474 * The physical start addresses of the ranges are the configuration, 475 * memory and I/O handles. 476 */ 477 for (n = 0; n < PSYCHO_NRANGE; n++) { 478 i = OFW_PCI_RANGE_CS(&range[n]); 479 if (sc->sc_pci_bh[i] != 0) 480 panic("%s: duplicate range for space %d", __func__, i); 481 sc->sc_pci_bh[i] = OFW_PCI_RANGE_PHYS(&range[n]); 482 } 483 free(range, M_OFWPROP); 484 485 /* Register the softc, this is needed for paired Psychos. */ 486 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 487 488 /* 489 * If we're a Hummingbird/Sabre or the first of a pair of Psychos 490 * to arrive here, do the interrupt setup and start up the IOMMU. 491 */ 492 if (osc == NULL) { 493 /* 494 * Hunt through all the interrupt mapping regs and register 495 * our interrupt controller for the corresponding interrupt 496 * vectors. We do this early in order to be able to catch 497 * stray interrupts. 498 */ 499 for (n = 0; n <= PSYCHO_MAX_INO; n++) { 500 if (psycho_find_intrmap(sc, n, &intrmap, &intrclr, 501 NULL) == 0) 502 continue; 503 pica = malloc(sizeof(*pica), M_DEVBUF, M_NOWAIT); 504 if (pica == NULL) 505 panic("%s: could not allocate interrupt " 506 "controller argument", __func__); 507 pica->pica_sc = sc; 508 pica->pica_map = intrmap; 509 pica->pica_clr = intrclr; 510#ifdef PSYCHO_DEBUG 511 /* 512 * Enable all interrupts and clear all interrupt 513 * states. This aids the debugging of interrupt 514 * routing problems. 515 */ 516 device_printf(dev, 517 "intr map (INO %d, %s) %#lx: %#lx, clr: %#lx\n", 518 n, intrmap <= PSR_PCIB3_INT_MAP ? "PCI" : "OBIO", 519 (u_long)intrmap, (u_long)PSYCHO_READ8(sc, intrmap), 520 (u_long)intrclr); 521 PSYCHO_WRITE8(sc, intrmap, INTMAP_VEC(sc->sc_ign, n)); 522 PSYCHO_WRITE8(sc, intrclr, 0); 523 PSYCHO_WRITE8(sc, intrmap, 524 INTMAP_ENABLE(INTMAP_VEC(sc->sc_ign, n), 525 PCPU_GET(mid))); 526#endif 527 i = intr_controller_register(INTMAP_VEC(sc->sc_ign, n), 528 &psycho_ic, pica); 529 if (i != 0) 530 device_printf(dev, "could not register " 531 "interrupt controller for INO %d (%d)\n", 532 n, i); 533 } 534 535 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 536 sparc64_counter_init(device_get_nameunit(dev), 537 rman_get_bustag(sc->sc_mem_res), 538 rman_get_bushandle(sc->sc_mem_res), PSR_TC0); 539 540 /* 541 * Set up IOMMU and PCI configuration if we're the first 542 * of a pair of Psychos to arrive here or a Hummingbird 543 * or Sabre. 544 * 545 * We should calculate a TSB size based on amount of RAM 546 * and number of bus controllers and number and type of 547 * child devices. 548 * 549 * For the moment, 32KB should be more than enough. 550 */ 551 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 552 M_NOWAIT | M_ZERO); 553 if (sc->sc_is == NULL) 554 panic("%s: malloc iommu_state failed", __func__); 555 if (sc->sc_mode == PSYCHO_MODE_SABRE) 556 sc->sc_is->is_pmaxaddr = 557 IOMMU_MAXADDR(SABRE_IOMMU_BITS); 558 else 559 sc->sc_is->is_pmaxaddr = 560 IOMMU_MAXADDR(PSYCHO_IOMMU_BITS); 561 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = 0; 562 if (OF_getproplen(node, "no-streaming-cache") < 0) 563 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 564 sc->sc_is->is_flags |= (rerun != 1) ? IOMMU_RERUN_DISABLE : 0; 565 psycho_iommu_init(sc, 3, dvmabase); 566 } else { 567 /* Just copy IOMMU state, config tag and address. */ 568 sc->sc_is = osc->sc_is; 569 if (OF_getproplen(node, "no-streaming-cache") < 0) 570 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 571 iommu_reset(sc->sc_is); 572 } 573 574 /* Allocate our tags. */ 575 sc->sc_pci_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 576 sc->sc_pci_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 577 sc->sc_pci_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 578 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 579 sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr, 580 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0) 581 panic("%s: bus_dma_tag_create failed", __func__); 582 /* Customize the tag. */ 583 sc->sc_pci_dmat->dt_cookie = sc->sc_is; 584 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 585 586 n = OF_getprop(node, "bus-range", (void *)prop_array, 587 sizeof(prop_array)); 588 if (n == -1) 589 panic("%s: could not get bus-range", __func__); 590 if (n != sizeof(prop_array)) 591 panic("%s: broken bus-range (%d)", __func__, n); 592 if (bootverbose) 593 device_printf(dev, "bus range %u to %u; PCI bus %d\n", 594 prop_array[0], prop_array[1], prop_array[0]); 595 sc->sc_pci_secbus = prop_array[0]; 596 597 /* Clear any pending PCI error bits. */ 598 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, 599 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 600 PCS_DEVICE, PCS_FUNC, PCIR_STATUS, 2), 2); 601 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS)); 602 PCICTL_WRITE8(sc, PCR_AFS, PCICTL_READ8(sc, PCR_AFS)); 603 604 if (osc == NULL) { 605 /* 606 * Establish handlers for interesting interrupts... 607 * 608 * XXX We need to remember these and remove this to support 609 * hotplug on the UPA/FHC bus. 610 * 611 * XXX Not all controllers have these, but installing them 612 * is better than trying to sort through this mess. 613 */ 614 psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL); 615 psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL); 616#ifdef DEBUGGER_ON_POWERFAIL 617 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, psycho_powerfail, 618 NULL); 619#else 620 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL, 621 (driver_intr_t *)psycho_powerfail); 622#endif 623 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 624 /* 625 * Hummingbirds/Sabres do not have the following two 626 * interrupts. 627 */ 628 629 /* 630 * The spare hardware interrupt is used for the 631 * over-temperature interrupt. 632 */ 633 psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP, 634 NULL, psycho_overtemp); 635#ifdef PSYCHO_MAP_WAKEUP 636 /* 637 * psycho_wakeup() doesn't do anything useful right 638 * now. 639 */ 640 psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP, 641 psycho_wakeup, NULL); 642#endif /* PSYCHO_MAP_WAKEUP */ 643 } 644 } 645 /* 646 * Register a PCI bus error interrupt handler according to which 647 * half this is. Hummingbird/Sabre don't have a PCI bus B error 648 * interrupt but they are also only used for PCI bus A. 649 */ 650 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP : 651 PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL); 652 653 /* 654 * Set the latency timer register as this isn't always done by the 655 * firmware. 656 */ 657 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, 658 PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 659 660 for (n = PCIR_VENDOR; n < PCIR_STATUS; n += sizeof(uint16_t)) 661 le16enc(&sc->sc_pci_hpbcfg[n], bus_space_read_2( 662 sc->sc_pci_cfgt, sc->sc_pci_bh[OFW_PCI_CS_CONFIG], 663 PSYCHO_CONF_OFF(sc->sc_pci_secbus, PCS_DEVICE, 664 PCS_FUNC, n))); 665 for (n = PCIR_REVID; n <= PCIR_BIST; n += sizeof(uint8_t)) 666 sc->sc_pci_hpbcfg[n] = bus_space_read_1(sc->sc_pci_cfgt, 667 sc->sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF( 668 sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, n)); 669 670 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 671 /* 672 * On E250 the interrupt map entry for the EBus bridge is wrong, 673 * causing incorrect interrupts to be assigned to some devices on 674 * the EBus. Work around it by changing our copy of the interrupt 675 * map mask to perform a full comparison of the INO. That way 676 * the interrupt map entry for the EBus bridge won't match at all 677 * and the INOs specified in the "interrupts" properties of the 678 * EBus devices will be used directly instead. 679 */ 680 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 && 681 sc->sc_pci_iinfo.opi_imapmsk != NULL) 682 *(ofw_pci_intr_t *)(&sc->sc_pci_iinfo.opi_imapmsk[ 683 sc->sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK; 684 685 device_add_child(dev, "pci", -1); 686 return (bus_generic_attach(dev)); 687} 688 689static void 690psycho_set_intr(struct psycho_softc *sc, u_int index, bus_addr_t intrmap, 691 driver_filter_t filt, driver_intr_t intr) 692{ 693 u_long vec; 694 int rid; 695 696 rid = index; 697 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ, 698 &rid, RF_ACTIVE); 699 if (sc->sc_irq_res[index] == NULL && intrmap >= PSR_POWER_INT_MAP) { 700 /* 701 * These interrupts aren't mandatory and not available 702 * with all controllers (not even Psychos). 703 */ 704 return; 705 } 706 if (sc->sc_irq_res[index] == NULL || 707 INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) != sc->sc_ign || 708 INTVEC(PSYCHO_READ8(sc, intrmap)) != vec || 709 intr_vectors[vec].iv_ic != &psycho_ic || 710 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 711 INTR_TYPE_MISC | INTR_FAST, filt, intr, sc, 712 &sc->sc_ihand[index]) != 0) 713 panic("%s: failed to set up interrupt %d", __func__, index); 714} 715 716static int 717psycho_find_intrmap(struct psycho_softc *sc, u_int ino, bus_addr_t *intrmapptr, 718 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 719{ 720 bus_addr_t intrclr, intrmap; 721 uint64_t diag; 722 int found; 723 724 /* 725 * XXX we only compare INOs rather than INRs since the firmware may 726 * not provide the IGN and the IGN is constant for all devices on 727 * that PCI controller. 728 * This could cause problems for the FFB/external interrupt which 729 * has a full vector that can be set arbitrarily. 730 */ 731 732 if (ino > PSYCHO_MAX_INO) { 733 device_printf(sc->sc_dev, "out of range INO %d requested\n", 734 ino); 735 return (0); 736 } 737 738 found = 0; 739 /* Hunt through OBIO first. */ 740 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 741 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 742 intrmap <= PSR_PWRMGT_INT_MAP; intrmap += 8, intrclr += 8, 743 diag >>= 2) { 744 if (sc->sc_mode == PSYCHO_MODE_SABRE && 745 (intrmap == PSR_TIMER0_INT_MAP || 746 intrmap == PSR_TIMER1_INT_MAP || 747 intrmap == PSR_PCIBERR_INT_MAP || 748 intrmap == PSR_PWRMGT_INT_MAP)) 749 continue; 750 if (INTINO(PSYCHO_READ8(sc, intrmap)) == ino) { 751 diag &= 2; 752 found = 1; 753 break; 754 } 755 } 756 757 if (!found) { 758 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 759 /* Now do PCI interrupts. */ 760 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 761 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 762 diag >>= 8) { 763 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 764 (intrmap == PSR_PCIA2_INT_MAP || 765 intrmap == PSR_PCIA3_INT_MAP)) 766 continue; 767 if (((PSYCHO_READ8(sc, intrmap) ^ ino) & 0x3c) == 0) { 768 intrclr += 8 * (ino & 3); 769 diag = (diag >> ((ino & 3) * 2)) & 2; 770 found = 1; 771 break; 772 } 773 } 774 } 775 if (intrmapptr != NULL) 776 *intrmapptr = intrmap; 777 if (intrclrptr != NULL) 778 *intrclrptr = intrclr; 779 if (intrdiagptr != NULL) 780 *intrdiagptr = diag; 781 return (found); 782} 783 784/* 785 * Interrupt handlers 786 */ 787static int 788psycho_ue(void *arg) 789{ 790 struct psycho_softc *sc = arg; 791 uint64_t afar, afsr; 792 793 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 794 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 795 /* 796 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 797 * the AFAR to be set to the physical address of the TTE entry that 798 * was invalid/write protected. Call into the IOMMU code to have 799 * them decoded to virtual I/O addresses. 800 */ 801 if ((afsr & UEAFSR_P_DTE) != 0) 802 iommu_decode_fault(sc->sc_is, afar); 803 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx", 804 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 805 return (FILTER_HANDLED); 806} 807 808static int 809psycho_ce(void *arg) 810{ 811 struct psycho_softc *sc = arg; 812 uint64_t afar, afsr; 813 814 mtx_lock_spin(sc->sc_mtx); 815 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 816 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 817 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx " 818 "AFSR %#lx\n", (u_long)afar, (u_long)afsr); 819 /* Clear the error bits that we caught. */ 820 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr); 821 mtx_unlock_spin(sc->sc_mtx); 822 return (FILTER_HANDLED); 823} 824 825static int 826psycho_pci_bus(void *arg) 827{ 828 struct psycho_softc *sc = arg; 829 uint64_t afar, afsr; 830 831 afar = PCICTL_READ8(sc, PCR_AFA); 832 afsr = PCICTL_READ8(sc, PCR_AFS); 833 panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx", 834 device_get_name(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar, 835 (u_long)afsr); 836 return (FILTER_HANDLED); 837} 838 839static int 840psycho_powerfail(void *arg) 841{ 842#ifdef DEBUGGER_ON_POWERFAIL 843 struct psycho_softc *sc = arg; 844 845 kdb_enter(KDB_WHY_POWERFAIL, "powerfail"); 846#else 847 static int shutdown; 848 849 /* As the interrupt is cleared we may be called multiple times. */ 850 if (shutdown != 0) 851 return (FILTER_HANDLED); 852 shutdown++; 853 printf("Power Failure Detected: Shutting down NOW.\n"); 854 shutdown_nice(0); 855#endif 856 return (FILTER_HANDLED); 857} 858 859static void 860psycho_overtemp(void *arg) 861{ 862 static int shutdown; 863 864 /* As the interrupt is cleared we may be called multiple times. */ 865 if (shutdown != 0) 866 return; 867 shutdown++; 868 printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n"); 869 shutdown_nice(RB_POWEROFF); 870} 871 872#ifdef PSYCHO_MAP_WAKEUP 873static int 874psycho_wakeup(void *arg) 875{ 876 struct psycho_softc *sc = arg; 877 878 /* Gee, we don't really have a framework to deal with this properly. */ 879 device_printf(sc->sc_dev, "power management wakeup\n"); 880 return (FILTER_HANDLED); 881} 882#endif /* PSYCHO_MAP_WAKEUP */ 883 884static void 885psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase) 886{ 887 struct iommu_state *is = sc->sc_is; 888 889 /* Punch in our copies. */ 890 is->is_bustag = rman_get_bustag(sc->sc_mem_res); 891 is->is_bushandle = rman_get_bushandle(sc->sc_mem_res); 892 is->is_iommu = PSR_IOMMU; 893 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 894 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 895 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 896 is->is_dva = PSR_IOMMU_SVADIAG; 897 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 898 899 iommu_init(device_get_nameunit(sc->sc_dev), is, tsbsize, dvmabase, 0); 900} 901 902static int 903psycho_maxslots(device_t dev) 904{ 905 906 /* XXX: is this correct? */ 907 return (PCI_SLOTMAX); 908} 909 910static uint32_t 911psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 912 int width) 913{ 914 struct psycho_softc *sc; 915 bus_space_handle_t bh; 916 u_long offset = 0; 917 uint8_t byte; 918 uint16_t shrt; 919 uint32_t r, wrd; 920 int i; 921 922 sc = device_get_softc(dev); 923 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 924 925 /* 926 * The Hummingbird and Sabre bridges are picky in that they 927 * only allow their config space to be accessed using the 928 * "native" width of the respective register being accessed 929 * and return semi-random other content of their config space 930 * otherwise. Given that the PCI specs don't say anything 931 * about such a (unusual) limitation and lots of stuff expects 932 * to be able to access the contents of the config space at 933 * any width we allow just that. We do this by using a copy 934 * of the header of the bridge (the rest is all zero anyway) 935 * read during attach (expect for PCIR_STATUS) in order to 936 * simplify things. 937 * The Psycho bridges contain a dupe of their header at 0x80 938 * which we nullify that way also. 939 */ 940 if (bus == sc->sc_pci_secbus && slot == PCS_DEVICE && 941 func == PCS_FUNC) { 942 if (offset % width != 0) 943 return (-1); 944 945 if (reg >= sizeof(sc->sc_pci_hpbcfg)) 946 return (0); 947 948 if ((reg < PCIR_STATUS && reg + width > PCIR_STATUS) || 949 reg == PCIR_STATUS || reg == PCIR_STATUS + 1) 950 le16enc(&sc->sc_pci_hpbcfg[PCIR_STATUS], 951 bus_space_read_2(sc->sc_pci_cfgt, bh, 952 PSYCHO_CONF_OFF(sc->sc_pci_secbus, 953 PCS_DEVICE, PCS_FUNC, PCIR_STATUS))); 954 955 switch (width) { 956 case 1: 957 return (sc->sc_pci_hpbcfg[reg]); 958 case 2: 959 return (le16dec(&sc->sc_pci_hpbcfg[reg])); 960 case 4: 961 return (le32dec(&sc->sc_pci_hpbcfg[reg])); 962 } 963 } 964 965 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 966 switch (width) { 967 case 1: 968 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 969 r = byte; 970 break; 971 case 2: 972 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 973 r = shrt; 974 break; 975 case 4: 976 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 977 r = wrd; 978 break; 979 default: 980 panic("%s: bad width", __func__); 981 /* NOTREACHED */ 982 } 983 984 if (i) { 985#ifdef PSYCHO_DEBUG 986 printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 987 __func__, bus, slot, func, reg); 988#endif 989 r = -1; 990 } 991 return (r); 992} 993 994static void 995psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 996 uint32_t val, int width) 997{ 998 struct psycho_softc *sc; 999 bus_space_handle_t bh; 1000 u_long offset = 0; 1001 1002 sc = device_get_softc(dev); 1003 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 1004 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1005 switch (width) { 1006 case 1: 1007 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 1008 break; 1009 case 2: 1010 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 1011 break; 1012 case 4: 1013 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 1014 break; 1015 default: 1016 panic("%s: bad width", __func__); 1017 /* NOTREACHED */ 1018 } 1019} 1020 1021static int 1022psycho_route_interrupt(device_t bridge, device_t dev, int pin) 1023{ 1024 struct psycho_softc *sc; 1025 struct ofw_pci_register reg; 1026 bus_addr_t intrmap; 1027 ofw_pci_intr_t pintr, mintr; 1028 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 1029 1030 sc = device_get_softc(bridge); 1031 pintr = pin; 1032 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, 1033 sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) 1034 return (mintr); 1035 /* 1036 * If this is outside of the range for an intpin, it's likely a full 1037 * INO, and no mapping is required at all; this happens on the U30, 1038 * where there's no interrupt map at the Psycho node. Fortunately, 1039 * there seem to be no INOs in the intpin range on this boxen, so 1040 * this easy heuristics will do. 1041 */ 1042 if (pin > 4) 1043 return (pin); 1044 /* 1045 * Guess the INO; we always assume that this is a non-OBIO 1046 * device, and that pin is a "real" intpin number. Determine 1047 * the mapping register to be used by the slot number. 1048 * We only need to do this on E450s, it seems; here, the slot numbers 1049 * for bus A are one-based, while those for bus B seemingly have an 1050 * offset of 2 (hence the factor of 3 below). 1051 */ 1052 intrmap = PSR_PCIA0_INT_MAP + 1053 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half); 1054 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1; 1055 device_printf(bridge, "guessing interrupt %d for device %d.%d pin %d\n", 1056 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin); 1057 return (mintr); 1058} 1059 1060static int 1061psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1062{ 1063 struct psycho_softc *sc; 1064 1065 sc = device_get_softc(dev); 1066 switch (which) { 1067 case PCIB_IVAR_DOMAIN: 1068 *result = device_get_unit(dev); 1069 return (0); 1070 case PCIB_IVAR_BUS: 1071 *result = sc->sc_pci_secbus; 1072 return (0); 1073 } 1074 return (ENOENT); 1075} 1076 1077static int 1078psycho_dma_sync_stub(void *arg) 1079{ 1080 struct psycho_dma_sync *pds = arg; 1081 1082 (void)PCIB_READ_CONFIG(pds->pds_ppb, pds->pds_bus, pds->pds_slot, 1083 pds->pds_func, PCIR_VENDOR, 2); 1084 (void)PSYCHO_READ8(pds->pds_sc, PSR_DMA_WRITE_SYNC); 1085 return (pds->pds_handler(pds->pds_arg)); 1086} 1087 1088static void 1089psycho_intr_enable(void *arg) 1090{ 1091 struct intr_vector *iv = arg; 1092 struct psycho_icarg *pica = iv->iv_icarg; 1093 1094 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, 1095 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1096} 1097 1098static void 1099psycho_intr_disable(void *arg) 1100{ 1101 struct intr_vector *iv = arg; 1102 struct psycho_icarg *pica = iv->iv_icarg; 1103 1104 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, iv->iv_vec); 1105} 1106 1107static void 1108psycho_intr_assign(void *arg) 1109{ 1110 struct intr_vector *iv = arg; 1111 struct psycho_icarg *pica = iv->iv_icarg; 1112 1113 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, INTMAP_TID( 1114 PSYCHO_READ8(pica->pica_sc, pica->pica_map), iv->iv_mid)); 1115} 1116 1117static void 1118psycho_intr_clear(void *arg) 1119{ 1120 struct intr_vector *iv = arg; 1121 struct psycho_icarg *pica = iv->iv_icarg; 1122 1123 PSYCHO_WRITE8(pica->pica_sc, pica->pica_clr, 0); 1124} 1125 1126static int 1127psycho_setup_intr(device_t dev, device_t child, struct resource *ires, 1128 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1129 void **cookiep) 1130{ 1131 struct { 1132 int apb:1; 1133 int ppb:1; 1134 } found; 1135 devclass_t pci_devclass; 1136 device_t cdev, pdev, pcidev; 1137 struct psycho_softc *sc; 1138 struct psycho_dma_sync *pds; 1139 u_long vec; 1140 int error; 1141 1142 sc = device_get_softc(dev); 1143 /* 1144 * Make sure the vector is fully specified and we registered 1145 * our interrupt controller for it. 1146 */ 1147 vec = rman_get_start(ires); 1148 if (INTIGN(vec) != sc->sc_ign || 1149 intr_vectors[vec].iv_ic != &psycho_ic) { 1150 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1151 return (EINVAL); 1152 } 1153 1154 /* 1155 * The Sabre-APB-combination does not automatically flush DMA 1156 * write data for devices behind additional PCI-PCI bridges 1157 * underneath the APB PCI-PCI bridge. The procedure for a 1158 * manual flush is to do a PIO read on the far side of the 1159 * farthest PCI-PCI bridge followed by a read of the PCI DMA 1160 * write sync register of the Sabre. 1161 */ 1162 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 1163 pds = malloc(sizeof(*pds), M_DEVBUF, M_NOWAIT | M_ZERO); 1164 if (pds == NULL) 1165 return (ENOMEM); 1166 pcidev = NULL; 1167 found.apb = found.ppb = 0; 1168 pci_devclass = devclass_find("pci"); 1169 for (cdev = child; cdev != dev; cdev = pdev) { 1170 pdev = device_get_parent(cdev); 1171 if (pcidev == NULL) { 1172 if (device_get_devclass(pdev) != pci_devclass) 1173 continue; 1174 pcidev = cdev; 1175 continue; 1176 } 1177 /* 1178 * NB: APB would also match as PCI-PCI bridges. 1179 */ 1180 if (pci_get_vendor(cdev) == 0x108e && 1181 pci_get_device(cdev) == 0x5000) { 1182 found.apb = 1; 1183 break; 1184 } 1185 if (pci_get_class(cdev) == PCIC_BRIDGE && 1186 pci_get_subclass(cdev) == PCIS_BRIDGE_PCI) 1187 found.ppb = 1; 1188 } 1189 if (found.apb && found.ppb && pcidev != NULL) { 1190 pds->pds_sc = sc; 1191 pds->pds_arg = arg; 1192 pds->pds_ppb = 1193 device_get_parent(device_get_parent(pcidev)); 1194 pds->pds_bus = pci_get_bus(pcidev); 1195 pds->pds_slot = pci_get_slot(pcidev); 1196 pds->pds_func = pci_get_function(pcidev); 1197 if (bootverbose) 1198 device_printf(dev, "installed DMA sync " 1199 "wrapper for device %d.%d on bus %d\n", 1200 pds->pds_slot, pds->pds_func, 1201 pds->pds_bus); 1202 if (intr == NULL) { 1203 pds->pds_handler = filt; 1204 error = bus_generic_setup_intr(dev, child, 1205 ires, flags, psycho_dma_sync_stub, intr, 1206 pds, cookiep); 1207 } else { 1208 pds->pds_handler = (driver_filter_t *)intr; 1209 error = bus_generic_setup_intr(dev, child, 1210 ires, flags, filt, 1211 (driver_intr_t *)psycho_dma_sync_stub, 1212 pds, cookiep); 1213 } 1214 } else 1215 error = bus_generic_setup_intr(dev, child, ires, 1216 flags, filt, intr, arg, cookiep); 1217 if (error != 0) { 1218 free(pds, M_DEVBUF); 1219 return (error); 1220 } 1221 pds->pds_cookie = *cookiep; 1222 *cookiep = pds; 1223 return (error); 1224 } 1225 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1226 arg, cookiep)); 1227} 1228 1229static int 1230psycho_teardown_intr(device_t dev, device_t child, struct resource *vec, 1231 void *cookie) 1232{ 1233 struct psycho_softc *sc; 1234 struct psycho_dma_sync *pds; 1235 int error; 1236 1237 sc = device_get_softc(dev); 1238 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 1239 pds = cookie; 1240 error = bus_generic_teardown_intr(dev, child, vec, 1241 pds->pds_cookie); 1242 if (error == 0) 1243 free(pds, M_DEVBUF); 1244 return (error); 1245 } 1246 return (bus_generic_teardown_intr(dev, child, vec, cookie)); 1247} 1248 1249static struct resource * 1250psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1251 u_long start, u_long end, u_long count, u_int flags) 1252{ 1253 struct psycho_softc *sc; 1254 struct resource *rv; 1255 struct rman *rm; 1256 bus_space_tag_t bt; 1257 bus_space_handle_t bh; 1258 int needactivate = flags & RF_ACTIVE; 1259 1260 flags &= ~RF_ACTIVE; 1261 1262 sc = device_get_softc(bus); 1263 if (type == SYS_RES_IRQ) { 1264 /* 1265 * XXX: Don't accept blank ranges for now, only single 1266 * interrupts. The other case should not happen with 1267 * the MI PCI code... 1268 * XXX: This may return a resource that is out of the 1269 * range that was specified. Is this correct...? 1270 */ 1271 if (start != end) 1272 panic("%s: XXX: interrupt range", __func__); 1273 start = end = INTMAP_VEC(sc->sc_ign, end); 1274 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, 1275 rid, start, end, count, flags)); 1276 } 1277 switch (type) { 1278 case SYS_RES_MEMORY: 1279 rm = &sc->sc_pci_mem_rman; 1280 bt = sc->sc_pci_memt; 1281 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1282 break; 1283 case SYS_RES_IOPORT: 1284 rm = &sc->sc_pci_io_rman; 1285 bt = sc->sc_pci_iot; 1286 bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1287 break; 1288 default: 1289 return (NULL); 1290 /* NOTREACHED */ 1291 } 1292 1293 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1294 if (rv == NULL) 1295 return (NULL); 1296 rman_set_rid(rv, *rid); 1297 bh += rman_get_start(rv); 1298 rman_set_bustag(rv, bt); 1299 rman_set_bushandle(rv, bh); 1300 1301 if (needactivate) { 1302 if (bus_activate_resource(child, type, *rid, rv)) { 1303 rman_release_resource(rv); 1304 return (NULL); 1305 } 1306 } 1307 return (rv); 1308} 1309 1310static int 1311psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1312 struct resource *r) 1313{ 1314 void *p; 1315 int error; 1316 1317 if (type == SYS_RES_IRQ) 1318 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1319 type, rid, r)); 1320 if (type == SYS_RES_MEMORY) { 1321 /* 1322 * Need to memory-map the device space, as some drivers 1323 * depend on the virtual address being set and usable. 1324 */ 1325 error = sparc64_bus_mem_map(rman_get_bustag(r), 1326 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1327 if (error != 0) 1328 return (error); 1329 rman_set_virtual(r, p); 1330 } 1331 return (rman_activate_resource(r)); 1332} 1333 1334static int 1335psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1336 struct resource *r) 1337{ 1338 1339 if (type == SYS_RES_IRQ) 1340 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1341 type, rid, r)); 1342 if (type == SYS_RES_MEMORY) { 1343 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1344 rman_set_virtual(r, NULL); 1345 } 1346 return (rman_deactivate_resource(r)); 1347} 1348 1349static int 1350psycho_release_resource(device_t bus, device_t child, int type, int rid, 1351 struct resource *r) 1352{ 1353 int error; 1354 1355 if (type == SYS_RES_IRQ) 1356 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1357 type, rid, r)); 1358 if (rman_get_flags(r) & RF_ACTIVE) { 1359 error = bus_deactivate_resource(child, type, rid, r); 1360 if (error) 1361 return (error); 1362 } 1363 return (rman_release_resource(r)); 1364} 1365 1366static bus_dma_tag_t 1367psycho_get_dma_tag(device_t bus, device_t child) 1368{ 1369 struct psycho_softc *sc; 1370 1371 sc = device_get_softc(bus); 1372 return (sc->sc_pci_dmat); 1373} 1374 1375static phandle_t 1376psycho_get_node(device_t bus, device_t dev) 1377{ 1378 struct psycho_softc *sc; 1379 1380 sc = device_get_softc(bus); 1381 /* We only have one child, the PCI bus, which needs our own node. */ 1382 return (sc->sc_node); 1383} 1384 1385static bus_space_tag_t 1386psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1387{ 1388 bus_space_tag_t bt; 1389 1390 bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF, M_NOWAIT | M_ZERO); 1391 if (bt == NULL) 1392 panic("%s: out of memory", __func__); 1393 1394 bt->bst_cookie = sc; 1395 bt->bst_parent = rman_get_bustag(sc->sc_mem_res); 1396 bt->bst_type = type; 1397 return (bt); 1398} 1399