psycho.c revision 178443
1/*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/sparc64/pci/psycho.c 178443 2008-04-23 20:04:38Z marius $"); 35 36/* 37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+' 38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges. 39 */ 40 41#include "opt_ofw_pci.h" 42#include "opt_psycho.h" 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/bus.h> 47#include <sys/endian.h> 48#include <sys/kdb.h> 49#include <sys/kernel.h> 50#include <sys/lock.h> 51#include <sys/malloc.h> 52#include <sys/module.h> 53#include <sys/mutex.h> 54#include <sys/pcpu.h> 55#include <sys/reboot.h> 56#include <sys/rman.h> 57 58#include <dev/ofw/ofw_bus.h> 59#include <dev/ofw/ofw_pci.h> 60#include <dev/ofw/openfirm.h> 61 62#include <machine/bus.h> 63#include <machine/bus_common.h> 64#include <machine/bus_private.h> 65#include <machine/iommureg.h> 66#include <machine/iommuvar.h> 67#include <machine/ofw_bus.h> 68#include <machine/resource.h> 69#include <machine/ver.h> 70 71#include <dev/pci/pcireg.h> 72#include <dev/pci/pcivar.h> 73 74#include <sparc64/pci/ofw_pci.h> 75#include <sparc64/pci/psychoreg.h> 76#include <sparc64/pci/psychovar.h> 77 78#include "pcib_if.h" 79 80static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *, 81 const char *); 82static const struct psycho_desc *psycho_get_desc(device_t); 83static void psycho_set_intr(struct psycho_softc *, u_int, bus_addr_t, 84 driver_filter_t, driver_intr_t); 85static int psycho_find_intrmap(struct psycho_softc *, u_int, bus_addr_t *, 86 bus_addr_t *, u_long *); 87static driver_filter_t psycho_dmasync; 88static void psycho_intr_enable(void *); 89static void psycho_intr_disable(void *); 90static void psycho_intr_assign(void *); 91static void psycho_intr_clear(void *); 92static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 93 94/* Interrupt handlers */ 95static driver_filter_t psycho_ue; 96static driver_filter_t psycho_ce; 97static driver_filter_t psycho_pci_bus; 98static driver_filter_t psycho_powerfail; 99static driver_intr_t psycho_overtemp; 100#ifdef PSYCHO_MAP_WAKEUP 101static driver_filter_t psycho_wakeup; 102#endif 103 104/* IOMMU support */ 105static void psycho_iommu_init(struct psycho_softc *, int, uint32_t); 106 107/* 108 * Methods 109 */ 110static device_probe_t psycho_probe; 111static device_attach_t psycho_attach; 112static bus_read_ivar_t psycho_read_ivar; 113static bus_setup_intr_t psycho_setup_intr; 114static bus_teardown_intr_t psycho_teardown_intr; 115static bus_alloc_resource_t psycho_alloc_resource; 116static bus_activate_resource_t psycho_activate_resource; 117static bus_deactivate_resource_t psycho_deactivate_resource; 118static bus_release_resource_t psycho_release_resource; 119static bus_get_dma_tag_t psycho_get_dma_tag; 120static pcib_maxslots_t psycho_maxslots; 121static pcib_read_config_t psycho_read_config; 122static pcib_write_config_t psycho_write_config; 123static pcib_route_interrupt_t psycho_route_interrupt; 124static ofw_pci_intr_pending_t psycho_intr_pending; 125static ofw_bus_get_node_t psycho_get_node; 126 127static device_method_t psycho_methods[] = { 128 /* Device interface */ 129 DEVMETHOD(device_probe, psycho_probe), 130 DEVMETHOD(device_attach, psycho_attach), 131 DEVMETHOD(device_shutdown, bus_generic_shutdown), 132 DEVMETHOD(device_suspend, bus_generic_suspend), 133 DEVMETHOD(device_resume, bus_generic_resume), 134 135 /* Bus interface */ 136 DEVMETHOD(bus_print_child, bus_generic_print_child), 137 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 138 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 139 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 140 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 141 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 142 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 143 DEVMETHOD(bus_release_resource, psycho_release_resource), 144 DEVMETHOD(bus_get_dma_tag, psycho_get_dma_tag), 145 146 /* pcib interface */ 147 DEVMETHOD(pcib_maxslots, psycho_maxslots), 148 DEVMETHOD(pcib_read_config, psycho_read_config), 149 DEVMETHOD(pcib_write_config, psycho_write_config), 150 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 151 152 /* ofw_bus interface */ 153 DEVMETHOD(ofw_bus_get_node, psycho_get_node), 154 155 /* ofw_pci interface */ 156 DEVMETHOD(ofw_pci_intr_pending, psycho_intr_pending), 157 158 { 0, 0 } 159}; 160 161static devclass_t psycho_devclass; 162 163DEFINE_CLASS_0(pcib, psycho_driver, psycho_methods, 164 sizeof(struct psycho_softc)); 165DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 166 167static SLIST_HEAD(, psycho_softc) psycho_softcs = 168 SLIST_HEAD_INITIALIZER(psycho_softcs); 169 170static const struct intr_controller psycho_ic = { 171 psycho_intr_enable, 172 psycho_intr_disable, 173 psycho_intr_assign, 174 psycho_intr_clear 175}; 176 177struct psycho_icarg { 178 struct psycho_softc *pica_sc; 179 bus_addr_t pica_map; 180 bus_addr_t pica_clr; 181}; 182 183struct psycho_dmasync { 184 struct psycho_softc *pds_sc; 185 driver_filter_t *pds_handler; /* handler to call */ 186 void *pds_arg; /* argument for the handler */ 187 void *pds_cookie; /* parent bus int. cookie */ 188 device_t pds_ppb; /* farest PCI-PCI bridge */ 189 uint8_t pds_bus; /* bus of farest PCI device */ 190 uint8_t pds_slot; /* slot of farest PCI device */ 191 uint8_t pds_func; /* func. of farest PCI device */ 192}; 193 194#define PSYCHO_READ8(sc, off) \ 195 bus_read_8((sc)->sc_mem_res, (off)) 196#define PSYCHO_WRITE8(sc, off, v) \ 197 bus_write_8((sc)->sc_mem_res, (off), (v)) 198#define PCICTL_READ8(sc, off) \ 199 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 200#define PCICTL_WRITE8(sc, off, v) \ 201 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 202 203/* 204 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 205 * single PCI bus and does not have a streaming buffer. It often has an APB 206 * (advanced PCI bridge) connected to it, which was designed specifically for 207 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 208 * appears as two "Simba"'s underneath the Sabre. 209 * 210 * "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's 211 * basically the same as Sabre but without an APB underneath it. 212 * 213 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA bus 214 * and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while 215 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 216 * will usually find a "Psycho+" since I don't think the original "Psycho" 217 * ever shipped, and if it did it would be in the U30. 218 * 219 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are 220 * both part of the same IC, they only have a single register space. As such, 221 * they need to be configured together, even though the autoconfiguration will 222 * attach them separately. 223 * 224 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often 225 * as pci1 and pci2, although they have been implemented with other PCI bus 226 * numbers on some machines. 227 * 228 * On UltraII machines, there can be any number of "Psycho+" ICs, each 229 * providing two PCI buses. 230 */ 231 232#define OFW_PCI_TYPE "pci" 233 234struct psycho_desc { 235 const char *pd_string; 236 int pd_mode; 237 const char *pd_name; 238}; 239 240static const struct psycho_desc psycho_compats[] = { 241 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 242 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" }, 243 { "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" }, 244 { NULL, 0, NULL } 245}; 246 247static const struct psycho_desc psycho_models[] = { 248 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 249 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 250 { NULL, 0, NULL } 251}; 252 253static const struct psycho_desc * 254psycho_find_desc(const struct psycho_desc *table, const char *string) 255{ 256 const struct psycho_desc *desc; 257 258 if (string == NULL) 259 return (NULL); 260 for (desc = table; desc->pd_string != NULL; desc++) 261 if (strcmp(desc->pd_string, string) == 0) 262 return (desc); 263 return (NULL); 264} 265 266static const struct psycho_desc * 267psycho_get_desc(device_t dev) 268{ 269 const struct psycho_desc *rv; 270 271 rv = psycho_find_desc(psycho_models, ofw_bus_get_model(dev)); 272 if (rv == NULL) 273 rv = psycho_find_desc(psycho_compats, ofw_bus_get_compat(dev)); 274 return (rv); 275} 276 277static int 278psycho_probe(device_t dev) 279{ 280 const char *dtype; 281 282 dtype = ofw_bus_get_type(dev); 283 if (dtype != NULL && strcmp(dtype, OFW_PCI_TYPE) == 0 && 284 psycho_get_desc(dev) != NULL) { 285 device_set_desc(dev, "U2P UPA-PCI bridge"); 286 return (0); 287 } 288 289 return (ENXIO); 290} 291 292static int 293psycho_attach(device_t dev) 294{ 295 char name[sizeof("pci108e,1000")]; 296 struct psycho_icarg *pica; 297 struct psycho_softc *asc, *sc, *osc; 298 struct ofw_pci_ranges *range; 299 const struct psycho_desc *desc; 300 bus_addr_t intrclr, intrmap; 301 uint64_t csr, dr; 302 phandle_t child, node; 303 uint32_t dvmabase, prop_array[2]; 304 int32_t rev; 305 u_int ver; 306 int i, n, nrange, rid; 307 308 node = ofw_bus_get_node(dev); 309 sc = device_get_softc(dev); 310 desc = psycho_get_desc(dev); 311 312 sc->sc_node = node; 313 sc->sc_dev = dev; 314 sc->sc_mode = desc->pd_mode; 315 316 /* 317 * The Psycho gets three register banks: 318 * (0) per-PBM configuration and status registers 319 * (1) per-PBM PCI configuration space, containing only the 320 * PBM 256-byte PCI header 321 * (2) the shared Psycho configuration registers 322 */ 323 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 324 rid = 2; 325 sc->sc_pcictl = 326 bus_get_resource_start(dev, SYS_RES_MEMORY, 0) - 327 bus_get_resource_start(dev, SYS_RES_MEMORY, 2); 328 switch (sc->sc_pcictl) { 329 case PSR_PCICTL0: 330 sc->sc_half = 0; 331 break; 332 case PSR_PCICTL1: 333 sc->sc_half = 1; 334 break; 335 default: 336 panic("%s: bogus PCI control register location", 337 __func__); 338 } 339 } else { 340 rid = 0; 341 sc->sc_pcictl = PSR_PCICTL0; 342 sc->sc_half = 0; 343 } 344 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 345 (sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) | 346 RF_ACTIVE); 347 if (sc->sc_mem_res == NULL) 348 panic("%s: could not allocate registers", __func__); 349 350 /* 351 * Match other Psycho's that are already configured against 352 * the base physical address. This will be the same for a 353 * pair of devices that share register space. 354 */ 355 osc = NULL; 356 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 357 if (rman_get_start(asc->sc_mem_res) == 358 rman_get_start(sc->sc_mem_res)) { 359 /* Found partner. */ 360 osc = asc; 361 break; 362 } 363 } 364 if (osc == NULL) { 365 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 366 M_NOWAIT | M_ZERO); 367 if (sc->sc_mtx == NULL) 368 panic("%s: could not malloc mutex", __func__); 369 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 370 } else { 371 if (mtx_initialized(osc->sc_mtx) == 0) 372 panic("%s: mutex not initialized", __func__); 373 sc->sc_mtx = osc->sc_mtx; 374 } 375 376 /* Clear PCI AFSR. */ 377 PCICTL_WRITE8(sc, PCR_AFS, PCIAFSR_ERRMASK); 378 379 csr = PSYCHO_READ8(sc, PSR_CS); 380 ver = PSYCHO_GCSR_VERS(csr); 381 sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */ 382 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 383 sc->sc_ign = PSYCHO_GCSR_IGN(csr); 384 385 device_printf(dev, "%s, impl %d, version %d, IGN %#x, bus %c\n", 386 desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign, 387 'A' + sc->sc_half); 388 389 /* Set up the PCI control and PCI diagnostic registers. */ 390 391 /* 392 * Revision 0 EBus bridges have a bug which prevents them from 393 * working when bus parking is enabled. 394 */ 395 rev = -1; 396 csr = PCICTL_READ8(sc, PCR_CS); 397 csr &= ~PCICTL_ARB_PARK; 398 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 399 if (OF_getprop(child, "name", name, sizeof(name)) == -1) 400 continue; 401 if ((strcmp(name, "ebus") == 0 || 402 strcmp(name, "pci108e,1000") == 0) && 403 OF_getprop(child, "revision-id", &rev, sizeof(rev)) > 0 && 404 rev == 0) 405 break; 406 } 407 if (rev != 0 && OF_getproplen(node, "no-bus-parking") < 0) 408 csr |= PCICTL_ARB_PARK; 409 410 /* Workarounds for version specific bugs. */ 411 dr = PCICTL_READ8(sc, PCR_DIAG); 412 switch (ver) { 413 case 0: 414 dr |= DIAG_RTRY_DIS; 415 dr &= ~DIAG_DWSYNC_DIS; 416 /* XXX need to also disable rerun of the streaming buffers. */ 417 break; 418 case 1: 419 csr &= ~PCICTL_ARB_PARK; 420 dr |= DIAG_RTRY_DIS | DIAG_DWSYNC_DIS; 421 /* XXX need to also disable rerun of the streaming buffers. */ 422 break; 423 default: 424 dr |= DIAG_DWSYNC_DIS; 425 dr &= ~DIAG_RTRY_DIS; 426 break; 427 } 428 429 csr |= PCICTL_SERR | PCICTL_ERRINTEN | PCICTL_ARB_4; 430 csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN); 431#ifdef PSYCHO_DEBUG 432 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 433 (unsigned long long)PCICTL_READ8(sc, PCR_CS), 434 (unsigned long long)csr); 435#endif 436 PCICTL_WRITE8(sc, PCR_CS, csr); 437 438 dr &= ~DIAG_ISYNC_DIS; 439#ifdef PSYCHO_DEBUG 440 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 441 (unsigned long long)PCICTL_READ8(sc, PCR_DIAG), 442 (unsigned long long)dr); 443#endif 444 PCICTL_WRITE8(sc, PCR_DIAG, dr); 445 446 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 447 /* Use the PROM preset for now. */ 448 csr = PCICTL_READ8(sc, PCR_TAS); 449 if (csr == 0) 450 panic("%s: Hummingbird/Sabre TAS not initialized.", 451 __func__); 452 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT; 453 } else 454 dvmabase = -1; 455 456 /* Initialize memory and I/O rmans. */ 457 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 458 sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports"; 459 if (rman_init(&sc->sc_pci_io_rman) != 0 || 460 rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0) 461 panic("%s: failed to set up I/O rman", __func__); 462 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 463 sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory"; 464 if (rman_init(&sc->sc_pci_mem_rman) != 0 || 465 rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 466 panic("%s: failed to set up memory rman", __func__); 467 468 nrange = OF_getprop_alloc(node, "ranges", sizeof(*range), 469 (void **)&range); 470 /* 471 * Make sure that the expected ranges are present. The OFW_PCI_CS_MEM64 472 * one is not currently used though. 473 */ 474 if (nrange != PSYCHO_NRANGE) 475 panic("%s: unsupported number of ranges", __func__); 476 /* 477 * Find the addresses of the various bus spaces. 478 * There should not be multiple ones of one kind. 479 * The physical start addresses of the ranges are the configuration, 480 * memory and I/O handles. 481 */ 482 for (n = 0; n < PSYCHO_NRANGE; n++) { 483 i = OFW_PCI_RANGE_CS(&range[n]); 484 if (sc->sc_pci_bh[i] != 0) 485 panic("%s: duplicate range for space %d", __func__, i); 486 sc->sc_pci_bh[i] = OFW_PCI_RANGE_PHYS(&range[n]); 487 } 488 free(range, M_OFWPROP); 489 490 /* Register the softc, this is needed for paired Psychos. */ 491 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 492 493 /* 494 * If we're a Hummingbird/Sabre or the first of a pair of Psychos 495 * to arrive here, do the interrupt setup and start up the IOMMU. 496 */ 497 if (osc == NULL) { 498 /* 499 * Hunt through all the interrupt mapping regs and register 500 * our interrupt controller for the corresponding interrupt 501 * vectors. 502 */ 503 for (n = 0; n <= PSYCHO_MAX_INO; n++) { 504 if (psycho_find_intrmap(sc, n, &intrmap, &intrclr, 505 NULL) == 0) 506 continue; 507 pica = malloc(sizeof(*pica), M_DEVBUF, M_NOWAIT); 508 if (pica == NULL) 509 panic("%s: could not allocate interrupt " 510 "controller argument", __func__); 511 pica->pica_sc = sc; 512 pica->pica_map = intrmap; 513 pica->pica_clr = intrclr; 514#ifdef PSYCHO_DEBUG 515 /* 516 * Enable all interrupts and clear all interrupt 517 * states. This aids the debugging of interrupt 518 * routing problems. 519 */ 520 device_printf(dev, 521 "intr map (INO %d, %s) %#lx: %#lx, clr: %#lx\n", 522 n, intrmap <= PSR_PCIB3_INT_MAP ? "PCI" : "OBIO", 523 (u_long)intrmap, (u_long)PSYCHO_READ8(sc, intrmap), 524 (u_long)intrclr); 525 PSYCHO_WRITE8(sc, intrmap, INTMAP_VEC(sc->sc_ign, n)); 526 PSYCHO_WRITE8(sc, intrclr, 0); 527 PSYCHO_WRITE8(sc, intrmap, 528 INTMAP_ENABLE(INTMAP_VEC(sc->sc_ign, n), 529 PCPU_GET(mid))); 530#endif 531 if (intr_controller_register(INTMAP_VEC(sc->sc_ign, n), 532 &psycho_ic, pica) != 0) 533 panic("%s: could not register interrupt " 534 "controller for INO %d", __func__, n); 535 } 536 537 /* 538 * Establish handlers for interesting interrupts... 539 * 540 * XXX We need to remember these and remove this to support 541 * hotplug on the UPA/FHC bus. 542 * 543 * XXX Not all controllers have these, but installing them 544 * is better than trying to sort through this mess. 545 */ 546 psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL); 547 psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL); 548#ifdef DEBUGGER_ON_POWERFAIL 549 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, psycho_powerfail, 550 NULL); 551#else 552 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL, 553 (driver_intr_t *)psycho_powerfail); 554#endif 555 /* Psycho-specific initialization */ 556 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 557 /* 558 * Hummingbirds/Sabres do not have the following two 559 * interrupts. 560 */ 561 562 /* 563 * The spare hardware interrupt is used for the 564 * over-temperature interrupt. 565 */ 566 psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP, 567 NULL, psycho_overtemp); 568#ifdef PSYCHO_MAP_WAKEUP 569 /* 570 * psycho_wakeup() doesn't do anything useful right 571 * now. 572 */ 573 psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP, 574 psycho_wakeup, NULL); 575#endif /* PSYCHO_MAP_WAKEUP */ 576 577 /* Initialize the counter-timer. */ 578 sparc64_counter_init(rman_get_bustag(sc->sc_mem_res), 579 rman_get_bushandle(sc->sc_mem_res), PSR_TC0); 580 } 581 582 /* 583 * Set up IOMMU and PCI configuration if we're the first 584 * of a pair of Psycho's to arrive here. 585 * 586 * We should calculate a TSB size based on amount of RAM 587 * and number of bus controllers and number and type of 588 * child devices. 589 * 590 * For the moment, 32KB should be more than enough. 591 */ 592 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 593 M_NOWAIT | M_ZERO); 594 if (sc->sc_is == NULL) 595 panic("%s: malloc iommu_state failed", __func__); 596 if (sc->sc_mode == PSYCHO_MODE_SABRE) 597 sc->sc_is->is_pmaxaddr = 598 IOMMU_MAXADDR(SABRE_IOMMU_BITS); 599 else 600 sc->sc_is->is_pmaxaddr = 601 IOMMU_MAXADDR(PSYCHO_IOMMU_BITS); 602 sc->sc_is->is_sb[0] = 0; 603 sc->sc_is->is_sb[1] = 0; 604 if (OF_getproplen(node, "no-streaming-cache") < 0) 605 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 606 psycho_iommu_init(sc, 3, dvmabase); 607 } else { 608 /* Just copy IOMMU state, config tag and address. */ 609 sc->sc_is = osc->sc_is; 610 if (OF_getproplen(node, "no-streaming-cache") < 0) 611 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 612 iommu_reset(sc->sc_is); 613 } 614 615 /* 616 * Register a PCI bus error interrupt handler according to which 617 * half this is. Hummingbird/Sabre don't have a PCI bus B error 618 * interrupt but they are also only used for PCI bus A. 619 */ 620 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP : 621 PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL); 622 623 /* Allocate our tags. */ 624 sc->sc_pci_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 625 sc->sc_pci_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 626 sc->sc_pci_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 627 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 628 sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr, 629 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0) 630 panic("%s: bus_dma_tag_create failed", __func__); 631 /* Customize the tag. */ 632 sc->sc_pci_dmat->dt_cookie = sc->sc_is; 633 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 634 635 n = OF_getprop(node, "bus-range", (void *)prop_array, 636 sizeof(prop_array)); 637 if (n == -1) 638 panic("%s: could not get bus-range", __func__); 639 if (n != sizeof(prop_array)) 640 panic("%s: broken bus-range (%d)", __func__, n); 641 if (bootverbose) 642 device_printf(dev, "bus range %u to %u; PCI bus %d\n", 643 prop_array[0], prop_array[1], prop_array[0]); 644 sc->sc_pci_secbus = prop_array[0]; 645 646 /* Clear PCI status error bits. */ 647 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, 648 PCIR_STATUS, PCIM_STATUS_PERR | PCIM_STATUS_RMABORT | 649 PCIM_STATUS_RTABORT | PCIM_STATUS_STABORT | 650 PCIM_STATUS_PERRREPORT, 2); 651 652 /* 653 * Set the latency timer register as this isn't always done by the 654 * firmware. 655 */ 656 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, 657 PCIR_LATTIMER, 64, 1); 658 659 for (n = PCIR_VENDOR; n < PCIR_STATUS; n += sizeof(uint16_t)) 660 le16enc(&sc->sc_pci_hpbcfg[n], bus_space_read_2( 661 sc->sc_pci_cfgt, sc->sc_pci_bh[OFW_PCI_CS_CONFIG], 662 PSYCHO_CONF_OFF(sc->sc_pci_secbus, PCS_DEVICE, 663 PCS_FUNC, n))); 664 for (n = PCIR_REVID; n <= PCIR_BIST; n += sizeof(uint8_t)) 665 sc->sc_pci_hpbcfg[n] = bus_space_read_1(sc->sc_pci_cfgt, 666 sc->sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF( 667 sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, n)); 668 669 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 670 /* 671 * On E250 the interrupt map entry for the EBus bridge is wrong, 672 * causing incorrect interrupts to be assigned to some devices on 673 * the EBus. Work around it by changing our copy of the interrupt 674 * map mask to perform a full comparison of the INO. That way 675 * the interrupt map entry for the EBus bridge won't match at all 676 * and the INOs specified in the "interrupts" properties of the 677 * EBus devices will be used directly instead. 678 */ 679 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 && 680 sc->sc_pci_iinfo.opi_imapmsk != NULL) 681 *(ofw_pci_intr_t *)(&sc->sc_pci_iinfo.opi_imapmsk[ 682 sc->sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK; 683 684 device_add_child(dev, "pci", -1); 685 return (bus_generic_attach(dev)); 686} 687 688static void 689psycho_set_intr(struct psycho_softc *sc, u_int index, bus_addr_t intrmap, 690 driver_filter_t filt, driver_intr_t intr) 691{ 692 u_long vec; 693 int rid; 694 695 rid = index; 696 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ, 697 &rid, RF_ACTIVE); 698 if (sc->sc_irq_res[index] == NULL || 699 INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) != sc->sc_ign || 700 INTVEC(PSYCHO_READ8(sc, intrmap)) != vec || 701 intr_vectors[vec].iv_ic != &psycho_ic || 702 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], INTR_TYPE_MISC, 703 filt, intr, sc, &sc->sc_ihand[index]) != 0) 704 panic("%s: failed to set up interrupt %d", __func__, index); 705} 706 707static int 708psycho_find_intrmap(struct psycho_softc *sc, u_int ino, bus_addr_t *intrmapptr, 709 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 710{ 711 bus_addr_t intrclr, intrmap; 712 uint64_t diag; 713 int found; 714 715 /* 716 * XXX we only compare INOs rather than INRs since the firmware may 717 * not provide the IGN and the IGN is constant for all devices on 718 * that PCI controller. 719 * This could cause problems for the FFB/external interrupt which 720 * has a full vector that can be set arbitrarily. 721 */ 722 723 if (ino > PSYCHO_MAX_INO) { 724 device_printf(sc->sc_dev, "out of range INO %d requested\n", 725 ino); 726 return (0); 727 } 728 729 found = 0; 730 /* Hunt through OBIO first. */ 731 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 732 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 733 intrmap <= PSR_PWRMGT_INT_MAP; intrmap += 8, intrclr += 8, 734 diag >>= 2) { 735 if (sc->sc_mode == PSYCHO_MODE_SABRE && 736 (intrmap == PSR_TIMER0_INT_MAP || 737 intrmap == PSR_TIMER1_INT_MAP || 738 intrmap == PSR_PCIBERR_INT_MAP || 739 intrmap == PSR_PWRMGT_INT_MAP)) 740 continue; 741 if (INTINO(PSYCHO_READ8(sc, intrmap)) == ino) { 742 diag &= 2; 743 found = 1; 744 break; 745 } 746 } 747 748 if (!found) { 749 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 750 /* Now do PCI interrupts. */ 751 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 752 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 753 diag >>= 8) { 754 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 755 (intrmap == PSR_PCIA2_INT_MAP || 756 intrmap == PSR_PCIA3_INT_MAP)) 757 continue; 758 if (((PSYCHO_READ8(sc, intrmap) ^ ino) & 0x3c) == 0) { 759 intrclr += 8 * (ino & 3); 760 diag = (diag >> ((ino & 3) * 2)) & 2; 761 found = 1; 762 break; 763 } 764 } 765 } 766 if (intrmapptr != NULL) 767 *intrmapptr = intrmap; 768 if (intrclrptr != NULL) 769 *intrclrptr = intrclr; 770 if (intrdiagptr != NULL) 771 *intrdiagptr = diag; 772 return (found); 773} 774 775/* 776 * Interrupt handlers 777 */ 778static int 779psycho_ue(void *arg) 780{ 781 struct psycho_softc *sc = arg; 782 uint64_t afar, afsr; 783 784 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 785 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 786 /* 787 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 788 * the AFAR to be set to the physical address of the TTE entry that 789 * was invalid/write protected. Call into the iommu code to have 790 * them decoded to virtual I/O addresses. 791 */ 792 if ((afsr & UEAFSR_P_DTE) != 0) 793 iommu_decode_fault(sc->sc_is, afar); 794 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx", 795 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 796 return (FILTER_HANDLED); 797} 798 799static int 800psycho_ce(void *arg) 801{ 802 struct psycho_softc *sc = arg; 803 uint64_t afar, afsr; 804 805 mtx_lock_spin(sc->sc_mtx); 806 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 807 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 808 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx " 809 "AFSR %#lx\n", (u_long)afar, (u_long)afsr); 810 /* Clear the error bits that we caught. */ 811 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr & CEAFSR_ERRMASK); 812 mtx_unlock_spin(sc->sc_mtx); 813 return (FILTER_HANDLED); 814} 815 816static int 817psycho_pci_bus(void *arg) 818{ 819 struct psycho_softc *sc = arg; 820 uint64_t afar, afsr; 821 822 afar = PCICTL_READ8(sc, PCR_AFA); 823 afsr = PCICTL_READ8(sc, PCR_AFS); 824 panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx", 825 device_get_name(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar, 826 (u_long)afsr); 827 return (FILTER_HANDLED); 828} 829 830static int 831psycho_powerfail(void *arg) 832{ 833#ifdef DEBUGGER_ON_POWERFAIL 834 struct psycho_softc *sc = arg; 835 836 kdb_enter(KDB_WHY_POWERFAIL, "powerfail"); 837#else 838 static int shutdown; 839 840 /* As the interrupt is cleared we may be called multiple times. */ 841 if (shutdown != 0) 842 return (FILTER_HANDLED); 843 shutdown++; 844 printf("Power Failure Detected: Shutting down NOW.\n"); 845 shutdown_nice(0); 846#endif 847 return (FILTER_HANDLED); 848} 849 850static void 851psycho_overtemp(void *arg) 852{ 853 static int shutdown; 854 855 /* As the interrupt is cleared we may be called multiple times. */ 856 if (shutdown != 0) 857 return; 858 shutdown++; 859 printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n"); 860 shutdown_nice(RB_POWEROFF); 861} 862 863#ifdef PSYCHO_MAP_WAKEUP 864static int 865psycho_wakeup(void *arg) 866{ 867 struct psycho_softc *sc = arg; 868 869 /* Gee, we don't really have a framework to deal with this properly. */ 870 device_printf(sc->sc_dev, "power management wakeup\n"); 871 return (FILTER_HANDLED); 872} 873#endif /* PSYCHO_MAP_WAKEUP */ 874 875static void 876psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase) 877{ 878 char *name; 879 struct iommu_state *is = sc->sc_is; 880 881 /* Punch in our copies. */ 882 is->is_bustag = rman_get_bustag(sc->sc_mem_res); 883 is->is_bushandle = rman_get_bushandle(sc->sc_mem_res); 884 is->is_iommu = PSR_IOMMU; 885 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 886 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 887 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 888 is->is_dva = PSR_IOMMU_SVADIAG; 889 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 890 891 /* Give us a nice name... */ 892 name = malloc(32, M_DEVBUF, M_NOWAIT); 893 if (name == NULL) 894 panic("%s: could not malloc iommu name", __func__); 895 snprintf(name, 32, "%s dvma", device_get_nameunit(sc->sc_dev)); 896 897 iommu_init(name, is, tsbsize, dvmabase, 0); 898} 899 900static int 901psycho_maxslots(device_t dev) 902{ 903 904 /* XXX: is this correct? */ 905 return (PCI_SLOTMAX); 906} 907 908static uint32_t 909psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 910 int width) 911{ 912 struct psycho_softc *sc; 913 bus_space_handle_t bh; 914 u_long offset = 0; 915 uint8_t byte; 916 uint16_t shrt; 917 uint32_t r, wrd; 918 int i; 919 920 sc = device_get_softc(dev); 921 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 922 923 /* 924 * The Hummingbird and Sabre bridges are picky in that they 925 * only allow their config space to be accessed using the 926 * "native" width of the respective register being accessed 927 * and return semi-random other content of their config space 928 * otherwise. Given that the PCI specs don't say anything 929 * about such a (unusual) limitation and lots of stuff expects 930 * to be able to access the contents of the config space at 931 * any width we allow just that. We do this by using a copy 932 * of the header of the bridge (the rest is all zero anyway) 933 * read during attach (expect for PCIR_STATUS) in order to 934 * simplify things. 935 * The Psycho bridges contain a dupe of their header at 0x80 936 * which we nullify that way also. 937 */ 938 if (bus == sc->sc_pci_secbus && slot == PCS_DEVICE && 939 func == PCS_FUNC) { 940 if (offset % width != 0) 941 return (-1); 942 943 if (reg >= sizeof(sc->sc_pci_hpbcfg)) 944 return (0); 945 946 if ((reg < PCIR_STATUS && reg + width > PCIR_STATUS) || 947 reg == PCIR_STATUS || reg == PCIR_STATUS + 1) 948 le16enc(&sc->sc_pci_hpbcfg[PCIR_STATUS], 949 bus_space_read_2(sc->sc_pci_cfgt, bh, 950 PSYCHO_CONF_OFF(sc->sc_pci_secbus, 951 PCS_DEVICE, PCS_FUNC, PCIR_STATUS))); 952 953 switch (width) { 954 case 1: 955 return (sc->sc_pci_hpbcfg[reg]); 956 case 2: 957 return (le16dec(&sc->sc_pci_hpbcfg[reg])); 958 case 4: 959 return (le32dec(&sc->sc_pci_hpbcfg[reg])); 960 } 961 } 962 963 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 964 switch (width) { 965 case 1: 966 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 967 r = byte; 968 break; 969 case 2: 970 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 971 r = shrt; 972 break; 973 case 4: 974 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 975 r = wrd; 976 break; 977 default: 978 panic("%s: bad width", __func__); 979 } 980 981 if (i) { 982#ifdef PSYCHO_DEBUG 983 printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 984 __func__, bus, slot, func, reg); 985#endif 986 r = -1; 987 } 988 return (r); 989} 990 991static void 992psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 993 uint32_t val, int width) 994{ 995 struct psycho_softc *sc; 996 bus_space_handle_t bh; 997 u_long offset = 0; 998 999 sc = device_get_softc(dev); 1000 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 1001 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1002 switch (width) { 1003 case 1: 1004 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 1005 break; 1006 case 2: 1007 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 1008 break; 1009 case 4: 1010 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 1011 break; 1012 default: 1013 panic("%s: bad width", __func__); 1014 } 1015} 1016 1017static int 1018psycho_route_interrupt(device_t bridge, device_t dev, int pin) 1019{ 1020 struct psycho_softc *sc; 1021 struct ofw_pci_register reg; 1022 bus_addr_t intrmap; 1023 ofw_pci_intr_t pintr, mintr; 1024 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 1025 1026 sc = device_get_softc(bridge); 1027 pintr = pin; 1028 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, 1029 sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) 1030 return (mintr); 1031 /* 1032 * If this is outside of the range for an intpin, it's likely a full 1033 * INO, and no mapping is required at all; this happens on the U30, 1034 * where there's no interrupt map at the Psycho node. Fortunately, 1035 * there seem to be no INOs in the intpin range on this boxen, so 1036 * this easy heuristics will do. 1037 */ 1038 if (pin > 4) 1039 return (pin); 1040 /* 1041 * Guess the INO; we always assume that this is a non-OBIO 1042 * device, and that pin is a "real" intpin number. Determine 1043 * the mapping register to be used by the slot number. 1044 * We only need to do this on E450s, it seems; here, the slot numbers 1045 * for bus A are one-based, while those for bus B seemingly have an 1046 * offset of 2 (hence the factor of 3 below). 1047 */ 1048 intrmap = PSR_PCIA0_INT_MAP + 1049 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half); 1050 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1; 1051 device_printf(bridge, "guessing interrupt %d for device %d.%d pin %d\n", 1052 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin); 1053 return (mintr); 1054} 1055 1056static int 1057psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1058{ 1059 struct psycho_softc *sc; 1060 1061 sc = device_get_softc(dev); 1062 switch (which) { 1063 case PCIB_IVAR_DOMAIN: 1064 *result = device_get_unit(dev); 1065 return (0); 1066 case PCIB_IVAR_BUS: 1067 *result = sc->sc_pci_secbus; 1068 return (0); 1069 } 1070 return (ENOENT); 1071} 1072 1073static int 1074psycho_dmasync(void *arg) 1075{ 1076 struct psycho_dmasync *pds = arg; 1077 1078 (void)PCIB_READ_CONFIG(pds->pds_ppb, pds->pds_bus, pds->pds_slot, 1079 pds->pds_func, PCIR_VENDOR, 2); 1080 (void)PSYCHO_READ8(pds->pds_sc, PSR_DMA_WRITE_SYNC); 1081 return (pds->pds_handler(pds->pds_arg)); 1082} 1083 1084static void 1085psycho_intr_enable(void *arg) 1086{ 1087 struct intr_vector *iv = arg; 1088 struct psycho_icarg *pica = iv->iv_icarg; 1089 1090 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, 1091 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1092} 1093 1094static void 1095psycho_intr_disable(void *arg) 1096{ 1097 struct intr_vector *iv = arg; 1098 struct psycho_icarg *pica = iv->iv_icarg; 1099 1100 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, iv->iv_vec); 1101} 1102 1103static void 1104psycho_intr_assign(void *arg) 1105{ 1106 struct intr_vector *iv = arg; 1107 struct psycho_icarg *pica = iv->iv_icarg; 1108 1109 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, INTMAP_TID( 1110 PSYCHO_READ8(pica->pica_sc, pica->pica_map), iv->iv_mid)); 1111} 1112 1113static void 1114psycho_intr_clear(void *arg) 1115{ 1116 struct intr_vector *iv = arg; 1117 struct psycho_icarg *pica = iv->iv_icarg; 1118 1119 PSYCHO_WRITE8(pica->pica_sc, pica->pica_clr, 0); 1120} 1121 1122static int 1123psycho_setup_intr(device_t dev, device_t child, struct resource *ires, 1124 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1125 void **cookiep) 1126{ 1127 struct { 1128 int apb:1; 1129 int ppb:1; 1130 } found; 1131 devclass_t pci_devclass; 1132 device_t cdev, pdev, pcidev; 1133 struct psycho_softc *sc; 1134 struct psycho_dmasync *pds; 1135 u_long vec; 1136 int error; 1137 1138 sc = device_get_softc(dev); 1139 /* 1140 * Make sure the vector is fully specified and we registered 1141 * our interrupt controller for it. 1142 */ 1143 vec = rman_get_start(ires); 1144 if (INTIGN(vec) != sc->sc_ign || 1145 intr_vectors[vec].iv_ic != &psycho_ic) { 1146 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1147 return (EINVAL); 1148 } 1149 1150 /* 1151 * The Sabre-APB-combination has a bug where it does not drain 1152 * DMA write data for devices behind additional PCI-PCI bridges 1153 * underneath the APB PCI-PCI bridge. The workaround is to do 1154 * a read on the farest PCI-PCI bridge followed by a read of the 1155 * PCI DMA write sync register of the Sabre. 1156 * XXX installing the wrapper for an affected device and the 1157 * actual workaround in psycho_dmasync() should be moved to 1158 * psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() 1159 * methods, respectively, once DMA tag creation is newbus'ified, 1160 * so the workaround isn't only applied for interrupt handlers 1161 * but also for polling(4) callbacks. 1162 */ 1163 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 1164 pds = malloc(sizeof(*pds), M_DEVBUF, M_NOWAIT | M_ZERO); 1165 if (pds == NULL) 1166 return (ENOMEM); 1167 pcidev = NULL; 1168 found.apb = found.ppb = 0; 1169 pci_devclass = devclass_find("pci"); 1170 for (cdev = child; cdev != dev; cdev = pdev) { 1171 pdev = device_get_parent(cdev); 1172 if (pcidev == NULL) { 1173 if (device_get_devclass(pdev) != pci_devclass) 1174 continue; 1175 pcidev = cdev; 1176 continue; 1177 } 1178 /* 1179 * NB: APB would also match as PCI-PCI bridges. 1180 */ 1181 if (pci_get_vendor(cdev) == 0x108e && 1182 pci_get_device(cdev) == 0x5000) { 1183 found.apb = 1; 1184 break; 1185 } 1186 if (pci_get_class(cdev) == PCIC_BRIDGE && 1187 pci_get_subclass(cdev) == PCIS_BRIDGE_PCI) 1188 found.ppb = 1; 1189 } 1190 if (found.apb && found.ppb && pcidev != NULL) { 1191 pds->pds_sc = sc; 1192 pds->pds_arg = arg; 1193 pds->pds_ppb = 1194 device_get_parent(device_get_parent(pcidev)); 1195 pds->pds_bus = pci_get_bus(pcidev); 1196 pds->pds_slot = pci_get_slot(pcidev); 1197 pds->pds_func = pci_get_function(pcidev); 1198 if (bootverbose) 1199 device_printf(dev, "installed DMA sync " 1200 "workaround for device %d.%d on bus %d\n", 1201 pds->pds_slot, pds->pds_func, 1202 pds->pds_bus); 1203 if (intr == NULL) { 1204 pds->pds_handler = filt; 1205 error = bus_generic_setup_intr(dev, child, 1206 ires, flags, psycho_dmasync, intr, pds, 1207 cookiep); 1208 } else { 1209 pds->pds_handler = (driver_filter_t *)intr; 1210 error = bus_generic_setup_intr(dev, child, 1211 ires, flags, filt, 1212 (driver_intr_t *)psycho_dmasync, pds, 1213 cookiep); 1214 } 1215 } else 1216 error = bus_generic_setup_intr(dev, child, ires, 1217 flags, filt, intr, arg, cookiep); 1218 if (error != 0) { 1219 free(pds, M_DEVBUF); 1220 return (error); 1221 } 1222 pds->pds_cookie = *cookiep; 1223 *cookiep = pds; 1224 return (error); 1225 } 1226 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1227 arg, cookiep)); 1228} 1229 1230static int 1231psycho_teardown_intr(device_t dev, device_t child, struct resource *vec, 1232 void *cookie) 1233{ 1234 struct psycho_softc *sc; 1235 struct psycho_dmasync *pds; 1236 int error; 1237 1238 sc = device_get_softc(dev); 1239 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 1240 pds = cookie; 1241 error = bus_generic_teardown_intr(dev, child, vec, 1242 pds->pds_cookie); 1243 if (error == 0) 1244 free(pds, M_DEVBUF); 1245 return (error); 1246 } 1247 return (bus_generic_teardown_intr(dev, child, vec, cookie)); 1248} 1249 1250static struct resource * 1251psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1252 u_long start, u_long end, u_long count, u_int flags) 1253{ 1254 struct psycho_softc *sc; 1255 struct resource *rv; 1256 struct rman *rm; 1257 bus_space_tag_t bt; 1258 bus_space_handle_t bh; 1259 int needactivate = flags & RF_ACTIVE; 1260 1261 flags &= ~RF_ACTIVE; 1262 1263 sc = device_get_softc(bus); 1264 if (type == SYS_RES_IRQ) { 1265 /* 1266 * XXX: Don't accept blank ranges for now, only single 1267 * interrupts. The other case should not happen with the 1268 * MI PCI code... 1269 * XXX: This may return a resource that is out of the 1270 * range that was specified. Is this correct...? 1271 */ 1272 if (start != end) 1273 panic("%s: XXX: interrupt range", __func__); 1274 start = end = INTMAP_VEC(sc->sc_ign, end); 1275 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, 1276 rid, start, end, count, flags)); 1277 } 1278 switch (type) { 1279 case SYS_RES_MEMORY: 1280 rm = &sc->sc_pci_mem_rman; 1281 bt = sc->sc_pci_memt; 1282 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1283 break; 1284 case SYS_RES_IOPORT: 1285 rm = &sc->sc_pci_io_rman; 1286 bt = sc->sc_pci_iot; 1287 bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1288 break; 1289 default: 1290 return (NULL); 1291 } 1292 1293 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1294 if (rv == NULL) 1295 return (NULL); 1296 rman_set_rid(rv, *rid); 1297 bh += rman_get_start(rv); 1298 rman_set_bustag(rv, bt); 1299 rman_set_bushandle(rv, bh); 1300 1301 if (needactivate) { 1302 if (bus_activate_resource(child, type, *rid, rv)) { 1303 rman_release_resource(rv); 1304 return (NULL); 1305 } 1306 } 1307 1308 return (rv); 1309} 1310 1311static int 1312psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1313 struct resource *r) 1314{ 1315 void *p; 1316 int error; 1317 1318 if (type == SYS_RES_IRQ) 1319 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1320 type, rid, r)); 1321 if (type == SYS_RES_MEMORY) { 1322 /* 1323 * Need to memory-map the device space, as some drivers depend 1324 * on the virtual address being set and useable. 1325 */ 1326 error = sparc64_bus_mem_map(rman_get_bustag(r), 1327 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1328 if (error != 0) 1329 return (error); 1330 rman_set_virtual(r, p); 1331 } 1332 return (rman_activate_resource(r)); 1333} 1334 1335static int 1336psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1337 struct resource *r) 1338{ 1339 1340 if (type == SYS_RES_IRQ) 1341 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1342 type, rid, r)); 1343 if (type == SYS_RES_MEMORY) { 1344 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1345 rman_set_virtual(r, NULL); 1346 } 1347 return (rman_deactivate_resource(r)); 1348} 1349 1350static int 1351psycho_release_resource(device_t bus, device_t child, int type, int rid, 1352 struct resource *r) 1353{ 1354 int error; 1355 1356 if (type == SYS_RES_IRQ) 1357 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1358 type, rid, r)); 1359 if (rman_get_flags(r) & RF_ACTIVE) { 1360 error = bus_deactivate_resource(child, type, rid, r); 1361 if (error) 1362 return (error); 1363 } 1364 return (rman_release_resource(r)); 1365} 1366 1367static bus_dma_tag_t 1368psycho_get_dma_tag(device_t bus, device_t child) 1369{ 1370 struct psycho_softc *sc; 1371 1372 sc = device_get_softc(bus); 1373 return (sc->sc_pci_dmat); 1374} 1375 1376static int 1377psycho_intr_pending(device_t dev, ofw_pci_intr_t intr) 1378{ 1379 struct psycho_softc *sc; 1380 u_long diag; 1381 1382 sc = device_get_softc(dev); 1383 if (psycho_find_intrmap(sc, intr, NULL, NULL, &diag) == 0) { 1384 device_printf(dev, "%s: mapping not found for %d\n", __func__, 1385 intr); 1386 return (0); 1387 } 1388 return (diag != 0); 1389} 1390 1391static phandle_t 1392psycho_get_node(device_t bus, device_t dev) 1393{ 1394 struct psycho_softc *sc; 1395 1396 sc = device_get_softc(bus); 1397 /* We only have one child, the PCI bus, which needs our own node. */ 1398 return (sc->sc_node); 1399} 1400 1401static bus_space_tag_t 1402psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1403{ 1404 bus_space_tag_t bt; 1405 1406 bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF, M_NOWAIT | M_ZERO); 1407 if (bt == NULL) 1408 panic("%s: out of memory", __func__); 1409 1410 bt->bst_cookie = sc; 1411 bt->bst_parent = rman_get_bustag(sc->sc_mem_res); 1412 bt->bst_type = type; 1413 return (bt); 1414} 1415