psycho.c revision 178279
1/*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/sparc64/pci/psycho.c 178279 2008-04-17 12:38:00Z marius $"); 35 36/* 37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+' 38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges. 39 */ 40 41#include "opt_ofw_pci.h" 42#include "opt_psycho.h" 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/bus.h> 47#include <sys/endian.h> 48#include <sys/kdb.h> 49#include <sys/kernel.h> 50#include <sys/lock.h> 51#include <sys/malloc.h> 52#include <sys/module.h> 53#include <sys/mutex.h> 54#include <sys/pcpu.h> 55#include <sys/reboot.h> 56#include <sys/rman.h> 57 58#include <dev/ofw/ofw_bus.h> 59#include <dev/ofw/ofw_pci.h> 60#include <dev/ofw/openfirm.h> 61 62#include <machine/bus.h> 63#include <machine/bus_common.h> 64#include <machine/bus_private.h> 65#include <machine/iommureg.h> 66#include <machine/iommuvar.h> 67#include <machine/ofw_bus.h> 68#include <machine/resource.h> 69#include <machine/ver.h> 70 71#include <dev/pci/pcireg.h> 72#include <dev/pci/pcivar.h> 73 74#include <sparc64/pci/ofw_pci.h> 75#include <sparc64/pci/psychoreg.h> 76#include <sparc64/pci/psychovar.h> 77 78#include "pcib_if.h" 79 80static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *, 81 const char *); 82static const struct psycho_desc *psycho_get_desc(device_t); 83static void psycho_set_intr(struct psycho_softc *, u_int, bus_addr_t, 84 driver_filter_t, driver_intr_t); 85static int psycho_find_intrmap(struct psycho_softc *, u_int, bus_addr_t *, 86 bus_addr_t *, u_long *); 87static driver_filter_t psycho_dmasync; 88static void psycho_intr_enable(void *); 89static void psycho_intr_disable(void *); 90static void psycho_intr_eoi(void *); 91static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 92 93/* Interrupt handlers */ 94static driver_filter_t psycho_ue; 95static driver_filter_t psycho_ce; 96static driver_filter_t psycho_pci_bus; 97static driver_filter_t psycho_powerfail; 98static driver_intr_t psycho_overtemp; 99#ifdef PSYCHO_MAP_WAKEUP 100static driver_filter_t psycho_wakeup; 101#endif 102 103/* IOMMU support */ 104static void psycho_iommu_init(struct psycho_softc *, int, uint32_t); 105 106/* 107 * Methods 108 */ 109static device_probe_t psycho_probe; 110static device_attach_t psycho_attach; 111static bus_read_ivar_t psycho_read_ivar; 112static bus_setup_intr_t psycho_setup_intr; 113static bus_teardown_intr_t psycho_teardown_intr; 114static bus_alloc_resource_t psycho_alloc_resource; 115static bus_activate_resource_t psycho_activate_resource; 116static bus_deactivate_resource_t psycho_deactivate_resource; 117static bus_release_resource_t psycho_release_resource; 118static bus_get_dma_tag_t psycho_get_dma_tag; 119static pcib_maxslots_t psycho_maxslots; 120static pcib_read_config_t psycho_read_config; 121static pcib_write_config_t psycho_write_config; 122static pcib_route_interrupt_t psycho_route_interrupt; 123static ofw_pci_intr_pending_t psycho_intr_pending; 124static ofw_bus_get_node_t psycho_get_node; 125 126static device_method_t psycho_methods[] = { 127 /* Device interface */ 128 DEVMETHOD(device_probe, psycho_probe), 129 DEVMETHOD(device_attach, psycho_attach), 130 DEVMETHOD(device_shutdown, bus_generic_shutdown), 131 DEVMETHOD(device_suspend, bus_generic_suspend), 132 DEVMETHOD(device_resume, bus_generic_resume), 133 134 /* Bus interface */ 135 DEVMETHOD(bus_print_child, bus_generic_print_child), 136 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 137 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 138 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 139 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 140 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 141 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 142 DEVMETHOD(bus_release_resource, psycho_release_resource), 143 DEVMETHOD(bus_get_dma_tag, psycho_get_dma_tag), 144 145 /* pcib interface */ 146 DEVMETHOD(pcib_maxslots, psycho_maxslots), 147 DEVMETHOD(pcib_read_config, psycho_read_config), 148 DEVMETHOD(pcib_write_config, psycho_write_config), 149 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 150 151 /* ofw_bus interface */ 152 DEVMETHOD(ofw_bus_get_node, psycho_get_node), 153 154 /* ofw_pci interface */ 155 DEVMETHOD(ofw_pci_intr_pending, psycho_intr_pending), 156 157 { 0, 0 } 158}; 159 160static devclass_t psycho_devclass; 161 162DEFINE_CLASS_0(pcib, psycho_driver, psycho_methods, 163 sizeof(struct psycho_softc)); 164DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 165 166static SLIST_HEAD(, psycho_softc) psycho_softcs = 167 SLIST_HEAD_INITIALIZER(psycho_softcs); 168 169static const struct intr_controller psycho_ic = { 170 psycho_intr_enable, 171 psycho_intr_disable, 172 psycho_intr_eoi 173}; 174 175struct psycho_icarg { 176 struct psycho_softc *pica_sc; 177 bus_addr_t pica_map; 178 bus_addr_t pica_clr; 179}; 180 181struct psycho_dmasync { 182 struct psycho_softc *pds_sc; 183 driver_filter_t *pds_handler; /* handler to call */ 184 void *pds_arg; /* argument for the handler */ 185 void *pds_cookie; /* parent bus int. cookie */ 186 device_t pds_ppb; /* farest PCI-PCI bridge */ 187 uint8_t pds_bus; /* bus of farest PCI device */ 188 uint8_t pds_slot; /* slot of farest PCI device */ 189 uint8_t pds_func; /* func. of farest PCI device */ 190}; 191 192#define PSYCHO_READ8(sc, off) \ 193 bus_read_8((sc)->sc_mem_res, (off)) 194#define PSYCHO_WRITE8(sc, off, v) \ 195 bus_write_8((sc)->sc_mem_res, (off), (v)) 196#define PCICTL_READ8(sc, off) \ 197 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 198#define PCICTL_WRITE8(sc, off, v) \ 199 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 200 201/* 202 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 203 * single PCI bus and does not have a streaming buffer. It often has an APB 204 * (advanced PCI bridge) connected to it, which was designed specifically for 205 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 206 * appears as two "Simba"'s underneath the Sabre. 207 * 208 * "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's 209 * basically the same as Sabre but without an APB underneath it. 210 * 211 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA bus 212 * and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while 213 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 214 * will usually find a "Psycho+" since I don't think the original "Psycho" 215 * ever shipped, and if it did it would be in the U30. 216 * 217 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are 218 * both part of the same IC, they only have a single register space. As such, 219 * they need to be configured together, even though the autoconfiguration will 220 * attach them separately. 221 * 222 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often 223 * as pci1 and pci2, although they have been implemented with other PCI bus 224 * numbers on some machines. 225 * 226 * On UltraII machines, there can be any number of "Psycho+" ICs, each 227 * providing two PCI buses. 228 */ 229 230#define OFW_PCI_TYPE "pci" 231 232struct psycho_desc { 233 const char *pd_string; 234 int pd_mode; 235 const char *pd_name; 236}; 237 238static const struct psycho_desc psycho_compats[] = { 239 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 240 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" }, 241 { "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" }, 242 { NULL, 0, NULL } 243}; 244 245static const struct psycho_desc psycho_models[] = { 246 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 247 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 248 { NULL, 0, NULL } 249}; 250 251static const struct psycho_desc * 252psycho_find_desc(const struct psycho_desc *table, const char *string) 253{ 254 const struct psycho_desc *desc; 255 256 if (string == NULL) 257 return (NULL); 258 for (desc = table; desc->pd_string != NULL; desc++) 259 if (strcmp(desc->pd_string, string) == 0) 260 return (desc); 261 return (NULL); 262} 263 264static const struct psycho_desc * 265psycho_get_desc(device_t dev) 266{ 267 const struct psycho_desc *rv; 268 269 rv = psycho_find_desc(psycho_models, ofw_bus_get_model(dev)); 270 if (rv == NULL) 271 rv = psycho_find_desc(psycho_compats, ofw_bus_get_compat(dev)); 272 return (rv); 273} 274 275static int 276psycho_probe(device_t dev) 277{ 278 const char *dtype; 279 280 dtype = ofw_bus_get_type(dev); 281 if (dtype != NULL && strcmp(dtype, OFW_PCI_TYPE) == 0 && 282 psycho_get_desc(dev) != NULL) { 283 device_set_desc(dev, "U2P UPA-PCI bridge"); 284 return (0); 285 } 286 287 return (ENXIO); 288} 289 290static int 291psycho_attach(device_t dev) 292{ 293 char name[sizeof("pci108e,1000")]; 294 struct psycho_icarg *pica; 295 struct psycho_softc *asc, *sc, *osc; 296 struct ofw_pci_ranges *range; 297 const struct psycho_desc *desc; 298 bus_addr_t intrclr, intrmap; 299 uint64_t csr, dr; 300 phandle_t child, node; 301 uint32_t dvmabase, prop_array[2]; 302 int32_t rev; 303 u_int ver; 304 int i, n, nrange, rid; 305 306 node = ofw_bus_get_node(dev); 307 sc = device_get_softc(dev); 308 desc = psycho_get_desc(dev); 309 310 sc->sc_node = node; 311 sc->sc_dev = dev; 312 sc->sc_mode = desc->pd_mode; 313 314 /* 315 * The Psycho gets three register banks: 316 * (0) per-PBM configuration and status registers 317 * (1) per-PBM PCI configuration space, containing only the 318 * PBM 256-byte PCI header 319 * (2) the shared Psycho configuration registers 320 */ 321 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 322 rid = 2; 323 sc->sc_pcictl = 324 bus_get_resource_start(dev, SYS_RES_MEMORY, 0) - 325 bus_get_resource_start(dev, SYS_RES_MEMORY, 2); 326 switch (sc->sc_pcictl) { 327 case PSR_PCICTL0: 328 sc->sc_half = 0; 329 break; 330 case PSR_PCICTL1: 331 sc->sc_half = 1; 332 break; 333 default: 334 panic("%s: bogus PCI control register location", 335 __func__); 336 } 337 } else { 338 rid = 0; 339 sc->sc_pcictl = PSR_PCICTL0; 340 sc->sc_half = 0; 341 } 342 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 343 (sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) | 344 RF_ACTIVE); 345 if (sc->sc_mem_res == NULL) 346 panic("%s: could not allocate registers", __func__); 347 348 /* 349 * Match other Psycho's that are already configured against 350 * the base physical address. This will be the same for a 351 * pair of devices that share register space. 352 */ 353 osc = NULL; 354 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 355 if (rman_get_start(asc->sc_mem_res) == 356 rman_get_start(sc->sc_mem_res)) { 357 /* Found partner. */ 358 osc = asc; 359 break; 360 } 361 } 362 if (osc == NULL) { 363 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 364 M_NOWAIT | M_ZERO); 365 if (sc->sc_mtx == NULL) 366 panic("%s: could not malloc mutex", __func__); 367 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 368 } else { 369 if (mtx_initialized(osc->sc_mtx) == 0) 370 panic("%s: mutex not initialized", __func__); 371 sc->sc_mtx = osc->sc_mtx; 372 } 373 374 /* Clear PCI AFSR. */ 375 PCICTL_WRITE8(sc, PCR_AFS, PCIAFSR_ERRMASK); 376 377 csr = PSYCHO_READ8(sc, PSR_CS); 378 ver = PSYCHO_GCSR_VERS(csr); 379 sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */ 380 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 381 sc->sc_ign = PSYCHO_GCSR_IGN(csr); 382 383 device_printf(dev, "%s, impl %d, version %d, IGN %#x, bus %c\n", 384 desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign, 385 'A' + sc->sc_half); 386 387 /* Set up the PCI control and PCI diagnostic registers. */ 388 389 /* 390 * Revision 0 EBus bridges have a bug which prevents them from 391 * working when bus parking is enabled. 392 */ 393 rev = -1; 394 csr = PCICTL_READ8(sc, PCR_CS); 395 csr &= ~PCICTL_ARB_PARK; 396 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 397 if (OF_getprop(child, "name", name, sizeof(name)) == -1) 398 continue; 399 if ((strcmp(name, "ebus") == 0 || 400 strcmp(name, "pci108e,1000") == 0) && 401 OF_getprop(child, "revision-id", &rev, sizeof(rev)) > 0 && 402 rev == 0) 403 break; 404 } 405 if (rev != 0 && OF_getproplen(node, "no-bus-parking") < 0) 406 csr |= PCICTL_ARB_PARK; 407 408 /* Workarounds for version specific bugs. */ 409 dr = PCICTL_READ8(sc, PCR_DIAG); 410 switch (ver) { 411 case 0: 412 dr |= DIAG_RTRY_DIS; 413 dr &= ~DIAG_DWSYNC_DIS; 414 /* XXX need to also disable rerun of the streaming buffers. */ 415 break; 416 case 1: 417 csr &= ~PCICTL_ARB_PARK; 418 dr |= DIAG_RTRY_DIS | DIAG_DWSYNC_DIS; 419 /* XXX need to also disable rerun of the streaming buffers. */ 420 break; 421 default: 422 dr |= DIAG_DWSYNC_DIS; 423 dr &= ~DIAG_RTRY_DIS; 424 break; 425 } 426 427 csr |= PCICTL_SERR | PCICTL_ERRINTEN | PCICTL_ARB_4; 428 csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN); 429#ifdef PSYCHO_DEBUG 430 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 431 (unsigned long long)PCICTL_READ8(sc, PCR_CS), 432 (unsigned long long)csr); 433#endif 434 PCICTL_WRITE8(sc, PCR_CS, csr); 435 436 dr &= ~DIAG_ISYNC_DIS; 437#ifdef PSYCHO_DEBUG 438 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 439 (unsigned long long)PCICTL_READ8(sc, PCR_DIAG), 440 (unsigned long long)dr); 441#endif 442 PCICTL_WRITE8(sc, PCR_DIAG, dr); 443 444 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 445 /* Use the PROM preset for now. */ 446 csr = PCICTL_READ8(sc, PCR_TAS); 447 if (csr == 0) 448 panic("%s: Hummingbird/Sabre TAS not initialized.", 449 __func__); 450 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT; 451 } else 452 dvmabase = -1; 453 454 /* Initialize memory and I/O rmans. */ 455 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 456 sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports"; 457 if (rman_init(&sc->sc_pci_io_rman) != 0 || 458 rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0) 459 panic("%s: failed to set up I/O rman", __func__); 460 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 461 sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory"; 462 if (rman_init(&sc->sc_pci_mem_rman) != 0 || 463 rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 464 panic("%s: failed to set up memory rman", __func__); 465 466 nrange = OF_getprop_alloc(node, "ranges", sizeof(*range), 467 (void **)&range); 468 /* 469 * Make sure that the expected ranges are present. The OFW_PCI_CS_MEM64 470 * one is not currently used though. 471 */ 472 if (nrange != PSYCHO_NRANGE) 473 panic("%s: unsupported number of ranges", __func__); 474 /* 475 * Find the addresses of the various bus spaces. 476 * There should not be multiple ones of one kind. 477 * The physical start addresses of the ranges are the configuration, 478 * memory and I/O handles. 479 */ 480 for (n = 0; n < PSYCHO_NRANGE; n++) { 481 i = OFW_PCI_RANGE_CS(&range[n]); 482 if (sc->sc_pci_bh[i] != 0) 483 panic("%s: duplicate range for space %d", __func__, i); 484 sc->sc_pci_bh[i] = OFW_PCI_RANGE_PHYS(&range[n]); 485 } 486 free(range, M_OFWPROP); 487 488 /* Register the softc, this is needed for paired Psychos. */ 489 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 490 491 /* 492 * If we're a Hummingbird/Sabre or the first of a pair of Psychos 493 * to arrive here, do the interrupt setup and start up the IOMMU. 494 */ 495 if (osc == NULL) { 496 /* 497 * Hunt through all the interrupt mapping regs and register 498 * our interrupt controller for the corresponding interrupt 499 * vectors. 500 */ 501 for (n = 0; n <= PSYCHO_MAX_INO; n++) { 502 if (psycho_find_intrmap(sc, n, &intrmap, &intrclr, 503 NULL) == 0) 504 continue; 505 pica = malloc(sizeof(*pica), M_DEVBUF, M_NOWAIT); 506 if (pica == NULL) 507 panic("%s: could not allocate interrupt " 508 "controller argument", __func__); 509 pica->pica_sc = sc; 510 pica->pica_map = intrmap; 511 pica->pica_clr = intrclr; 512#ifdef PSYCHO_DEBUG 513 /* 514 * Enable all interrupts and clear all interrupt 515 * states. This aids the debugging of interrupt 516 * routing problems. 517 */ 518 device_printf(dev, 519 "intr map (INO %d, %s) %#lx: %#lx, clr: %#lx\n", 520 n, intrmap <= PSR_PCIB3_INT_MAP ? "PCI" : "OBIO", 521 (u_long)intrmap, (u_long)PSYCHO_READ8(sc, intrmap), 522 (u_long)intrclr); 523 PSYCHO_WRITE8(sc, intrmap, INTMAP_VEC(sc->sc_ign, n)); 524 PSYCHO_WRITE8(sc, intrclr, 0); 525 PSYCHO_WRITE8(sc, intrmap, 526 INTMAP_ENABLE(INTMAP_VEC(sc->sc_ign, n), 527 PCPU_GET(mid))); 528#endif 529 if (intr_controller_register(INTMAP_VEC(sc->sc_ign, n), 530 &psycho_ic, pica) != 0) 531 panic("%s: could not register interrupt " 532 "controller for INO %d", __func__, n); 533 } 534 535 /* 536 * Establish handlers for interesting interrupts... 537 * 538 * XXX We need to remember these and remove this to support 539 * hotplug on the UPA/FHC bus. 540 * 541 * XXX Not all controllers have these, but installing them 542 * is better than trying to sort through this mess. 543 */ 544 psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL); 545 psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL); 546#ifdef DEBUGGER_ON_POWERFAIL 547 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, psycho_powerfail, 548 NULL); 549#else 550 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL, 551 (driver_intr_t *)psycho_powerfail); 552#endif 553 /* Psycho-specific initialization */ 554 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 555 /* 556 * Hummingbirds/Sabres do not have the following two 557 * interrupts. 558 */ 559 560 /* 561 * The spare hardware interrupt is used for the 562 * over-temperature interrupt. 563 */ 564 psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP, 565 NULL, psycho_overtemp); 566#ifdef PSYCHO_MAP_WAKEUP 567 /* 568 * psycho_wakeup() doesn't do anything useful right 569 * now. 570 */ 571 psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP, 572 psycho_wakeup, NULL); 573#endif /* PSYCHO_MAP_WAKEUP */ 574 575 /* Initialize the counter-timer. */ 576 sparc64_counter_init(rman_get_bustag(sc->sc_mem_res), 577 rman_get_bushandle(sc->sc_mem_res), PSR_TC0); 578 } 579 580 /* 581 * Set up IOMMU and PCI configuration if we're the first 582 * of a pair of Psycho's to arrive here. 583 * 584 * We should calculate a TSB size based on amount of RAM 585 * and number of bus controllers and number and type of 586 * child devices. 587 * 588 * For the moment, 32KB should be more than enough. 589 */ 590 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 591 M_NOWAIT | M_ZERO); 592 if (sc->sc_is == NULL) 593 panic("%s: malloc iommu_state failed", __func__); 594 if (sc->sc_mode == PSYCHO_MODE_SABRE) 595 sc->sc_is->is_pmaxaddr = 596 IOMMU_MAXADDR(SABRE_IOMMU_BITS); 597 else 598 sc->sc_is->is_pmaxaddr = 599 IOMMU_MAXADDR(PSYCHO_IOMMU_BITS); 600 sc->sc_is->is_sb[0] = 0; 601 sc->sc_is->is_sb[1] = 0; 602 if (OF_getproplen(node, "no-streaming-cache") < 0) 603 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 604 psycho_iommu_init(sc, 3, dvmabase); 605 } else { 606 /* Just copy IOMMU state, config tag and address. */ 607 sc->sc_is = osc->sc_is; 608 if (OF_getproplen(node, "no-streaming-cache") < 0) 609 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 610 iommu_reset(sc->sc_is); 611 } 612 613 /* 614 * Register a PCI bus error interrupt handler according to which 615 * half this is. Hummingbird/Sabre don't have a PCI bus B error 616 * interrupt but they are also only used for PCI bus A. 617 */ 618 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP : 619 PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL); 620 621 /* Allocate our tags. */ 622 sc->sc_pci_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 623 sc->sc_pci_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 624 sc->sc_pci_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 625 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 626 sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr, 627 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0) 628 panic("%s: bus_dma_tag_create failed", __func__); 629 /* Customize the tag. */ 630 sc->sc_pci_dmat->dt_cookie = sc->sc_is; 631 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 632 633 n = OF_getprop(node, "bus-range", (void *)prop_array, 634 sizeof(prop_array)); 635 if (n == -1) 636 panic("%s: could not get bus-range", __func__); 637 if (n != sizeof(prop_array)) 638 panic("%s: broken bus-range (%d)", __func__, n); 639 if (bootverbose) 640 device_printf(dev, "bus range %u to %u; PCI bus %d\n", 641 prop_array[0], prop_array[1], prop_array[0]); 642 sc->sc_pci_secbus = prop_array[0]; 643 644 /* Clear PCI status error bits. */ 645 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, 646 PCIR_STATUS, PCIM_STATUS_PERR | PCIM_STATUS_RMABORT | 647 PCIM_STATUS_RTABORT | PCIM_STATUS_STABORT | 648 PCIM_STATUS_PERRREPORT, 2); 649 650 /* 651 * Set the latency timer register as this isn't always done by the 652 * firmware. 653 */ 654 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, 655 PCIR_LATTIMER, 64, 1); 656 657 for (n = PCIR_VENDOR; n < PCIR_STATUS; n += sizeof(uint16_t)) 658 le16enc(&sc->sc_pci_hpbcfg[n], bus_space_read_2( 659 sc->sc_pci_cfgt, sc->sc_pci_bh[OFW_PCI_CS_CONFIG], 660 PSYCHO_CONF_OFF(sc->sc_pci_secbus, PCS_DEVICE, 661 PCS_FUNC, n))); 662 for (n = PCIR_REVID; n <= PCIR_BIST; n += sizeof(uint8_t)) 663 sc->sc_pci_hpbcfg[n] = bus_space_read_1(sc->sc_pci_cfgt, 664 sc->sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF( 665 sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, n)); 666 667 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 668 /* 669 * On E250 the interrupt map entry for the EBus bridge is wrong, 670 * causing incorrect interrupts to be assigned to some devices on 671 * the EBus. Work around it by changing our copy of the interrupt 672 * map mask to perform a full comparison of the INO. That way 673 * the interrupt map entry for the EBus bridge won't match at all 674 * and the INOs specified in the "interrupts" properties of the 675 * EBus devices will be used directly instead. 676 */ 677 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 && 678 sc->sc_pci_iinfo.opi_imapmsk != NULL) 679 *(ofw_pci_intr_t *)(&sc->sc_pci_iinfo.opi_imapmsk[ 680 sc->sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK; 681 682 device_add_child(dev, "pci", -1); 683 return (bus_generic_attach(dev)); 684} 685 686static void 687psycho_set_intr(struct psycho_softc *sc, u_int index, bus_addr_t intrmap, 688 driver_filter_t filt, driver_intr_t intr) 689{ 690 u_long vec; 691 int rid; 692 693 rid = index; 694 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ, 695 &rid, RF_ACTIVE); 696 if (sc->sc_irq_res[index] == NULL || 697 INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) != sc->sc_ign || 698 INTVEC(PSYCHO_READ8(sc, intrmap)) != vec || 699 intr_vectors[vec].iv_ic != &psycho_ic || 700 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], INTR_TYPE_MISC, 701 filt, intr, sc, &sc->sc_ihand[index]) != 0) 702 panic("%s: failed to set up interrupt %d", __func__, index); 703} 704 705static int 706psycho_find_intrmap(struct psycho_softc *sc, u_int ino, bus_addr_t *intrmapptr, 707 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 708{ 709 bus_addr_t intrclr, intrmap; 710 uint64_t diag; 711 int found; 712 713 /* 714 * XXX we only compare INOs rather than INRs since the firmware may 715 * not provide the IGN and the IGN is constant for all devices on 716 * that PCI controller. 717 * This could cause problems for the FFB/external interrupt which 718 * has a full vector that can be set arbitrarily. 719 */ 720 721 if (ino > PSYCHO_MAX_INO) { 722 device_printf(sc->sc_dev, "out of range INO %d requested\n", 723 ino); 724 return (0); 725 } 726 727 found = 0; 728 /* Hunt through OBIO first. */ 729 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 730 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 731 intrmap <= PSR_PWRMGT_INT_MAP; intrmap += 8, intrclr += 8, 732 diag >>= 2) { 733 if (sc->sc_mode == PSYCHO_MODE_SABRE && 734 (intrmap == PSR_TIMER0_INT_MAP || 735 intrmap == PSR_TIMER1_INT_MAP || 736 intrmap == PSR_PCIBERR_INT_MAP || 737 intrmap == PSR_PWRMGT_INT_MAP)) 738 continue; 739 if (INTINO(PSYCHO_READ8(sc, intrmap)) == ino) { 740 diag &= 2; 741 found = 1; 742 break; 743 } 744 } 745 746 if (!found) { 747 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 748 /* Now do PCI interrupts. */ 749 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 750 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 751 diag >>= 8) { 752 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 753 (intrmap == PSR_PCIA2_INT_MAP || 754 intrmap == PSR_PCIA3_INT_MAP)) 755 continue; 756 if (((PSYCHO_READ8(sc, intrmap) ^ ino) & 0x3c) == 0) { 757 intrclr += 8 * (ino & 3); 758 diag = (diag >> ((ino & 3) * 2)) & 2; 759 found = 1; 760 break; 761 } 762 } 763 } 764 if (intrmapptr != NULL) 765 *intrmapptr = intrmap; 766 if (intrclrptr != NULL) 767 *intrclrptr = intrclr; 768 if (intrdiagptr != NULL) 769 *intrdiagptr = diag; 770 return (found); 771} 772 773/* 774 * Interrupt handlers 775 */ 776static int 777psycho_ue(void *arg) 778{ 779 struct psycho_softc *sc = arg; 780 uint64_t afar, afsr; 781 782 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 783 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 784 /* 785 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 786 * the AFAR to be set to the physical address of the TTE entry that 787 * was invalid/write protected. Call into the iommu code to have 788 * them decoded to virtual I/O addresses. 789 */ 790 if ((afsr & UEAFSR_P_DTE) != 0) 791 iommu_decode_fault(sc->sc_is, afar); 792 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx", 793 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 794 return (FILTER_HANDLED); 795} 796 797static int 798psycho_ce(void *arg) 799{ 800 struct psycho_softc *sc = arg; 801 uint64_t afar, afsr; 802 803 mtx_lock_spin(sc->sc_mtx); 804 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 805 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 806 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx " 807 "AFSR %#lx\n", (u_long)afar, (u_long)afsr); 808 /* Clear the error bits that we caught. */ 809 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr & CEAFSR_ERRMASK); 810 mtx_unlock_spin(sc->sc_mtx); 811 return (FILTER_HANDLED); 812} 813 814static int 815psycho_pci_bus(void *arg) 816{ 817 struct psycho_softc *sc = arg; 818 uint64_t afar, afsr; 819 820 afar = PCICTL_READ8(sc, PCR_AFA); 821 afsr = PCICTL_READ8(sc, PCR_AFS); 822 panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx", 823 device_get_name(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar, 824 (u_long)afsr); 825 return (FILTER_HANDLED); 826} 827 828static int 829psycho_powerfail(void *arg) 830{ 831#ifdef DEBUGGER_ON_POWERFAIL 832 struct psycho_softc *sc = arg; 833 834 kdb_enter(KDB_WHY_POWERFAIL, "powerfail"); 835#else 836 static int shutdown; 837 838 /* As the interrupt is cleared we may be called multiple times. */ 839 if (shutdown != 0) 840 return (FILTER_HANDLED); 841 shutdown++; 842 printf("Power Failure Detected: Shutting down NOW.\n"); 843 shutdown_nice(0); 844#endif 845 return (FILTER_HANDLED); 846} 847 848static void 849psycho_overtemp(void *arg) 850{ 851 static int shutdown; 852 853 /* As the interrupt is cleared we may be called multiple times. */ 854 if (shutdown != 0) 855 return; 856 shutdown++; 857 printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n"); 858 shutdown_nice(RB_POWEROFF); 859} 860 861#ifdef PSYCHO_MAP_WAKEUP 862static int 863psycho_wakeup(void *arg) 864{ 865 struct psycho_softc *sc = arg; 866 867 /* Gee, we don't really have a framework to deal with this properly. */ 868 device_printf(sc->sc_dev, "power management wakeup\n"); 869 return (FILTER_HANDLED); 870} 871#endif /* PSYCHO_MAP_WAKEUP */ 872 873static void 874psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase) 875{ 876 char *name; 877 struct iommu_state *is = sc->sc_is; 878 879 /* Punch in our copies. */ 880 is->is_bustag = rman_get_bustag(sc->sc_mem_res); 881 is->is_bushandle = rman_get_bushandle(sc->sc_mem_res); 882 is->is_iommu = PSR_IOMMU; 883 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 884 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 885 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 886 is->is_dva = PSR_IOMMU_SVADIAG; 887 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 888 889 /* Give us a nice name... */ 890 name = malloc(32, M_DEVBUF, M_NOWAIT); 891 if (name == NULL) 892 panic("%s: could not malloc iommu name", __func__); 893 snprintf(name, 32, "%s dvma", device_get_nameunit(sc->sc_dev)); 894 895 iommu_init(name, is, tsbsize, dvmabase, 0); 896} 897 898static int 899psycho_maxslots(device_t dev) 900{ 901 902 /* XXX: is this correct? */ 903 return (PCI_SLOTMAX); 904} 905 906static uint32_t 907psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 908 int width) 909{ 910 struct psycho_softc *sc; 911 bus_space_handle_t bh; 912 u_long offset = 0; 913 uint8_t byte; 914 uint16_t shrt; 915 uint32_t r, wrd; 916 int i; 917 918 sc = device_get_softc(dev); 919 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 920 921 /* 922 * The Hummingbird and Sabre bridges are picky in that they 923 * only allow their config space to be accessed using the 924 * "native" width of the respective register being accessed 925 * and return semi-random other content of their config space 926 * otherwise. Given that the PCI specs don't say anything 927 * about such a (unusual) limitation and lots of stuff expects 928 * to be able to access the contents of the config space at 929 * any width we allow just that. We do this by using a copy 930 * of the header of the bridge (the rest is all zero anyway) 931 * read during attach (expect for PCIR_STATUS) in order to 932 * simplify things. 933 * The Psycho bridges contain a dupe of their header at 0x80 934 * which we nullify that way also. 935 */ 936 if (bus == sc->sc_pci_secbus && slot == PCS_DEVICE && 937 func == PCS_FUNC) { 938 if (offset % width != 0) 939 return (-1); 940 941 if (reg >= sizeof(sc->sc_pci_hpbcfg)) 942 return (0); 943 944 if ((reg < PCIR_STATUS && reg + width > PCIR_STATUS) || 945 reg == PCIR_STATUS || reg == PCIR_STATUS + 1) 946 le16enc(&sc->sc_pci_hpbcfg[PCIR_STATUS], 947 bus_space_read_2(sc->sc_pci_cfgt, bh, 948 PSYCHO_CONF_OFF(sc->sc_pci_secbus, 949 PCS_DEVICE, PCS_FUNC, PCIR_STATUS))); 950 951 switch (width) { 952 case 1: 953 return (sc->sc_pci_hpbcfg[reg]); 954 case 2: 955 return (le16dec(&sc->sc_pci_hpbcfg[reg])); 956 case 4: 957 return (le32dec(&sc->sc_pci_hpbcfg[reg])); 958 } 959 } 960 961 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 962 switch (width) { 963 case 1: 964 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 965 r = byte; 966 break; 967 case 2: 968 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 969 r = shrt; 970 break; 971 case 4: 972 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 973 r = wrd; 974 break; 975 default: 976 panic("%s: bad width", __func__); 977 } 978 979 if (i) { 980#ifdef PSYCHO_DEBUG 981 printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 982 __func__, bus, slot, func, reg); 983#endif 984 r = -1; 985 } 986 return (r); 987} 988 989static void 990psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 991 uint32_t val, int width) 992{ 993 struct psycho_softc *sc; 994 bus_space_handle_t bh; 995 u_long offset = 0; 996 997 sc = device_get_softc(dev); 998 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 999 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1000 switch (width) { 1001 case 1: 1002 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 1003 break; 1004 case 2: 1005 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 1006 break; 1007 case 4: 1008 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 1009 break; 1010 default: 1011 panic("%s: bad width", __func__); 1012 } 1013} 1014 1015static int 1016psycho_route_interrupt(device_t bridge, device_t dev, int pin) 1017{ 1018 struct psycho_softc *sc; 1019 struct ofw_pci_register reg; 1020 bus_addr_t intrmap; 1021 ofw_pci_intr_t pintr, mintr; 1022 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 1023 1024 sc = device_get_softc(bridge); 1025 pintr = pin; 1026 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, 1027 sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) 1028 return (mintr); 1029 /* 1030 * If this is outside of the range for an intpin, it's likely a full 1031 * INO, and no mapping is required at all; this happens on the U30, 1032 * where there's no interrupt map at the Psycho node. Fortunately, 1033 * there seem to be no INOs in the intpin range on this boxen, so 1034 * this easy heuristics will do. 1035 */ 1036 if (pin > 4) 1037 return (pin); 1038 /* 1039 * Guess the INO; we always assume that this is a non-OBIO 1040 * device, and that pin is a "real" intpin number. Determine 1041 * the mapping register to be used by the slot number. 1042 * We only need to do this on E450s, it seems; here, the slot numbers 1043 * for bus A are one-based, while those for bus B seemingly have an 1044 * offset of 2 (hence the factor of 3 below). 1045 */ 1046 intrmap = PSR_PCIA0_INT_MAP + 1047 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half); 1048 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1; 1049 device_printf(bridge, "guessing interrupt %d for device %d.%d pin %d\n", 1050 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin); 1051 return (mintr); 1052} 1053 1054static int 1055psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1056{ 1057 struct psycho_softc *sc; 1058 1059 sc = device_get_softc(dev); 1060 switch (which) { 1061 case PCIB_IVAR_DOMAIN: 1062 *result = device_get_unit(dev); 1063 return (0); 1064 case PCIB_IVAR_BUS: 1065 *result = sc->sc_pci_secbus; 1066 return (0); 1067 } 1068 return (ENOENT); 1069} 1070 1071static int 1072psycho_dmasync(void *arg) 1073{ 1074 struct psycho_dmasync *pds = arg; 1075 1076 (void)PCIB_READ_CONFIG(pds->pds_ppb, pds->pds_bus, pds->pds_slot, 1077 pds->pds_func, PCIR_VENDOR, 2); 1078 (void)PSYCHO_READ8(pds->pds_sc, PSR_DMA_WRITE_SYNC); 1079 return (pds->pds_handler(pds->pds_arg)); 1080} 1081 1082static void 1083psycho_intr_enable(void *arg) 1084{ 1085 struct intr_vector *iv = arg; 1086 struct psycho_icarg *pica = iv->iv_icarg; 1087 1088 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, 1089 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1090} 1091 1092static void 1093psycho_intr_disable(void *arg) 1094{ 1095 struct intr_vector *iv = arg; 1096 struct psycho_icarg *pica = iv->iv_icarg; 1097 1098 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, iv->iv_vec); 1099} 1100 1101static void 1102psycho_intr_eoi(void *arg) 1103{ 1104 struct intr_vector *iv = arg; 1105 struct psycho_icarg *pica = iv->iv_icarg; 1106 1107 PSYCHO_WRITE8(pica->pica_sc, pica->pica_clr, 0); 1108} 1109 1110static int 1111psycho_setup_intr(device_t dev, device_t child, struct resource *ires, 1112 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1113 void **cookiep) 1114{ 1115 struct { 1116 int apb:1; 1117 int ppb:1; 1118 } found; 1119 devclass_t pci_devclass; 1120 device_t cdev, pdev, pcidev; 1121 struct psycho_softc *sc; 1122 struct psycho_dmasync *pds; 1123 u_long vec; 1124 int error; 1125 1126 sc = device_get_softc(dev); 1127 /* 1128 * Make sure the vector is fully specified and we registered 1129 * our interrupt controller for it. 1130 */ 1131 vec = rman_get_start(ires); 1132 if (INTIGN(vec) != sc->sc_ign || 1133 intr_vectors[vec].iv_ic != &psycho_ic) { 1134 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1135 return (EINVAL); 1136 } 1137 1138 /* 1139 * The Sabre-APB-combination has a bug where it does not drain 1140 * DMA write data for devices behind additional PCI-PCI bridges 1141 * underneath the APB PCI-PCI bridge. The workaround is to do 1142 * a read on the farest PCI-PCI bridge followed by a read of the 1143 * PCI DMA write sync register of the Sabre. 1144 * XXX installing the wrapper for an affected device and the 1145 * actual workaround in psycho_dmasync() should be moved to 1146 * psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() 1147 * methods, respectively, once DMA tag creation is newbus'ified, 1148 * so the workaround isn't only applied for interrupt handlers 1149 * but also for polling(4) callbacks. 1150 */ 1151 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 1152 pds = malloc(sizeof(*pds), M_DEVBUF, M_NOWAIT | M_ZERO); 1153 if (pds == NULL) 1154 return (ENOMEM); 1155 pcidev = NULL; 1156 found.apb = found.ppb = 0; 1157 pci_devclass = devclass_find("pci"); 1158 for (cdev = child; cdev != dev; cdev = pdev) { 1159 pdev = device_get_parent(cdev); 1160 if (pcidev == NULL) { 1161 if (device_get_devclass(pdev) != pci_devclass) 1162 continue; 1163 pcidev = cdev; 1164 continue; 1165 } 1166 /* 1167 * NB: APB would also match as PCI-PCI bridges. 1168 */ 1169 if (pci_get_vendor(cdev) == 0x108e && 1170 pci_get_device(cdev) == 0x5000) { 1171 found.apb = 1; 1172 break; 1173 } 1174 if (pci_get_class(cdev) == PCIC_BRIDGE && 1175 pci_get_subclass(cdev) == PCIS_BRIDGE_PCI) 1176 found.ppb = 1; 1177 } 1178 if (found.apb && found.ppb && pcidev != NULL) { 1179 pds->pds_sc = sc; 1180 pds->pds_arg = arg; 1181 pds->pds_ppb = 1182 device_get_parent(device_get_parent(pcidev)); 1183 pds->pds_bus = pci_get_bus(pcidev); 1184 pds->pds_slot = pci_get_slot(pcidev); 1185 pds->pds_func = pci_get_function(pcidev); 1186 if (bootverbose) 1187 device_printf(dev, "installed DMA sync " 1188 "workaround for device %d.%d on bus %d\n", 1189 pds->pds_slot, pds->pds_func, 1190 pds->pds_bus); 1191 if (intr == NULL) { 1192 pds->pds_handler = filt; 1193 error = bus_generic_setup_intr(dev, child, 1194 ires, flags, psycho_dmasync, intr, pds, 1195 cookiep); 1196 } else { 1197 pds->pds_handler = (driver_filter_t *)intr; 1198 error = bus_generic_setup_intr(dev, child, 1199 ires, flags, filt, 1200 (driver_intr_t *)psycho_dmasync, pds, 1201 cookiep); 1202 } 1203 } else 1204 error = bus_generic_setup_intr(dev, child, ires, 1205 flags, filt, intr, arg, cookiep); 1206 if (error != 0) { 1207 free(pds, M_DEVBUF); 1208 return (error); 1209 } 1210 pds->pds_cookie = *cookiep; 1211 *cookiep = pds; 1212 return (error); 1213 } 1214 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1215 arg, cookiep)); 1216} 1217 1218static int 1219psycho_teardown_intr(device_t dev, device_t child, struct resource *vec, 1220 void *cookie) 1221{ 1222 struct psycho_softc *sc; 1223 struct psycho_dmasync *pds; 1224 int error; 1225 1226 sc = device_get_softc(dev); 1227 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 1228 pds = cookie; 1229 error = bus_generic_teardown_intr(dev, child, vec, 1230 pds->pds_cookie); 1231 if (error == 0) 1232 free(pds, M_DEVBUF); 1233 return (error); 1234 } 1235 return (bus_generic_teardown_intr(dev, child, vec, cookie)); 1236} 1237 1238static struct resource * 1239psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1240 u_long start, u_long end, u_long count, u_int flags) 1241{ 1242 struct psycho_softc *sc; 1243 struct resource *rv; 1244 struct rman *rm; 1245 bus_space_tag_t bt; 1246 bus_space_handle_t bh; 1247 int needactivate = flags & RF_ACTIVE; 1248 1249 flags &= ~RF_ACTIVE; 1250 1251 sc = device_get_softc(bus); 1252 if (type == SYS_RES_IRQ) { 1253 /* 1254 * XXX: Don't accept blank ranges for now, only single 1255 * interrupts. The other case should not happen with the 1256 * MI PCI code... 1257 * XXX: This may return a resource that is out of the 1258 * range that was specified. Is this correct...? 1259 */ 1260 if (start != end) 1261 panic("%s: XXX: interrupt range", __func__); 1262 start = end = INTMAP_VEC(sc->sc_ign, end); 1263 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, 1264 rid, start, end, count, flags)); 1265 } 1266 switch (type) { 1267 case SYS_RES_MEMORY: 1268 rm = &sc->sc_pci_mem_rman; 1269 bt = sc->sc_pci_memt; 1270 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1271 break; 1272 case SYS_RES_IOPORT: 1273 rm = &sc->sc_pci_io_rman; 1274 bt = sc->sc_pci_iot; 1275 bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1276 break; 1277 default: 1278 return (NULL); 1279 } 1280 1281 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1282 if (rv == NULL) 1283 return (NULL); 1284 rman_set_rid(rv, *rid); 1285 bh += rman_get_start(rv); 1286 rman_set_bustag(rv, bt); 1287 rman_set_bushandle(rv, bh); 1288 1289 if (needactivate) { 1290 if (bus_activate_resource(child, type, *rid, rv)) { 1291 rman_release_resource(rv); 1292 return (NULL); 1293 } 1294 } 1295 1296 return (rv); 1297} 1298 1299static int 1300psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1301 struct resource *r) 1302{ 1303 void *p; 1304 int error; 1305 1306 if (type == SYS_RES_IRQ) 1307 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1308 type, rid, r)); 1309 if (type == SYS_RES_MEMORY) { 1310 /* 1311 * Need to memory-map the device space, as some drivers depend 1312 * on the virtual address being set and useable. 1313 */ 1314 error = sparc64_bus_mem_map(rman_get_bustag(r), 1315 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1316 if (error != 0) 1317 return (error); 1318 rman_set_virtual(r, p); 1319 } 1320 return (rman_activate_resource(r)); 1321} 1322 1323static int 1324psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1325 struct resource *r) 1326{ 1327 1328 if (type == SYS_RES_IRQ) 1329 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1330 type, rid, r)); 1331 if (type == SYS_RES_MEMORY) { 1332 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1333 rman_set_virtual(r, NULL); 1334 } 1335 return (rman_deactivate_resource(r)); 1336} 1337 1338static int 1339psycho_release_resource(device_t bus, device_t child, int type, int rid, 1340 struct resource *r) 1341{ 1342 int error; 1343 1344 if (type == SYS_RES_IRQ) 1345 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1346 type, rid, r)); 1347 if (rman_get_flags(r) & RF_ACTIVE) { 1348 error = bus_deactivate_resource(child, type, rid, r); 1349 if (error) 1350 return (error); 1351 } 1352 return (rman_release_resource(r)); 1353} 1354 1355static bus_dma_tag_t 1356psycho_get_dma_tag(device_t bus, device_t child) 1357{ 1358 struct psycho_softc *sc; 1359 1360 sc = device_get_softc(bus); 1361 return (sc->sc_pci_dmat); 1362} 1363 1364static int 1365psycho_intr_pending(device_t dev, ofw_pci_intr_t intr) 1366{ 1367 struct psycho_softc *sc; 1368 u_long diag; 1369 1370 sc = device_get_softc(dev); 1371 if (psycho_find_intrmap(sc, intr, NULL, NULL, &diag) == 0) { 1372 device_printf(dev, "%s: mapping not found for %d\n", __func__, 1373 intr); 1374 return (0); 1375 } 1376 return (diag != 0); 1377} 1378 1379static phandle_t 1380psycho_get_node(device_t bus, device_t dev) 1381{ 1382 struct psycho_softc *sc; 1383 1384 sc = device_get_softc(bus); 1385 /* We only have one child, the PCI bus, which needs our own node. */ 1386 return (sc->sc_node); 1387} 1388 1389static bus_space_tag_t 1390psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1391{ 1392 bus_space_tag_t bt; 1393 1394 bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF, M_NOWAIT | M_ZERO); 1395 if (bt == NULL) 1396 panic("%s: out of memory", __func__); 1397 1398 bt->bst_cookie = sc; 1399 bt->bst_parent = rman_get_bustag(sc->sc_mem_res); 1400 bt->bst_type = type; 1401 return (bt); 1402} 1403