psycho.c revision 174134
1/*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/sparc64/pci/psycho.c 174134 2007-12-01 19:42:33Z marius $"); 35 36/* 37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+' 38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges. 39 */ 40 41#include "opt_ofw_pci.h" 42#include "opt_psycho.h" 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/bus.h> 47#include <sys/endian.h> 48#include <sys/kdb.h> 49#include <sys/kernel.h> 50#include <sys/lock.h> 51#include <sys/malloc.h> 52#include <sys/module.h> 53#include <sys/mutex.h> 54#include <sys/pcpu.h> 55#include <sys/reboot.h> 56#include <sys/rman.h> 57 58#include <dev/ofw/ofw_bus.h> 59#include <dev/ofw/ofw_pci.h> 60#include <dev/ofw/openfirm.h> 61 62#include <machine/bus.h> 63#include <machine/bus_common.h> 64#include <machine/bus_private.h> 65#include <machine/iommureg.h> 66#include <machine/iommuvar.h> 67#include <machine/ofw_bus.h> 68#include <machine/resource.h> 69#include <machine/ver.h> 70 71#include <dev/pci/pcireg.h> 72#include <dev/pci/pcivar.h> 73 74#include <sparc64/pci/ofw_pci.h> 75#include <sparc64/pci/psychoreg.h> 76#include <sparc64/pci/psychovar.h> 77 78#include "pcib_if.h" 79 80static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *, 81 const char *); 82static const struct psycho_desc *psycho_get_desc(device_t); 83static void psycho_set_intr(struct psycho_softc *, u_int, bus_addr_t, 84 driver_filter_t, driver_intr_t); 85static int psycho_find_intrmap(struct psycho_softc *, u_int, bus_addr_t *, 86 bus_addr_t *, u_long *); 87static driver_filter_t psycho_dmasync; 88static void psycho_intr_enable(void *); 89static void psycho_intr_disable(void *); 90static void psycho_intr_eoi(void *); 91static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 92 93/* Interrupt handlers */ 94static driver_filter_t psycho_ue; 95static driver_filter_t psycho_ce; 96static driver_filter_t psycho_pci_bus; 97static driver_filter_t psycho_powerfail; 98static driver_intr_t psycho_overtemp; 99#ifdef PSYCHO_MAP_WAKEUP 100static driver_filter_t psycho_wakeup; 101#endif 102 103/* IOMMU support */ 104static void psycho_iommu_init(struct psycho_softc *, int, uint32_t); 105 106/* 107 * Methods 108 */ 109static device_probe_t psycho_probe; 110static device_attach_t psycho_attach; 111static bus_read_ivar_t psycho_read_ivar; 112static bus_setup_intr_t psycho_setup_intr; 113static bus_teardown_intr_t psycho_teardown_intr; 114static bus_alloc_resource_t psycho_alloc_resource; 115static bus_activate_resource_t psycho_activate_resource; 116static bus_deactivate_resource_t psycho_deactivate_resource; 117static bus_release_resource_t psycho_release_resource; 118static bus_get_dma_tag_t psycho_get_dma_tag; 119static pcib_maxslots_t psycho_maxslots; 120static pcib_read_config_t psycho_read_config; 121static pcib_write_config_t psycho_write_config; 122static pcib_route_interrupt_t psycho_route_interrupt; 123static ofw_pci_intr_pending_t psycho_intr_pending; 124static ofw_bus_get_node_t psycho_get_node; 125static ofw_pci_alloc_busno_t psycho_alloc_busno; 126static ofw_pci_adjust_busrange_t psycho_adjust_busrange; 127 128static device_method_t psycho_methods[] = { 129 /* Device interface */ 130 DEVMETHOD(device_probe, psycho_probe), 131 DEVMETHOD(device_attach, psycho_attach), 132 DEVMETHOD(device_shutdown, bus_generic_shutdown), 133 DEVMETHOD(device_suspend, bus_generic_suspend), 134 DEVMETHOD(device_resume, bus_generic_resume), 135 136 /* Bus interface */ 137 DEVMETHOD(bus_print_child, bus_generic_print_child), 138 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 139 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 140 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 141 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 142 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 143 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 144 DEVMETHOD(bus_release_resource, psycho_release_resource), 145 DEVMETHOD(bus_get_dma_tag, psycho_get_dma_tag), 146 147 /* pcib interface */ 148 DEVMETHOD(pcib_maxslots, psycho_maxslots), 149 DEVMETHOD(pcib_read_config, psycho_read_config), 150 DEVMETHOD(pcib_write_config, psycho_write_config), 151 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 152 153 /* ofw_bus interface */ 154 DEVMETHOD(ofw_bus_get_node, psycho_get_node), 155 156 /* ofw_pci interface */ 157 DEVMETHOD(ofw_pci_intr_pending, psycho_intr_pending), 158 DEVMETHOD(ofw_pci_alloc_busno, psycho_alloc_busno), 159 DEVMETHOD(ofw_pci_adjust_busrange, psycho_adjust_busrange), 160 161 { 0, 0 } 162}; 163 164static devclass_t psycho_devclass; 165 166DEFINE_CLASS_0(pcib, psycho_driver, psycho_methods, 167 sizeof(struct psycho_softc)); 168DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 169 170static SLIST_HEAD(, psycho_softc) psycho_softcs = 171 SLIST_HEAD_INITIALIZER(psycho_softcs); 172 173static uint8_t psycho_pci_bus_cnt; 174 175static const struct intr_controller psycho_ic = { 176 psycho_intr_enable, 177 psycho_intr_disable, 178 psycho_intr_eoi 179}; 180 181struct psycho_icarg { 182 struct psycho_softc *pica_sc; 183 bus_addr_t pica_map; 184 bus_addr_t pica_clr; 185}; 186 187struct psycho_dmasync { 188 struct psycho_softc *pds_sc; 189 driver_filter_t *pds_handler; /* handler to call */ 190 void *pds_arg; /* argument for the handler */ 191 void *pds_cookie; /* parent bus int. cookie */ 192 device_t pds_ppb; /* farest PCI-PCI bridge */ 193 uint8_t pds_bus; /* bus of farest PCI device */ 194 uint8_t pds_slot; /* slot of farest PCI device */ 195 uint8_t pds_func; /* func. of farest PCI device */ 196}; 197 198#define PSYCHO_READ8(sc, off) \ 199 bus_read_8((sc)->sc_mem_res, (off)) 200#define PSYCHO_WRITE8(sc, off, v) \ 201 bus_write_8((sc)->sc_mem_res, (off), (v)) 202#define PCICTL_READ8(sc, off) \ 203 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 204#define PCICTL_WRITE8(sc, off, v) \ 205 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 206 207/* 208 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 209 * single PCI bus and does not have a streaming buffer. It often has an APB 210 * (advanced PCI bridge) connected to it, which was designed specifically for 211 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 212 * appears as two "Simba"'s underneath the Sabre. 213 * 214 * "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's 215 * basically the same as Sabre but without an APB underneath it. 216 * 217 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA bus 218 * and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while 219 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 220 * will usually find a "Psycho+" since I don't think the original "Psycho" 221 * ever shipped, and if it did it would be in the U30. 222 * 223 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are 224 * both part of the same IC, they only have a single register space. As such, 225 * they need to be configured together, even though the autoconfiguration will 226 * attach them separately. 227 * 228 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often 229 * as pci1 and pci2, although they have been implemented with other PCI bus 230 * numbers on some machines. 231 * 232 * On UltraII machines, there can be any number of "Psycho+" ICs, each 233 * providing two PCI buses. 234 */ 235 236#define OFW_PCI_TYPE "pci" 237 238struct psycho_desc { 239 const char *pd_string; 240 int pd_mode; 241 const char *pd_name; 242}; 243 244static const struct psycho_desc psycho_compats[] = { 245 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 246 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" }, 247 { "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" }, 248 { NULL, 0, NULL } 249}; 250 251static const struct psycho_desc psycho_models[] = { 252 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 253 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 254 { NULL, 0, NULL } 255}; 256 257static const struct psycho_desc * 258psycho_find_desc(const struct psycho_desc *table, const char *string) 259{ 260 const struct psycho_desc *desc; 261 262 if (string == NULL) 263 return (NULL); 264 for (desc = table; desc->pd_string != NULL; desc++) 265 if (strcmp(desc->pd_string, string) == 0) 266 return (desc); 267 return (NULL); 268} 269 270static const struct psycho_desc * 271psycho_get_desc(device_t dev) 272{ 273 const struct psycho_desc *rv; 274 275 rv = psycho_find_desc(psycho_models, ofw_bus_get_model(dev)); 276 if (rv == NULL) 277 rv = psycho_find_desc(psycho_compats, ofw_bus_get_compat(dev)); 278 return (rv); 279} 280 281static int 282psycho_probe(device_t dev) 283{ 284 const char *dtype; 285 286 dtype = ofw_bus_get_type(dev); 287 if (dtype != NULL && strcmp(dtype, OFW_PCI_TYPE) == 0 && 288 psycho_get_desc(dev) != NULL) { 289 device_set_desc(dev, "U2P UPA-PCI bridge"); 290 return (0); 291 } 292 293 return (ENXIO); 294} 295 296static int 297psycho_attach(device_t dev) 298{ 299 char name[sizeof("pci108e,1000")]; 300 struct psycho_icarg *pica; 301 struct psycho_softc *asc, *sc, *osc; 302 struct ofw_pci_ranges *range; 303 const struct psycho_desc *desc; 304 bus_addr_t intrclr, intrmap; 305 uint64_t csr, dr; 306 phandle_t child, node; 307 uint32_t dvmabase, psycho_br[2]; 308 int32_t rev; 309 u_int ver; 310 int i, n, nrange, rid; 311 312 node = ofw_bus_get_node(dev); 313 sc = device_get_softc(dev); 314 desc = psycho_get_desc(dev); 315 316 sc->sc_node = node; 317 sc->sc_dev = dev; 318 sc->sc_mode = desc->pd_mode; 319 320 /* 321 * The Psycho gets three register banks: 322 * (0) per-PBM configuration and status registers 323 * (1) per-PBM PCI configuration space, containing only the 324 * PBM 256-byte PCI header 325 * (2) the shared Psycho configuration registers 326 */ 327 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 328 rid = 2; 329 sc->sc_pcictl = 330 bus_get_resource_start(dev, SYS_RES_MEMORY, 0) - 331 bus_get_resource_start(dev, SYS_RES_MEMORY, 2); 332 switch (sc->sc_pcictl) { 333 case PSR_PCICTL0: 334 sc->sc_half = 0; 335 break; 336 case PSR_PCICTL1: 337 sc->sc_half = 1; 338 break; 339 default: 340 panic("%s: bogus PCI control register location", 341 __func__); 342 } 343 } else { 344 rid = 0; 345 sc->sc_pcictl = PSR_PCICTL0; 346 sc->sc_half = 0; 347 } 348 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 349 (sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) | 350 RF_ACTIVE); 351 if (sc->sc_mem_res == NULL) 352 panic("%s: could not allocate registers", __func__); 353 354 /* 355 * Match other Psycho's that are already configured against 356 * the base physical address. This will be the same for a 357 * pair of devices that share register space. 358 */ 359 osc = NULL; 360 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 361 if (rman_get_start(asc->sc_mem_res) == 362 rman_get_start(sc->sc_mem_res)) { 363 /* Found partner. */ 364 osc = asc; 365 break; 366 } 367 } 368 if (osc == NULL) { 369 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 370 M_NOWAIT | M_ZERO); 371 if (sc->sc_mtx == NULL) 372 panic("%s: could not malloc mutex", __func__); 373 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 374 } else { 375 if (mtx_initialized(osc->sc_mtx) == 0) 376 panic("%s: mutex not initialized", __func__); 377 sc->sc_mtx = osc->sc_mtx; 378 } 379 380 /* Clear PCI AFSR. */ 381 PCICTL_WRITE8(sc, PCR_AFS, PCIAFSR_ERRMASK); 382 383 csr = PSYCHO_READ8(sc, PSR_CS); 384 ver = PSYCHO_GCSR_VERS(csr); 385 sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */ 386 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 387 sc->sc_ign = PSYCHO_GCSR_IGN(csr); 388 389 device_printf(dev, "%s, impl %d, version %d, IGN %#x, bus %c\n", 390 desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign, 391 'A' + sc->sc_half); 392 393 /* Set up the PCI control and PCI diagnostic registers. */ 394 395 /* 396 * Revision 0 EBus bridges have a bug which prevents them from 397 * working when bus parking is enabled. 398 */ 399 rev = -1; 400 csr = PCICTL_READ8(sc, PCR_CS); 401 csr &= ~PCICTL_ARB_PARK; 402 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 403 if (OF_getprop(child, "name", name, sizeof(name)) == -1) 404 continue; 405 if ((strcmp(name, "ebus") == 0 || 406 strcmp(name, "pci108e,1000") == 0) && 407 OF_getprop(child, "revision-id", &rev, sizeof(rev)) > 0 && 408 rev == 0) 409 break; 410 } 411 if (rev != 0 && OF_getproplen(node, "no-bus-parking") < 0) 412 csr |= PCICTL_ARB_PARK; 413 414 /* Workarounds for version specific bugs. */ 415 dr = PCICTL_READ8(sc, PCR_DIAG); 416 switch (ver) { 417 case 0: 418 dr |= DIAG_RTRY_DIS; 419 dr &= ~DIAG_DWSYNC_DIS; 420 /* XXX need to also disable rerun of the streaming buffers. */ 421 break; 422 case 1: 423 csr &= ~PCICTL_ARB_PARK; 424 dr |= DIAG_RTRY_DIS | DIAG_DWSYNC_DIS; 425 /* XXX need to also disable rerun of the streaming buffers. */ 426 break; 427 default: 428 dr |= DIAG_DWSYNC_DIS; 429 dr &= ~DIAG_RTRY_DIS; 430 break; 431 } 432 433 csr |= PCICTL_SERR | PCICTL_ERRINTEN | PCICTL_ARB_4; 434 csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN); 435#ifdef PSYCHO_DEBUG 436 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 437 (unsigned long long)PCICTL_READ8(sc, PCR_CS), 438 (unsigned long long)csr); 439#endif 440 PCICTL_WRITE8(sc, PCR_CS, csr); 441 442 dr &= ~DIAG_ISYNC_DIS; 443#ifdef PSYCHO_DEBUG 444 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 445 (unsigned long long)PCICTL_READ8(sc, PCR_DIAG), 446 (unsigned long long)dr); 447#endif 448 PCICTL_WRITE8(sc, PCR_DIAG, dr); 449 450 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 451 /* Use the PROM preset for now. */ 452 csr = PCICTL_READ8(sc, PCR_TAS); 453 if (csr == 0) 454 panic("%s: Hummingbird/Sabre TAS not initialized.", 455 __func__); 456 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT; 457 } else 458 dvmabase = -1; 459 460 /* Initialize memory and I/O rmans. */ 461 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 462 sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports"; 463 if (rman_init(&sc->sc_pci_io_rman) != 0 || 464 rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0) 465 panic("%s: failed to set up I/O rman", __func__); 466 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 467 sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory"; 468 if (rman_init(&sc->sc_pci_mem_rman) != 0 || 469 rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 470 panic("%s: failed to set up memory rman", __func__); 471 472 nrange = OF_getprop_alloc(node, "ranges", sizeof(*range), 473 (void **)&range); 474 /* 475 * Make sure that the expected ranges are present. The OFW_PCI_CS_MEM64 476 * one is not currently used though. 477 */ 478 if (nrange != PSYCHO_NRANGE) 479 panic("%s: unsupported number of ranges", __func__); 480 /* 481 * Find the addresses of the various bus spaces. 482 * There should not be multiple ones of one kind. 483 * The physical start addresses of the ranges are the configuration, 484 * memory and I/O handles. 485 */ 486 for (n = 0; n < PSYCHO_NRANGE; n++) { 487 i = OFW_PCI_RANGE_CS(&range[n]); 488 if (sc->sc_pci_bh[i] != 0) 489 panic("%s: duplicate range for space %d", __func__, i); 490 sc->sc_pci_bh[i] = OFW_PCI_RANGE_PHYS(&range[n]); 491 } 492 free(range, M_OFWPROP); 493 494 /* Register the softc, this is needed for paired Psychos. */ 495 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 496 497 /* 498 * If we're a Hummingbird/Sabre or the first of a pair of Psychos 499 * to arrive here, do the interrupt setup and start up the IOMMU. 500 */ 501 if (osc == NULL) { 502 /* 503 * Hunt through all the interrupt mapping regs and register 504 * our interrupt controller for the corresponding interrupt 505 * vectors. 506 */ 507 for (n = 0; n <= PSYCHO_MAX_INO; n++) { 508 if (psycho_find_intrmap(sc, n, &intrmap, &intrclr, 509 NULL) == 0) 510 continue; 511 pica = malloc(sizeof(*pica), M_DEVBUF, M_NOWAIT); 512 if (pica == NULL) 513 panic("%s: could not allocate interrupt " 514 "controller argument", __func__); 515 pica->pica_sc = sc; 516 pica->pica_map = intrmap; 517 pica->pica_clr = intrclr; 518#ifdef PSYCHO_DEBUG 519 /* 520 * Enable all interrupts and clear all interrupt 521 * states. This aids the debugging of interrupt 522 * routing problems. 523 */ 524 device_printf(dev, 525 "intr map (INO %d, %s) %#lx: %#lx, clr: %#lx\n", 526 n, intrmap <= PSR_PCIB3_INT_MAP ? "PCI" : "OBIO", 527 (u_long)intrmap, (u_long)PSYCHO_READ8(sc, intrmap), 528 (u_long)intrclr); 529 PSYCHO_WRITE8(sc, intrmap, INTMAP_VEC(sc->sc_ign, n)); 530 PSYCHO_WRITE8(sc, intrclr, 0); 531 PSYCHO_WRITE8(sc, intrmap, 532 INTMAP_ENABLE(INTMAP_VEC(sc->sc_ign, n), 533 PCPU_GET(mid))); 534#endif 535 if (intr_controller_register(INTMAP_VEC(sc->sc_ign, n), 536 &psycho_ic, pica) != 0) 537 panic("%s: could not register interrupt " 538 "controller for INO %d", __func__, n); 539 } 540 541 /* 542 * Establish handlers for interesting interrupts... 543 * 544 * XXX We need to remember these and remove this to support 545 * hotplug on the UPA/FHC bus. 546 * 547 * XXX Not all controllers have these, but installing them 548 * is better than trying to sort through this mess. 549 */ 550 psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL); 551 psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL); 552#ifdef DEBUGGER_ON_POWERFAIL 553 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, psycho_powerfail, 554 NULL); 555#else 556 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL, 557 (driver_intr_t *)psycho_powerfail); 558#endif 559 /* Psycho-specific initialization */ 560 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 561 /* 562 * Hummingbirds/Sabres do not have the following two 563 * interrupts. 564 */ 565 566 /* 567 * The spare hardware interrupt is used for the 568 * over-temperature interrupt. 569 */ 570 psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP, 571 NULL, psycho_overtemp); 572#ifdef PSYCHO_MAP_WAKEUP 573 /* 574 * psycho_wakeup() doesn't do anything useful right 575 * now. 576 */ 577 psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP, 578 psycho_wakeup, NULL); 579#endif /* PSYCHO_MAP_WAKEUP */ 580 581 /* Initialize the counter-timer. */ 582 sparc64_counter_init(rman_get_bustag(sc->sc_mem_res), 583 rman_get_bushandle(sc->sc_mem_res), PSR_TC0); 584 } 585 586 /* 587 * Set up IOMMU and PCI configuration if we're the first 588 * of a pair of Psycho's to arrive here. 589 * 590 * We should calculate a TSB size based on amount of RAM 591 * and number of bus controllers and number and type of 592 * child devices. 593 * 594 * For the moment, 32KB should be more than enough. 595 */ 596 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 597 M_NOWAIT | M_ZERO); 598 if (sc->sc_is == NULL) 599 panic("%s: malloc iommu_state failed", __func__); 600 if (sc->sc_mode == PSYCHO_MODE_SABRE) 601 sc->sc_is->is_pmaxaddr = 602 IOMMU_MAXADDR(SABRE_IOMMU_BITS); 603 else 604 sc->sc_is->is_pmaxaddr = 605 IOMMU_MAXADDR(PSYCHO_IOMMU_BITS); 606 sc->sc_is->is_sb[0] = 0; 607 sc->sc_is->is_sb[1] = 0; 608 if (OF_getproplen(node, "no-streaming-cache") < 0) 609 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 610 psycho_iommu_init(sc, 3, dvmabase); 611 } else { 612 /* Just copy IOMMU state, config tag and address. */ 613 sc->sc_is = osc->sc_is; 614 if (OF_getproplen(node, "no-streaming-cache") < 0) 615 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 616 iommu_reset(sc->sc_is); 617 } 618 619 /* 620 * Register a PCI bus error interrupt handler according to which 621 * half this is. Hummingbird/Sabre don't have a PCI bus B error 622 * interrupt but they are also only used for PCI bus A. 623 */ 624 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP : 625 PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL); 626 627 /* Allocate our tags. */ 628 sc->sc_pci_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 629 sc->sc_pci_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 630 sc->sc_pci_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 631 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 632 sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr, 633 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0) 634 panic("%s: bus_dma_tag_create failed", __func__); 635 /* Customize the tag. */ 636 sc->sc_pci_dmat->dt_cookie = sc->sc_is; 637 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 638 639 /* 640 * Get the bus range from the firmware; it is used solely for obtaining 641 * the inital bus number, and cannot be trusted on all machines. 642 */ 643 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br)); 644 if (n == -1) 645 panic("%s: could not get bus-range", __func__); 646 if (n != sizeof(psycho_br)) 647 panic("%s: broken bus-range (%d)", __func__, n); 648 649 /* Clear PCI status error bits. */ 650 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, 651 PCIR_STATUS, PCIM_STATUS_PERR | PCIM_STATUS_RMABORT | 652 PCIM_STATUS_RTABORT | PCIM_STATUS_STABORT | 653 PCIM_STATUS_PERRREPORT, 2); 654 655 /* 656 * Set the latency timer register as this isn't always done by the 657 * firmware. 658 */ 659 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, 660 PCIR_LATTIMER, 64, 1); 661 662 sc->sc_pci_secbus = sc->sc_pci_subbus = psycho_alloc_busno(dev); 663 /* 664 * Program the bus range registers. 665 * NOTE: for the Psycho, the second write changes the bus number the 666 * Psycho itself uses for it's configuration space, so these 667 * writes must be kept in this order! 668 * The Hummingbird/Sabre always uses bus 0, but there only can be one 669 * Hummingbird/Sabre per machine. 670 */ 671 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SUBBUS, 672 sc->sc_pci_subbus, 1); 673 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SECBUS, 674 sc->sc_pci_secbus, 1); 675 676 for (n = PCIR_VENDOR; n < PCIR_STATUS; n += sizeof(uint16_t)) 677 le16enc(&sc->sc_pci_hpbcfg[n], bus_space_read_2( 678 sc->sc_pci_cfgt, sc->sc_pci_bh[OFW_PCI_CS_CONFIG], 679 PSYCHO_CONF_OFF(sc->sc_pci_secbus, PCS_DEVICE, 680 PCS_FUNC, n))); 681 for (n = PCIR_REVID; n <= PCIR_BIST; n += sizeof(uint8_t)) 682 sc->sc_pci_hpbcfg[n] = bus_space_read_1(sc->sc_pci_cfgt, 683 sc->sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF( 684 sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, n)); 685 686 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 687 /* 688 * On E250 the interrupt map entry for the EBus bridge is wrong, 689 * causing incorrect interrupts to be assigned to some devices on 690 * the EBus. Work around it by changing our copy of the interrupt 691 * map mask to perform a full comparison of the INO. That way 692 * the interrupt map entry for the EBus bridge won't match at all 693 * and the INOs specified in the "interrupts" properties of the 694 * EBus devices will be used directly instead. 695 */ 696 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 && 697 sc->sc_pci_iinfo.opi_imapmsk != NULL) 698 *(ofw_pci_intr_t *)(&sc->sc_pci_iinfo.opi_imapmsk[ 699 sc->sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK; 700 701 device_add_child(dev, "pci", sc->sc_pci_secbus); 702 return (bus_generic_attach(dev)); 703} 704 705static void 706psycho_set_intr(struct psycho_softc *sc, u_int index, bus_addr_t intrmap, 707 driver_filter_t filt, driver_intr_t intr) 708{ 709 u_long vec; 710 int rid; 711 712 rid = index; 713 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ, 714 &rid, RF_ACTIVE); 715 if (sc->sc_irq_res[index] == NULL || 716 INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) != sc->sc_ign || 717 INTVEC(PSYCHO_READ8(sc, intrmap)) != vec || 718 intr_vectors[vec].iv_ic != &psycho_ic || 719 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], INTR_TYPE_MISC, 720 filt, intr, sc, &sc->sc_ihand[index]) != 0) 721 panic("%s: failed to set up interrupt %d", __func__, index); 722} 723 724static int 725psycho_find_intrmap(struct psycho_softc *sc, u_int ino, bus_addr_t *intrmapptr, 726 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 727{ 728 bus_addr_t intrclr, intrmap; 729 uint64_t diag; 730 int found; 731 732 /* 733 * XXX we only compare INOs rather than INRs since the firmware may 734 * not provide the IGN and the IGN is constant for all devices on 735 * that PCI controller. 736 * This could cause problems for the FFB/external interrupt which 737 * has a full vector that can be set arbitrarily. 738 */ 739 740 if (ino > PSYCHO_MAX_INO) { 741 device_printf(sc->sc_dev, "out of range INO %d requested\n", 742 ino); 743 return (0); 744 } 745 746 found = 0; 747 /* Hunt through OBIO first. */ 748 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 749 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 750 intrmap <= PSR_PWRMGT_INT_MAP; intrmap += 8, intrclr += 8, 751 diag >>= 2) { 752 if (sc->sc_mode == PSYCHO_MODE_SABRE && 753 (intrmap == PSR_TIMER0_INT_MAP || 754 intrmap == PSR_TIMER1_INT_MAP || 755 intrmap == PSR_PCIBERR_INT_MAP || 756 intrmap == PSR_PWRMGT_INT_MAP)) 757 continue; 758 if (INTINO(PSYCHO_READ8(sc, intrmap)) == ino) { 759 diag &= 2; 760 found = 1; 761 break; 762 } 763 } 764 765 if (!found) { 766 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 767 /* Now do PCI interrupts. */ 768 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 769 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 770 diag >>= 8) { 771 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 772 (intrmap == PSR_PCIA2_INT_MAP || 773 intrmap == PSR_PCIA3_INT_MAP)) 774 continue; 775 if (((PSYCHO_READ8(sc, intrmap) ^ ino) & 0x3c) == 0) { 776 intrclr += 8 * (ino & 3); 777 diag = (diag >> ((ino & 3) * 2)) & 2; 778 found = 1; 779 break; 780 } 781 } 782 } 783 if (intrmapptr != NULL) 784 *intrmapptr = intrmap; 785 if (intrclrptr != NULL) 786 *intrclrptr = intrclr; 787 if (intrdiagptr != NULL) 788 *intrdiagptr = diag; 789 return (found); 790} 791 792/* 793 * Interrupt handlers 794 */ 795static int 796psycho_ue(void *arg) 797{ 798 struct psycho_softc *sc = arg; 799 uint64_t afar, afsr; 800 801 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 802 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 803 /* 804 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 805 * the AFAR to be set to the physical address of the TTE entry that 806 * was invalid/write protected. Call into the iommu code to have 807 * them decoded to virtual I/O addresses. 808 */ 809 if ((afsr & UEAFSR_P_DTE) != 0) 810 iommu_decode_fault(sc->sc_is, afar); 811 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx", 812 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 813 return (FILTER_HANDLED); 814} 815 816static int 817psycho_ce(void *arg) 818{ 819 struct psycho_softc *sc = arg; 820 uint64_t afar, afsr; 821 822 mtx_lock_spin(sc->sc_mtx); 823 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 824 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 825 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx " 826 "AFSR %#lx\n", (u_long)afar, (u_long)afsr); 827 /* Clear the error bits that we caught. */ 828 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr & CEAFSR_ERRMASK); 829 mtx_unlock_spin(sc->sc_mtx); 830 return (FILTER_HANDLED); 831} 832 833static int 834psycho_pci_bus(void *arg) 835{ 836 struct psycho_softc *sc = arg; 837 uint64_t afar, afsr; 838 839 afar = PCICTL_READ8(sc, PCR_AFA); 840 afsr = PCICTL_READ8(sc, PCR_AFS); 841 panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx", 842 device_get_name(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar, 843 (u_long)afsr); 844 return (FILTER_HANDLED); 845} 846 847static int 848psycho_powerfail(void *arg) 849{ 850#ifdef DEBUGGER_ON_POWERFAIL 851 struct psycho_softc *sc = arg; 852 853 kdb_enter("powerfail"); 854#else 855 static int shutdown; 856 857 /* As the interrupt is cleared we may be called multiple times. */ 858 if (shutdown != 0) 859 return (FILTER_HANDLED); 860 shutdown++; 861 printf("Power Failure Detected: Shutting down NOW.\n"); 862 shutdown_nice(0); 863#endif 864 return (FILTER_HANDLED); 865} 866 867static void 868psycho_overtemp(void *arg) 869{ 870 static int shutdown; 871 872 /* As the interrupt is cleared we may be called multiple times. */ 873 if (shutdown != 0) 874 return; 875 shutdown++; 876 printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n"); 877 shutdown_nice(RB_POWEROFF); 878} 879 880#ifdef PSYCHO_MAP_WAKEUP 881static int 882psycho_wakeup(void *arg) 883{ 884 struct psycho_softc *sc = arg; 885 886 /* Gee, we don't really have a framework to deal with this properly. */ 887 device_printf(sc->sc_dev, "power management wakeup\n"); 888 return (FILTER_HANDLED); 889} 890#endif /* PSYCHO_MAP_WAKEUP */ 891 892static void 893psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase) 894{ 895 char *name; 896 struct iommu_state *is = sc->sc_is; 897 898 /* Punch in our copies. */ 899 is->is_bustag = rman_get_bustag(sc->sc_mem_res); 900 is->is_bushandle = rman_get_bushandle(sc->sc_mem_res); 901 is->is_iommu = PSR_IOMMU; 902 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 903 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 904 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 905 is->is_dva = PSR_IOMMU_SVADIAG; 906 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 907 908 /* Give us a nice name... */ 909 name = malloc(32, M_DEVBUF, M_NOWAIT); 910 if (name == NULL) 911 panic("%s: could not malloc iommu name", __func__); 912 snprintf(name, 32, "%s dvma", device_get_nameunit(sc->sc_dev)); 913 914 iommu_init(name, is, tsbsize, dvmabase, 0); 915} 916 917static int 918psycho_maxslots(device_t dev) 919{ 920 921 /* XXX: is this correct? */ 922 return (PCI_SLOTMAX); 923} 924 925static uint32_t 926psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 927 int width) 928{ 929 struct psycho_softc *sc; 930 bus_space_handle_t bh; 931 u_long offset = 0; 932 uint8_t byte; 933 uint16_t shrt; 934 uint32_t r, wrd; 935 int i; 936 937 sc = device_get_softc(dev); 938 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 939 940 /* 941 * The Hummingbird and Sabre bridges are picky in that they 942 * only allow their config space to be accessed using the 943 * "native" width of the respective register being accessed 944 * and return semi-random other content of their config space 945 * otherwise. Given that the PCI specs don't say anything 946 * about such a (unusual) limitation and lots of stuff expects 947 * to be able to access the contents of the config space at 948 * any width we allow just that. We do this by using a copy 949 * of the header of the bridge (the rest is all zero anyway) 950 * read during attach (expect for PCIR_STATUS) in order to 951 * simplify things. 952 * The Psycho bridges contain a dupe of their header at 0x80 953 * which we nullify that way also. 954 */ 955 if (bus == sc->sc_pci_secbus && slot == PCS_DEVICE && 956 func == PCS_FUNC) { 957 if (offset % width != 0) 958 return (-1); 959 960 if (reg >= sizeof(sc->sc_pci_hpbcfg)) 961 return (0); 962 963 if ((reg < PCIR_STATUS && reg + width > PCIR_STATUS) || 964 reg == PCIR_STATUS || reg == PCIR_STATUS + 1) 965 le16enc(&sc->sc_pci_hpbcfg[PCIR_STATUS], 966 bus_space_read_2(sc->sc_pci_cfgt, bh, 967 PSYCHO_CONF_OFF(sc->sc_pci_secbus, 968 PCS_DEVICE, PCS_FUNC, PCIR_STATUS))); 969 970 switch (width) { 971 case 1: 972 return (sc->sc_pci_hpbcfg[reg]); 973 case 2: 974 return (le16dec(&sc->sc_pci_hpbcfg[reg])); 975 case 4: 976 return (le32dec(&sc->sc_pci_hpbcfg[reg])); 977 } 978 } 979 980 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 981 switch (width) { 982 case 1: 983 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 984 r = byte; 985 break; 986 case 2: 987 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 988 r = shrt; 989 break; 990 case 4: 991 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 992 r = wrd; 993 break; 994 default: 995 panic("%s: bad width", __func__); 996 } 997 998 if (i) { 999#ifdef PSYCHO_DEBUG 1000 printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 1001 __func__, bus, slot, func, reg); 1002#endif 1003 r = -1; 1004 } 1005 return (r); 1006} 1007 1008static void 1009psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 1010 uint32_t val, int width) 1011{ 1012 struct psycho_softc *sc; 1013 bus_space_handle_t bh; 1014 u_long offset = 0; 1015 1016 sc = device_get_softc(dev); 1017 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 1018 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1019 switch (width) { 1020 case 1: 1021 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 1022 break; 1023 case 2: 1024 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 1025 break; 1026 case 4: 1027 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 1028 break; 1029 default: 1030 panic("%s: bad width", __func__); 1031 } 1032} 1033 1034static int 1035psycho_route_interrupt(device_t bridge, device_t dev, int pin) 1036{ 1037 struct psycho_softc *sc; 1038 struct ofw_pci_register reg; 1039 bus_addr_t intrmap; 1040 ofw_pci_intr_t pintr, mintr; 1041 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 1042 1043 sc = device_get_softc(bridge); 1044 pintr = pin; 1045 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, 1046 sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) 1047 return (mintr); 1048 /* 1049 * If this is outside of the range for an intpin, it's likely a full 1050 * INO, and no mapping is required at all; this happens on the U30, 1051 * where there's no interrupt map at the Psycho node. Fortunately, 1052 * there seem to be no INOs in the intpin range on this boxen, so 1053 * this easy heuristics will do. 1054 */ 1055 if (pin > 4) 1056 return (pin); 1057 /* 1058 * Guess the INO; we always assume that this is a non-OBIO 1059 * device, and that pin is a "real" intpin number. Determine 1060 * the mapping register to be used by the slot number. 1061 * We only need to do this on E450s, it seems; here, the slot numbers 1062 * for bus A are one-based, while those for bus B seemingly have an 1063 * offset of 2 (hence the factor of 3 below). 1064 */ 1065 intrmap = PSR_PCIA0_INT_MAP + 1066 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half); 1067 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1; 1068 device_printf(bridge, "guessing interrupt %d for device %d.%d pin %d\n", 1069 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin); 1070 return (mintr); 1071} 1072 1073static int 1074psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1075{ 1076 struct psycho_softc *sc; 1077 1078 sc = device_get_softc(dev); 1079 switch (which) { 1080 case PCIB_IVAR_DOMAIN: 1081 *result = 0; 1082 return (0); 1083 case PCIB_IVAR_BUS: 1084 *result = sc->sc_pci_secbus; 1085 return (0); 1086 } 1087 return (ENOENT); 1088} 1089 1090static int 1091psycho_dmasync(void *arg) 1092{ 1093 struct psycho_dmasync *pds = arg; 1094 1095 (void)PCIB_READ_CONFIG(pds->pds_ppb, pds->pds_bus, pds->pds_slot, 1096 pds->pds_func, PCIR_VENDOR, 2); 1097 (void)PSYCHO_READ8(pds->pds_sc, PSR_DMA_WRITE_SYNC); 1098 return (pds->pds_handler(pds->pds_arg)); 1099} 1100 1101static void 1102psycho_intr_enable(void *arg) 1103{ 1104 struct intr_vector *iv = arg; 1105 struct psycho_icarg *pica = iv->iv_icarg; 1106 1107 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, 1108 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1109} 1110 1111static void 1112psycho_intr_disable(void *arg) 1113{ 1114 struct intr_vector *iv = arg; 1115 struct psycho_icarg *pica = iv->iv_icarg; 1116 1117 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, iv->iv_vec); 1118} 1119 1120static void 1121psycho_intr_eoi(void *arg) 1122{ 1123 struct intr_vector *iv = arg; 1124 struct psycho_icarg *pica = iv->iv_icarg; 1125 1126 PSYCHO_WRITE8(pica->pica_sc, pica->pica_clr, 0); 1127} 1128 1129static int 1130psycho_setup_intr(device_t dev, device_t child, struct resource *ires, 1131 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1132 void **cookiep) 1133{ 1134 struct { 1135 int apb:1; 1136 int ppb:1; 1137 } found; 1138 devclass_t pci_devclass; 1139 device_t cdev, pdev, pcidev; 1140 struct psycho_softc *sc; 1141 struct psycho_dmasync *pds; 1142 u_long vec; 1143 int error; 1144 1145 sc = device_get_softc(dev); 1146 /* 1147 * Make sure the vector is fully specified and we registered 1148 * our interrupt controller for it. 1149 */ 1150 vec = rman_get_start(ires); 1151 if (INTIGN(vec) != sc->sc_ign || 1152 intr_vectors[vec].iv_ic != &psycho_ic) { 1153 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1154 return (EINVAL); 1155 } 1156 1157 /* 1158 * The Sabre-APB-combination has a bug where it does not drain 1159 * DMA write data for devices behind additional PCI-PCI bridges 1160 * underneath the APB PCI-PCI bridge. The workaround is to do 1161 * a read on the farest PCI-PCI bridge followed by a read of the 1162 * PCI DMA write sync register of the Sabre. 1163 * XXX installing the wrapper for an affected device and the 1164 * actual workaround in psycho_dmasync() should be moved to 1165 * psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() 1166 * methods, respectively, once DMA tag creation is newbus'ified, 1167 * so the workaround isn't only applied for interrupt handlers 1168 * but also for polling(4) callbacks. 1169 */ 1170 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 1171 pds = malloc(sizeof(*pds), M_DEVBUF, M_NOWAIT | M_ZERO); 1172 if (pds == NULL) 1173 return (ENOMEM); 1174 pcidev = NULL; 1175 found.apb = found.ppb = 0; 1176 pci_devclass = devclass_find("pci"); 1177 for (cdev = child; cdev != dev; cdev = pdev) { 1178 pdev = device_get_parent(cdev); 1179 if (pcidev == NULL) { 1180 if (device_get_devclass(pdev) != pci_devclass) 1181 continue; 1182 pcidev = cdev; 1183 continue; 1184 } 1185 /* 1186 * NB: APB would also match as PCI-PCI bridges. 1187 */ 1188 if (pci_get_vendor(cdev) == 0x108e && 1189 pci_get_device(cdev) == 0x5000) { 1190 found.apb = 1; 1191 break; 1192 } 1193 if (pci_get_class(cdev) == PCIC_BRIDGE && 1194 pci_get_subclass(cdev) == PCIS_BRIDGE_PCI) 1195 found.ppb = 1; 1196 } 1197 if (found.apb && found.ppb && pcidev != NULL) { 1198 pds->pds_sc = sc; 1199 pds->pds_arg = arg; 1200 pds->pds_ppb = 1201 device_get_parent(device_get_parent(pcidev)); 1202 pds->pds_bus = pci_get_bus(pcidev); 1203 pds->pds_slot = pci_get_slot(pcidev); 1204 pds->pds_func = pci_get_function(pcidev); 1205 if (bootverbose) 1206 device_printf(dev, "installed DMA sync " 1207 "workaround for device %d.%d on bus %d\n", 1208 pds->pds_slot, pds->pds_func, 1209 pds->pds_bus); 1210 if (intr == NULL) { 1211 pds->pds_handler = filt; 1212 error = bus_generic_setup_intr(dev, child, 1213 ires, flags, psycho_dmasync, intr, pds, 1214 cookiep); 1215 } else { 1216 pds->pds_handler = (driver_filter_t *)intr; 1217 error = bus_generic_setup_intr(dev, child, 1218 ires, flags, filt, 1219 (driver_intr_t *)psycho_dmasync, pds, 1220 cookiep); 1221 } 1222 } else 1223 error = bus_generic_setup_intr(dev, child, ires, 1224 flags, filt, intr, arg, cookiep); 1225 if (error != 0) { 1226 free(pds, M_DEVBUF); 1227 return (error); 1228 } 1229 pds->pds_cookie = *cookiep; 1230 *cookiep = pds; 1231 return (error); 1232 } 1233 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1234 arg, cookiep)); 1235} 1236 1237static int 1238psycho_teardown_intr(device_t dev, device_t child, struct resource *vec, 1239 void *cookie) 1240{ 1241 struct psycho_softc *sc; 1242 struct psycho_dmasync *pds; 1243 int error; 1244 1245 sc = device_get_softc(dev); 1246 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 1247 pds = cookie; 1248 error = bus_generic_teardown_intr(dev, child, vec, 1249 pds->pds_cookie); 1250 if (error == 0) 1251 free(pds, M_DEVBUF); 1252 return (error); 1253 } 1254 return (bus_generic_teardown_intr(dev, child, vec, cookie)); 1255} 1256 1257static struct resource * 1258psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1259 u_long start, u_long end, u_long count, u_int flags) 1260{ 1261 struct psycho_softc *sc; 1262 struct resource *rv; 1263 struct rman *rm; 1264 bus_space_tag_t bt; 1265 bus_space_handle_t bh; 1266 int needactivate = flags & RF_ACTIVE; 1267 1268 flags &= ~RF_ACTIVE; 1269 1270 sc = device_get_softc(bus); 1271 if (type == SYS_RES_IRQ) { 1272 /* 1273 * XXX: Don't accept blank ranges for now, only single 1274 * interrupts. The other case should not happen with the 1275 * MI PCI code... 1276 * XXX: This may return a resource that is out of the 1277 * range that was specified. Is this correct...? 1278 */ 1279 if (start != end) 1280 panic("%s: XXX: interrupt range", __func__); 1281 start = end = INTMAP_VEC(sc->sc_ign, end); 1282 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, 1283 rid, start, end, count, flags)); 1284 } 1285 switch (type) { 1286 case SYS_RES_MEMORY: 1287 rm = &sc->sc_pci_mem_rman; 1288 bt = sc->sc_pci_memt; 1289 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1290 break; 1291 case SYS_RES_IOPORT: 1292 rm = &sc->sc_pci_io_rman; 1293 bt = sc->sc_pci_iot; 1294 bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1295 break; 1296 default: 1297 return (NULL); 1298 } 1299 1300 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1301 if (rv == NULL) 1302 return (NULL); 1303 rman_set_rid(rv, *rid); 1304 bh += rman_get_start(rv); 1305 rman_set_bustag(rv, bt); 1306 rman_set_bushandle(rv, bh); 1307 1308 if (needactivate) { 1309 if (bus_activate_resource(child, type, *rid, rv)) { 1310 rman_release_resource(rv); 1311 return (NULL); 1312 } 1313 } 1314 1315 return (rv); 1316} 1317 1318static int 1319psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1320 struct resource *r) 1321{ 1322 void *p; 1323 int error; 1324 1325 if (type == SYS_RES_IRQ) 1326 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1327 type, rid, r)); 1328 if (type == SYS_RES_MEMORY) { 1329 /* 1330 * Need to memory-map the device space, as some drivers depend 1331 * on the virtual address being set and useable. 1332 */ 1333 error = sparc64_bus_mem_map(rman_get_bustag(r), 1334 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1335 if (error != 0) 1336 return (error); 1337 rman_set_virtual(r, p); 1338 } 1339 return (rman_activate_resource(r)); 1340} 1341 1342static int 1343psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1344 struct resource *r) 1345{ 1346 1347 if (type == SYS_RES_IRQ) 1348 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1349 type, rid, r)); 1350 if (type == SYS_RES_MEMORY) { 1351 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1352 rman_set_virtual(r, NULL); 1353 } 1354 return (rman_deactivate_resource(r)); 1355} 1356 1357static int 1358psycho_release_resource(device_t bus, device_t child, int type, int rid, 1359 struct resource *r) 1360{ 1361 int error; 1362 1363 if (type == SYS_RES_IRQ) 1364 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1365 type, rid, r)); 1366 if (rman_get_flags(r) & RF_ACTIVE) { 1367 error = bus_deactivate_resource(child, type, rid, r); 1368 if (error) 1369 return (error); 1370 } 1371 return (rman_release_resource(r)); 1372} 1373 1374static bus_dma_tag_t 1375psycho_get_dma_tag(device_t bus, device_t child) 1376{ 1377 struct psycho_softc *sc; 1378 1379 sc = device_get_softc(bus); 1380 return (sc->sc_pci_dmat); 1381} 1382 1383static int 1384psycho_intr_pending(device_t dev, ofw_pci_intr_t intr) 1385{ 1386 struct psycho_softc *sc; 1387 u_long diag; 1388 1389 sc = device_get_softc(dev); 1390 if (psycho_find_intrmap(sc, intr, NULL, NULL, &diag) == 0) { 1391 device_printf(dev, "%s: mapping not found for %d\n", __func__, 1392 intr); 1393 return (0); 1394 } 1395 return (diag != 0); 1396} 1397 1398static phandle_t 1399psycho_get_node(device_t bus, device_t dev) 1400{ 1401 struct psycho_softc *sc; 1402 1403 sc = device_get_softc(bus); 1404 /* We only have one child, the PCI bus, which needs our own node. */ 1405 return (sc->sc_node); 1406} 1407 1408static int 1409psycho_alloc_busno(device_t dev) 1410{ 1411 1412 if (psycho_pci_bus_cnt == PCI_BUSMAX) 1413 panic("%s: out of PCI bus numbers", __func__); 1414 return (psycho_pci_bus_cnt++); 1415} 1416 1417static void 1418psycho_adjust_busrange(device_t dev, u_int subbus) 1419{ 1420 struct psycho_softc *sc; 1421 1422 sc = device_get_softc(dev); 1423 /* If necessary, adjust the subordinate bus number register. */ 1424 if (subbus > sc->sc_pci_subbus) { 1425#ifdef PSYCHO_DEBUG 1426 device_printf(dev, 1427 "adjusting subordinate bus number from %d to %d\n", 1428 sc->sc_pci_subbus, subbus); 1429#endif 1430 sc->sc_pci_subbus = subbus; 1431 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, 1432 PCSR_SUBBUS, subbus, 1); 1433 } 1434} 1435 1436static bus_space_tag_t 1437psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1438{ 1439 bus_space_tag_t bt; 1440 1441 bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF, M_NOWAIT | M_ZERO); 1442 if (bt == NULL) 1443 panic("%s: out of memory", __func__); 1444 1445 bt->bst_cookie = sc; 1446 bt->bst_parent = rman_get_bustag(sc->sc_mem_res); 1447 bt->bst_type = type; 1448 return (bt); 1449} 1450