psycho.c revision 172066
1/*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/sparc64/pci/psycho.c 172066 2007-09-06 19:16:30Z marius $"); 35 36/* 37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+' 38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges. 39 */ 40 41#include "opt_ofw_pci.h" 42#include "opt_psycho.h" 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/bus.h> 47#include <sys/kdb.h> 48#include <sys/kernel.h> 49#include <sys/lock.h> 50#include <sys/malloc.h> 51#include <sys/module.h> 52#include <sys/mutex.h> 53#include <sys/pcpu.h> 54#include <sys/reboot.h> 55#include <sys/rman.h> 56 57#include <dev/ofw/ofw_bus.h> 58#include <dev/ofw/ofw_pci.h> 59#include <dev/ofw/openfirm.h> 60 61#include <machine/bus.h> 62#include <machine/bus_common.h> 63#include <machine/bus_private.h> 64#include <machine/iommureg.h> 65#include <machine/iommuvar.h> 66#include <machine/ofw_bus.h> 67#include <machine/resource.h> 68#include <machine/ver.h> 69 70#include <dev/pci/pcireg.h> 71#include <dev/pci/pcivar.h> 72 73#include <sparc64/pci/ofw_pci.h> 74#include <sparc64/pci/psychoreg.h> 75#include <sparc64/pci/psychovar.h> 76 77#include "pcib_if.h" 78 79static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *, 80 const char *); 81static const struct psycho_desc *psycho_get_desc(device_t); 82static void psycho_set_intr(struct psycho_softc *, u_int, bus_addr_t, 83 driver_filter_t, driver_intr_t); 84static int psycho_find_intrmap(struct psycho_softc *, u_int, bus_addr_t *, 85 bus_addr_t *, u_long *); 86static driver_filter_t psycho_dmasync; 87static void psycho_intr_enable(void *); 88static void psycho_intr_disable(void *); 89static void psycho_intr_eoi(void *); 90static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 91 92/* Interrupt handlers */ 93static driver_filter_t psycho_ue; 94static driver_filter_t psycho_ce; 95static driver_filter_t psycho_pci_bus; 96static driver_filter_t psycho_powerfail; 97static driver_intr_t psycho_overtemp; 98#ifdef PSYCHO_MAP_WAKEUP 99static driver_filter_t psycho_wakeup; 100#endif 101 102/* IOMMU support */ 103static void psycho_iommu_init(struct psycho_softc *, int, uint32_t); 104 105/* 106 * Methods 107 */ 108static device_probe_t psycho_probe; 109static device_attach_t psycho_attach; 110static bus_read_ivar_t psycho_read_ivar; 111static bus_setup_intr_t psycho_setup_intr; 112static bus_teardown_intr_t psycho_teardown_intr; 113static bus_alloc_resource_t psycho_alloc_resource; 114static bus_activate_resource_t psycho_activate_resource; 115static bus_deactivate_resource_t psycho_deactivate_resource; 116static bus_release_resource_t psycho_release_resource; 117static bus_get_dma_tag_t psycho_get_dma_tag; 118static pcib_maxslots_t psycho_maxslots; 119static pcib_read_config_t psycho_read_config; 120static pcib_write_config_t psycho_write_config; 121static pcib_route_interrupt_t psycho_route_interrupt; 122static ofw_pci_intr_pending_t psycho_intr_pending; 123static ofw_bus_get_node_t psycho_get_node; 124static ofw_pci_alloc_busno_t psycho_alloc_busno; 125static ofw_pci_adjust_busrange_t psycho_adjust_busrange; 126 127static device_method_t psycho_methods[] = { 128 /* Device interface */ 129 DEVMETHOD(device_probe, psycho_probe), 130 DEVMETHOD(device_attach, psycho_attach), 131 DEVMETHOD(device_shutdown, bus_generic_shutdown), 132 DEVMETHOD(device_suspend, bus_generic_suspend), 133 DEVMETHOD(device_resume, bus_generic_resume), 134 135 /* Bus interface */ 136 DEVMETHOD(bus_print_child, bus_generic_print_child), 137 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 138 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 139 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 140 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 141 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 142 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 143 DEVMETHOD(bus_release_resource, psycho_release_resource), 144 DEVMETHOD(bus_get_dma_tag, psycho_get_dma_tag), 145 146 /* pcib interface */ 147 DEVMETHOD(pcib_maxslots, psycho_maxslots), 148 DEVMETHOD(pcib_read_config, psycho_read_config), 149 DEVMETHOD(pcib_write_config, psycho_write_config), 150 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 151 152 /* ofw_bus interface */ 153 DEVMETHOD(ofw_bus_get_node, psycho_get_node), 154 155 /* ofw_pci interface */ 156 DEVMETHOD(ofw_pci_intr_pending, psycho_intr_pending), 157 DEVMETHOD(ofw_pci_alloc_busno, psycho_alloc_busno), 158 DEVMETHOD(ofw_pci_adjust_busrange, psycho_adjust_busrange), 159 160 { 0, 0 } 161}; 162 163static driver_t psycho_driver = { 164 "pcib", 165 psycho_methods, 166 sizeof(struct psycho_softc), 167}; 168 169static devclass_t psycho_devclass; 170 171DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 172 173static SLIST_HEAD(, psycho_softc) psycho_softcs = 174 SLIST_HEAD_INITIALIZER(psycho_softcs); 175 176static uint8_t psycho_pci_bus_cnt; 177 178static const struct intr_controller psycho_ic = { 179 psycho_intr_enable, 180 psycho_intr_disable, 181 psycho_intr_eoi 182}; 183 184struct psycho_icarg { 185 struct psycho_softc *pica_sc; 186 bus_addr_t pica_map; 187 bus_addr_t pica_clr; 188}; 189 190struct psycho_dmasync { 191 struct psycho_softc *pds_sc; 192 driver_filter_t *pds_handler; /* handler to call */ 193 void *pds_arg; /* argument for the handler */ 194 void *pds_cookie; /* parent bus int. cookie */ 195 device_t pds_ppb; /* farest PCI-PCI bridge */ 196 uint8_t pds_bus; /* bus of farest PCI device */ 197 uint8_t pds_slot; /* slot of farest PCI device */ 198 uint8_t pds_func; /* func. of farest PCI device */ 199}; 200 201#define PSYCHO_READ8(sc, off) \ 202 bus_read_8((sc)->sc_mem_res, (off)) 203#define PSYCHO_WRITE8(sc, off, v) \ 204 bus_write_8((sc)->sc_mem_res, (off), (v)) 205#define PCICTL_READ8(sc, off) \ 206 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 207#define PCICTL_WRITE8(sc, off, v) \ 208 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 209 210/* 211 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 212 * single PCI bus and does not have a streaming buffer. It often has an APB 213 * (advanced PCI bridge) connected to it, which was designed specifically for 214 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 215 * appears as two "Simba"'s underneath the Sabre. 216 * 217 * "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's 218 * basically the same as Sabre but without an APB underneath it. 219 * 220 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA bus 221 * and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while 222 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 223 * will usually find a "Psycho+" since I don't think the original "Psycho" 224 * ever shipped, and if it did it would be in the U30. 225 * 226 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are 227 * both part of the same IC, they only have a single register space. As such, 228 * they need to be configured together, even though the autoconfiguration will 229 * attach them separately. 230 * 231 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often 232 * as pci1 and pci2, although they have been implemented with other PCI bus 233 * numbers on some machines. 234 * 235 * On UltraII machines, there can be any number of "Psycho+" ICs, each 236 * providing two PCI buses. 237 */ 238 239#define OFW_PCI_TYPE "pci" 240 241struct psycho_desc { 242 const char *pd_string; 243 int pd_mode; 244 const char *pd_name; 245}; 246 247static const struct psycho_desc psycho_compats[] = { 248 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 249 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" }, 250 { "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" }, 251 { NULL, 0, NULL } 252}; 253 254static const struct psycho_desc psycho_models[] = { 255 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 256 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 257 { NULL, 0, NULL } 258}; 259 260static const struct psycho_desc * 261psycho_find_desc(const struct psycho_desc *table, const char *string) 262{ 263 const struct psycho_desc *desc; 264 265 if (string == NULL) 266 return (NULL); 267 for (desc = table; desc->pd_string != NULL; desc++) 268 if (strcmp(desc->pd_string, string) == 0) 269 return (desc); 270 return (NULL); 271} 272 273static const struct psycho_desc * 274psycho_get_desc(device_t dev) 275{ 276 const struct psycho_desc *rv; 277 278 rv = psycho_find_desc(psycho_models, ofw_bus_get_model(dev)); 279 if (rv == NULL) 280 rv = psycho_find_desc(psycho_compats, ofw_bus_get_compat(dev)); 281 return (rv); 282} 283 284static int 285psycho_probe(device_t dev) 286{ 287 const char *dtype; 288 289 dtype = ofw_bus_get_type(dev); 290 if (dtype != NULL && strcmp(dtype, OFW_PCI_TYPE) == 0 && 291 psycho_get_desc(dev) != NULL) { 292 device_set_desc(dev, "U2P UPA-PCI bridge"); 293 return (0); 294 } 295 296 return (ENXIO); 297} 298 299static int 300psycho_attach(device_t dev) 301{ 302 char name[sizeof("pci108e,1000")]; 303 struct psycho_icarg *pica; 304 struct psycho_softc *asc, *sc, *osc; 305 struct ofw_pci_ranges *range; 306 const struct psycho_desc *desc; 307 phandle_t child, node; 308 bus_addr_t intrclr, intrmap; 309 uint64_t csr, dr; 310 uint32_t dvmabase, psycho_br[2]; 311 int32_t rev; 312 u_int ver; 313 int i, n, nrange, rid; 314 315 node = ofw_bus_get_node(dev); 316 sc = device_get_softc(dev); 317 desc = psycho_get_desc(dev); 318 319 sc->sc_node = node; 320 sc->sc_dev = dev; 321 sc->sc_mode = desc->pd_mode; 322 323 /* 324 * The Psycho gets three register banks: 325 * (0) per-PBM configuration and status registers 326 * (1) per-PBM PCI configuration space, containing only the 327 * PBM 256-byte PCI header 328 * (2) the shared Psycho configuration registers 329 */ 330 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 331 rid = 2; 332 sc->sc_pcictl = 333 bus_get_resource_start(dev, SYS_RES_MEMORY, 0) - 334 bus_get_resource_start(dev, SYS_RES_MEMORY, 2); 335 switch (sc->sc_pcictl) { 336 case PSR_PCICTL0: 337 sc->sc_half = 0; 338 break; 339 case PSR_PCICTL1: 340 sc->sc_half = 1; 341 break; 342 default: 343 panic("%s: bogus PCI control register location", 344 __func__); 345 } 346 } else { 347 rid = 0; 348 sc->sc_pcictl = PSR_PCICTL0; 349 sc->sc_half = 0; 350 } 351 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 352 (sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) | 353 RF_ACTIVE); 354 if (sc->sc_mem_res == NULL) 355 panic("%s: could not allocate registers", __func__); 356 357 /* 358 * Match other Psycho's that are already configured against 359 * the base physical address. This will be the same for a 360 * pair of devices that share register space. 361 */ 362 osc = NULL; 363 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 364 if (rman_get_start(asc->sc_mem_res) == 365 rman_get_start(sc->sc_mem_res)) { 366 /* Found partner. */ 367 osc = asc; 368 break; 369 } 370 } 371 if (osc == NULL) { 372 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 373 M_NOWAIT | M_ZERO); 374 if (sc->sc_mtx == NULL) 375 panic("%s: could not malloc mutex", __func__); 376 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 377 } else { 378 if (mtx_initialized(osc->sc_mtx) == 0) 379 panic("%s: mutex not initialized", __func__); 380 sc->sc_mtx = osc->sc_mtx; 381 } 382 383 /* Clear PCI AFSR. */ 384 PCICTL_WRITE8(sc, PCR_AFS, PCIAFSR_ERRMASK); 385 386 csr = PSYCHO_READ8(sc, PSR_CS); 387 ver = PSYCHO_GCSR_VERS(csr); 388 sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */ 389 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 390 sc->sc_ign = PSYCHO_GCSR_IGN(csr); 391 392 device_printf(dev, "%s, impl %d, version %d, IGN %#x, bus %c\n", 393 desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign, 394 'A' + sc->sc_half); 395 396 /* Set up the PCI control and PCI diagnostic registers. */ 397 398 /* 399 * Revision 0 EBus bridges have a bug which prevents them from 400 * working when bus parking is enabled. 401 */ 402 rev = -1; 403 csr = PCICTL_READ8(sc, PCR_CS); 404 csr &= ~PCICTL_ARB_PARK; 405 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 406 if (OF_getprop(child, "name", name, sizeof(name)) == -1) 407 continue; 408 if ((strcmp(name, "ebus") == 0 || 409 strcmp(name, "pci108e,1000") == 0) && 410 OF_getprop(child, "revision-id", &rev, sizeof(rev)) > 0 && 411 rev == 0) 412 break; 413 } 414 if (rev != 0 && OF_getproplen(node, "no-bus-parking") < 0) 415 csr |= PCICTL_ARB_PARK; 416 417 /* Workarounds for version specific bugs. */ 418 dr = PCICTL_READ8(sc, PCR_DIAG); 419 switch (ver) { 420 case 0: 421 dr |= DIAG_RTRY_DIS; 422 dr &= ~DIAG_DWSYNC_DIS; 423 /* XXX need to also disable rerun of the streaming buffers. */ 424 break; 425 case 1: 426 csr &= ~PCICTL_ARB_PARK; 427 dr |= DIAG_RTRY_DIS | DIAG_DWSYNC_DIS; 428 /* XXX need to also disable rerun of the streaming buffers. */ 429 break; 430 default: 431 dr |= DIAG_DWSYNC_DIS; 432 dr &= ~DIAG_RTRY_DIS; 433 break; 434 } 435 436 csr |= PCICTL_SERR | PCICTL_ERRINTEN | PCICTL_ARB_4; 437 csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN); 438#ifdef PSYCHO_DEBUG 439 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 440 (unsigned long long)PCICTL_READ8(sc, PCR_CS), 441 (unsigned long long)csr); 442#endif 443 PCICTL_WRITE8(sc, PCR_CS, csr); 444 445 dr &= ~DIAG_ISYNC_DIS; 446#ifdef PSYCHO_DEBUG 447 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 448 (unsigned long long)PCICTL_READ8(sc, PCR_DIAG), 449 (unsigned long long)dr); 450#endif 451 PCICTL_WRITE8(sc, PCR_DIAG, dr); 452 453 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 454 /* Use the PROM preset for now. */ 455 csr = PCICTL_READ8(sc, PCR_TAS); 456 if (csr == 0) 457 panic("%s: Hummingbird/Sabre TAS not initialized.", 458 __func__); 459 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT; 460 } else 461 dvmabase = -1; 462 463 /* Initialize memory and I/O rmans. */ 464 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 465 sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports"; 466 if (rman_init(&sc->sc_pci_io_rman) != 0 || 467 rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0) 468 panic("%s: failed to set up I/O rman", __func__); 469 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 470 sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory"; 471 if (rman_init(&sc->sc_pci_mem_rman) != 0 || 472 rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 473 panic("%s: failed to set up memory rman", __func__); 474 475 nrange = OF_getprop_alloc(node, "ranges", sizeof(*range), 476 (void **)&range); 477 /* 478 * Make sure that the expected ranges are present. The OFW_PCI_CS_MEM64 479 * one is not currently used though. 480 */ 481 if (nrange != PSYCHO_NRANGE) 482 panic("%s: unsupported number of ranges", __func__); 483 /* 484 * Find the addresses of the various bus spaces. 485 * There should not be multiple ones of one kind. 486 * The physical start addresses of the ranges are the configuration, 487 * memory and I/O handles. 488 */ 489 for (n = 0; n < PSYCHO_NRANGE; n++) { 490 i = OFW_PCI_RANGE_CS(&range[n]); 491 if (sc->sc_pci_bh[i] != 0) 492 panic("%s: duplicate range for space %d", __func__, i); 493 sc->sc_pci_bh[i] = OFW_PCI_RANGE_PHYS(&range[n]); 494 } 495 free(range, M_OFWPROP); 496 497 /* Register the softc, this is needed for paired Psychos. */ 498 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 499 500 /* 501 * If we're a Hummingbird/Sabre or the first of a pair of Psychos 502 * to arrive here, do the interrupt setup and start up the IOMMU. 503 */ 504 if (osc == NULL) { 505 /* 506 * Hunt through all the interrupt mapping regs and register 507 * our interrupt controller for the corresponding interrupt 508 * vectors. 509 */ 510 for (n = 0; n <= PSYCHO_MAX_INO; n++) { 511 if (psycho_find_intrmap(sc, n, &intrmap, &intrclr, 512 NULL) == 0) 513 continue; 514 pica = malloc(sizeof(*pica), M_DEVBUF, M_NOWAIT); 515 if (pica == NULL) 516 panic("%s: could not allocate interrupt " 517 "controller argument", __func__); 518 pica->pica_sc = sc; 519 pica->pica_map = intrmap; 520 pica->pica_clr = intrclr; 521#ifdef PSYCHO_DEBUG 522 /* 523 * Enable all interrupts and clear all interrupt 524 * states. This aids the debugging of interrupt 525 * routing problems. 526 */ 527 device_printf(dev, 528 "intr map (INO %d, %s) %#lx: %#lx, clr: %#lx\n", 529 n, intrmap <= PSR_PCIB3_INT_MAP ? "PCI" : "OBIO", 530 (u_long)intrmap, (u_long)PSYCHO_READ8(sc, intrmap), 531 (u_long)intrclr); 532 PSYCHO_WRITE8(sc, intrmap, INTMAP_VEC(sc->sc_ign, n)); 533 PSYCHO_WRITE8(sc, intrclr, 0); 534 PSYCHO_WRITE8(sc, intrmap, 535 INTMAP_ENABLE(INTMAP_VEC(sc->sc_ign, n), 536 PCPU_GET(mid))); 537#endif 538 if (intr_controller_register(INTMAP_VEC(sc->sc_ign, n), 539 &psycho_ic, pica) != 0) 540 panic("%s: could not register interrupt " 541 "controller for INO %d", __func__, n); 542 } 543 544 /* 545 * Establish handlers for interesting interrupts... 546 * 547 * XXX We need to remember these and remove this to support 548 * hotplug on the UPA/FHC bus. 549 * 550 * XXX Not all controllers have these, but installing them 551 * is better than trying to sort through this mess. 552 */ 553 psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL); 554 psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL); 555#ifdef DEBUGGER_ON_POWERFAIL 556 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, psycho_powerfail, 557 NULL); 558#else 559 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL, 560 (driver_intr_t *)psycho_powerfail); 561#endif 562 /* Psycho-specific initialization */ 563 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 564 /* 565 * Hummingbirds/Sabres do not have the following two 566 * interrupts. 567 */ 568 569 /* 570 * The spare hardware interrupt is used for the 571 * over-temperature interrupt. 572 */ 573 psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP, 574 NULL, psycho_overtemp); 575#ifdef PSYCHO_MAP_WAKEUP 576 /* 577 * psycho_wakeup() doesn't do anything useful right 578 * now. 579 */ 580 psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP, 581 psycho_wakeup, NULL); 582#endif /* PSYCHO_MAP_WAKEUP */ 583 584 /* Initialize the counter-timer. */ 585 sparc64_counter_init(rman_get_bustag(sc->sc_mem_res), 586 rman_get_bushandle(sc->sc_mem_res), PSR_TC0); 587 } 588 589 /* 590 * Set up IOMMU and PCI configuration if we're the first 591 * of a pair of Psycho's to arrive here. 592 * 593 * We should calculate a TSB size based on amount of RAM 594 * and number of bus controllers and number and type of 595 * child devices. 596 * 597 * For the moment, 32KB should be more than enough. 598 */ 599 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 600 M_NOWAIT | M_ZERO); 601 if (sc->sc_is == NULL) 602 panic("%s: malloc iommu_state failed", __func__); 603 if (sc->sc_mode == PSYCHO_MODE_SABRE) 604 sc->sc_is->is_pmaxaddr = 605 IOMMU_MAXADDR(SABRE_IOMMU_BITS); 606 else 607 sc->sc_is->is_pmaxaddr = 608 IOMMU_MAXADDR(PSYCHO_IOMMU_BITS); 609 sc->sc_is->is_sb[0] = 0; 610 sc->sc_is->is_sb[1] = 0; 611 if (OF_getproplen(node, "no-streaming-cache") < 0) 612 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 613 psycho_iommu_init(sc, 3, dvmabase); 614 } else { 615 /* Just copy IOMMU state, config tag and address. */ 616 sc->sc_is = osc->sc_is; 617 if (OF_getproplen(node, "no-streaming-cache") < 0) 618 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 619 iommu_reset(sc->sc_is); 620 } 621 622 /* 623 * Register a PCI bus error interrupt handler according to which 624 * half this is. Hummingbird/Sabre don't have a PCI bus B error 625 * interrupt but they are also only used for PCI bus A. 626 */ 627 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP : 628 PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL); 629 630 /* Allocate our tags. */ 631 sc->sc_pci_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 632 sc->sc_pci_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 633 sc->sc_pci_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 634 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 635 sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr, 636 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0) 637 panic("%s: bus_dma_tag_create failed", __func__); 638 /* Customize the tag. */ 639 sc->sc_pci_dmat->dt_cookie = sc->sc_is; 640 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 641 642 /* 643 * Get the bus range from the firmware; it is used solely for obtaining 644 * the inital bus number, and cannot be trusted on all machines. 645 */ 646 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br)); 647 if (n == -1) 648 panic("%s: could not get bus-range", __func__); 649 if (n != sizeof(psycho_br)) 650 panic("%s: broken bus-range (%d)", __func__, n); 651 652 /* Clear PCI status error bits. */ 653 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, 654 PCIR_STATUS, PCIM_STATUS_PERR | PCIM_STATUS_RMABORT | 655 PCIM_STATUS_RTABORT | PCIM_STATUS_STABORT | 656 PCIM_STATUS_PERRREPORT, 2); 657 658 /* 659 * Set the latency timer register as this isn't always done by the 660 * firmware. 661 */ 662 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, 663 PCIR_LATTIMER, 64, 1); 664 665 sc->sc_pci_secbus = sc->sc_pci_subbus = psycho_alloc_busno(dev); 666 /* 667 * Program the bus range registers. 668 * NOTE: for the Psycho, the second write changes the bus number the 669 * Psycho itself uses for it's configuration space, so these 670 * writes must be kept in this order! 671 * The Hummingbird/Sabre always uses bus 0, but there only can be one 672 * Hummingbird/Sabre per machine. 673 */ 674 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SUBBUS, 675 sc->sc_pci_subbus, 1); 676 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SECBUS, 677 sc->sc_pci_secbus, 1); 678 679 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 680 /* 681 * On E250 the interrupt map entry for the EBus bridge is wrong, 682 * causing incorrect interrupts to be assigned to some devices on 683 * the EBus. Work around it by changing our copy of the interrupt 684 * map mask to perform a full comparison of the INO. That way 685 * the interrupt map entry for the EBus bridge won't match at all 686 * and the INOs specified in the "interrupts" properties of the 687 * EBus devices will be used directly instead. 688 */ 689 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 && 690 sc->sc_pci_iinfo.opi_imapmsk != NULL) 691 *(ofw_pci_intr_t *)(&sc->sc_pci_iinfo.opi_imapmsk[ 692 sc->sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK; 693 694 device_add_child(dev, "pci", sc->sc_pci_secbus); 695 return (bus_generic_attach(dev)); 696} 697 698static void 699psycho_set_intr(struct psycho_softc *sc, u_int index, bus_addr_t intrmap, 700 driver_filter_t filt, driver_intr_t intr) 701{ 702 u_long vec; 703 int rid; 704 705 rid = index; 706 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ, 707 &rid, RF_ACTIVE); 708 if (sc->sc_irq_res[index] == NULL || 709 INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) != sc->sc_ign || 710 INTVEC(PSYCHO_READ8(sc, intrmap)) != vec || 711 intr_vectors[vec].iv_ic != &psycho_ic || 712 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], INTR_TYPE_MISC, 713 filt, intr, sc, &sc->sc_ihand[index]) != 0) 714 panic("%s: failed to set up interrupt %d", __func__, index); 715} 716 717static int 718psycho_find_intrmap(struct psycho_softc *sc, u_int ino, bus_addr_t *intrmapptr, 719 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 720{ 721 bus_addr_t intrclr, intrmap; 722 uint64_t diag; 723 int found; 724 725 /* 726 * XXX we only compare INOs rather than INRs since the firmware may 727 * not provide the IGN and the IGN is constant for all devices on 728 * that PCI controller. 729 * This could cause problems for the FFB/external interrupt which 730 * has a full vector that can be set arbitrarily. 731 */ 732 733 if (ino > PSYCHO_MAX_INO) { 734 device_printf(sc->sc_dev, "out of range INO %d requested\n", 735 ino); 736 return (0); 737 } 738 739 found = 0; 740 /* Hunt through OBIO first. */ 741 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 742 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 743 intrmap <= PSR_PWRMGT_INT_MAP; intrmap += 8, intrclr += 8, 744 diag >>= 2) { 745 if (sc->sc_mode == PSYCHO_MODE_SABRE && 746 (intrmap == PSR_TIMER0_INT_MAP || 747 intrmap == PSR_TIMER1_INT_MAP || 748 intrmap == PSR_PCIBERR_INT_MAP || 749 intrmap == PSR_PWRMGT_INT_MAP)) 750 continue; 751 if (INTINO(PSYCHO_READ8(sc, intrmap)) == ino) { 752 diag &= 2; 753 found = 1; 754 break; 755 } 756 } 757 758 if (!found) { 759 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 760 /* Now do PCI interrupts. */ 761 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 762 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 763 diag >>= 8) { 764 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 765 (intrmap == PSR_PCIA2_INT_MAP || 766 intrmap == PSR_PCIA3_INT_MAP)) 767 continue; 768 if (((PSYCHO_READ8(sc, intrmap) ^ ino) & 0x3c) == 0) { 769 intrclr += 8 * (ino & 3); 770 diag = (diag >> ((ino & 3) * 2)) & 2; 771 found = 1; 772 break; 773 } 774 } 775 } 776 if (intrmapptr != NULL) 777 *intrmapptr = intrmap; 778 if (intrclrptr != NULL) 779 *intrclrptr = intrclr; 780 if (intrdiagptr != NULL) 781 *intrdiagptr = diag; 782 return (found); 783} 784 785/* 786 * Interrupt handlers 787 */ 788static int 789psycho_ue(void *arg) 790{ 791 struct psycho_softc *sc = arg; 792 uint64_t afar, afsr; 793 794 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 795 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 796 /* 797 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 798 * the AFAR to be set to the physical address of the TTE entry that 799 * was invalid/write protected. Call into the iommu code to have 800 * them decoded to virtual I/O addresses. 801 */ 802 if ((afsr & UEAFSR_P_DTE) != 0) 803 iommu_decode_fault(sc->sc_is, afar); 804 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx", 805 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 806 return (FILTER_HANDLED); 807} 808 809static int 810psycho_ce(void *arg) 811{ 812 struct psycho_softc *sc = arg; 813 uint64_t afar, afsr; 814 815 mtx_lock_spin(sc->sc_mtx); 816 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 817 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 818 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx " 819 "AFSR %#lx\n", (u_long)afar, (u_long)afsr); 820 /* Clear the error bits that we caught. */ 821 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr & CEAFSR_ERRMASK); 822 mtx_unlock_spin(sc->sc_mtx); 823 return (FILTER_HANDLED); 824} 825 826static int 827psycho_pci_bus(void *arg) 828{ 829 struct psycho_softc *sc = arg; 830 uint64_t afar, afsr; 831 832 afar = PCICTL_READ8(sc, PCR_AFA); 833 afsr = PCICTL_READ8(sc, PCR_AFS); 834 panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx", 835 device_get_name(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar, 836 (u_long)afsr); 837 return (FILTER_HANDLED); 838} 839 840static int 841psycho_powerfail(void *arg) 842{ 843#ifdef DEBUGGER_ON_POWERFAIL 844 struct psycho_softc *sc = arg; 845 846 kdb_enter("powerfail"); 847#else 848 static int shutdown; 849 850 /* As the interrupt is cleared we may be called multiple times. */ 851 if (shutdown != 0) 852 return (FILTER_HANDLED); 853 shutdown++; 854 printf("Power Failure Detected: Shutting down NOW.\n"); 855 shutdown_nice(0); 856#endif 857 return (FILTER_HANDLED); 858} 859 860static void 861psycho_overtemp(void *arg) 862{ 863 static int shutdown; 864 865 /* As the interrupt is cleared we may be called multiple times. */ 866 if (shutdown != 0) 867 return; 868 shutdown++; 869 printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n"); 870 shutdown_nice(RB_POWEROFF); 871} 872 873#ifdef PSYCHO_MAP_WAKEUP 874static int 875psycho_wakeup(void *arg) 876{ 877 struct psycho_softc *sc = arg; 878 879 /* Gee, we don't really have a framework to deal with this properly. */ 880 device_printf(sc->sc_dev, "power management wakeup\n"); 881 return (FILTER_HANDLED); 882} 883#endif /* PSYCHO_MAP_WAKEUP */ 884 885static void 886psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase) 887{ 888 char *name; 889 struct iommu_state *is = sc->sc_is; 890 891 /* Punch in our copies. */ 892 is->is_bustag = rman_get_bustag(sc->sc_mem_res); 893 is->is_bushandle = rman_get_bushandle(sc->sc_mem_res); 894 is->is_iommu = PSR_IOMMU; 895 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 896 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 897 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 898 is->is_dva = PSR_IOMMU_SVADIAG; 899 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 900 901 /* Give us a nice name... */ 902 name = malloc(32, M_DEVBUF, M_NOWAIT); 903 if (name == NULL) 904 panic("%s: could not malloc iommu name", __func__); 905 snprintf(name, 32, "%s dvma", device_get_nameunit(sc->sc_dev)); 906 907 iommu_init(name, is, tsbsize, dvmabase, 0); 908} 909 910static int 911psycho_maxslots(device_t dev) 912{ 913 914 /* XXX: is this correct? */ 915 return (PCI_SLOTMAX); 916} 917 918static uint32_t 919psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 920 int width) 921{ 922 struct psycho_softc *sc; 923 bus_space_handle_t bh; 924 u_long offset = 0; 925 uint8_t byte; 926 uint16_t shrt; 927 uint32_t wrd; 928 uint32_t r; 929 int i; 930 931 sc = device_get_softc(dev); 932 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 933 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 934 switch (width) { 935 case 1: 936 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 937 r = byte; 938 break; 939 case 2: 940 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 941 r = shrt; 942 break; 943 case 4: 944 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 945 r = wrd; 946 break; 947 default: 948 panic("%s: bad width", __func__); 949 } 950 951 if (i) { 952#ifdef PSYCHO_DEBUG 953 printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 954 __func__, bus, slot, func, reg); 955#endif 956 r = -1; 957 } 958 return (r); 959} 960 961static void 962psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 963 uint32_t val, int width) 964{ 965 struct psycho_softc *sc; 966 bus_space_handle_t bh; 967 u_long offset = 0; 968 969 sc = device_get_softc(dev); 970 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 971 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 972 switch (width) { 973 case 1: 974 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 975 break; 976 case 2: 977 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 978 break; 979 case 4: 980 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 981 break; 982 default: 983 panic("%s: bad width", __func__); 984 } 985} 986 987static int 988psycho_route_interrupt(device_t bridge, device_t dev, int pin) 989{ 990 struct psycho_softc *sc; 991 struct ofw_pci_register reg; 992 bus_addr_t intrmap; 993 ofw_pci_intr_t pintr, mintr; 994 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 995 996 sc = device_get_softc(bridge); 997 pintr = pin; 998 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, 999 sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) 1000 return (mintr); 1001 /* 1002 * If this is outside of the range for an intpin, it's likely a full 1003 * INO, and no mapping is required at all; this happens on the U30, 1004 * where there's no interrupt map at the Psycho node. Fortunately, 1005 * there seem to be no INOs in the intpin range on this boxen, so 1006 * this easy heuristics will do. 1007 */ 1008 if (pin > 4) 1009 return (pin); 1010 /* 1011 * Guess the INO; we always assume that this is a non-OBIO 1012 * device, and that pin is a "real" intpin number. Determine 1013 * the mapping register to be used by the slot number. 1014 * We only need to do this on E450s, it seems; here, the slot numbers 1015 * for bus A are one-based, while those for bus B seemingly have an 1016 * offset of 2 (hence the factor of 3 below). 1017 */ 1018 intrmap = PSR_PCIA0_INT_MAP + 1019 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half); 1020 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1; 1021 device_printf(bridge, "guessing interrupt %d for device %d.%d pin %d\n", 1022 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin); 1023 return (mintr); 1024} 1025 1026static int 1027psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1028{ 1029 struct psycho_softc *sc; 1030 1031 sc = device_get_softc(dev); 1032 switch (which) { 1033 case PCIB_IVAR_BUS: 1034 *result = sc->sc_pci_secbus; 1035 return (0); 1036 } 1037 return (ENOENT); 1038} 1039 1040static int 1041psycho_dmasync(void *arg) 1042{ 1043 struct psycho_dmasync *pds = arg; 1044 1045 (void)PCIB_READ_CONFIG(pds->pds_ppb, pds->pds_bus, pds->pds_slot, 1046 pds->pds_func, PCIR_VENDOR, 2); 1047 (void)PSYCHO_READ8(pds->pds_sc, PSR_DMA_WRITE_SYNC); 1048 return (pds->pds_handler(pds->pds_arg)); 1049} 1050 1051static void 1052psycho_intr_enable(void *arg) 1053{ 1054 struct intr_vector *iv = arg; 1055 struct psycho_icarg *pica = iv->iv_icarg; 1056 1057 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, 1058 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1059} 1060 1061static void 1062psycho_intr_disable(void *arg) 1063{ 1064 struct intr_vector *iv = arg; 1065 struct psycho_icarg *pica = iv->iv_icarg; 1066 1067 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, iv->iv_vec); 1068} 1069 1070static void 1071psycho_intr_eoi(void *arg) 1072{ 1073 struct intr_vector *iv = arg; 1074 struct psycho_icarg *pica = iv->iv_icarg; 1075 1076 PSYCHO_WRITE8(pica->pica_sc, pica->pica_clr, 0); 1077} 1078 1079static int 1080psycho_setup_intr(device_t dev, device_t child, struct resource *ires, 1081 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1082 void **cookiep) 1083{ 1084 struct { 1085 int apb:1; 1086 int ppb:1; 1087 } found; 1088 devclass_t pci_devclass; 1089 device_t cdev, pdev, pcidev; 1090 struct psycho_softc *sc; 1091 struct psycho_dmasync *pds; 1092 u_long vec; 1093 int error; 1094 1095 sc = device_get_softc(dev); 1096 /* 1097 * Make sure the vector is fully specified and we registered 1098 * our interrupt controller for it. 1099 */ 1100 vec = rman_get_start(ires); 1101 if (INTIGN(vec) != sc->sc_ign || 1102 intr_vectors[vec].iv_ic != &psycho_ic) { 1103 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1104 return (EINVAL); 1105 } 1106 1107 /* 1108 * The Sabre-APB-combination has a bug where it does not drain 1109 * DMA write data for devices behind additional PCI-PCI bridges 1110 * underneath the APB PCI-PCI bridge. The workaround is to do 1111 * a read on the farest PCI-PCI bridge followed by a read of the 1112 * PCI DMA write sync register of the Sabre. 1113 * XXX installing the wrapper for an affected device and the 1114 * actual workaround in psycho_dmasync() should be moved to 1115 * psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() 1116 * methods, respectively, once DMA tag creation is newbus'ified, 1117 * so the workaround isn't only applied for interrupt handlers 1118 * but also for polling(4) callbacks. 1119 */ 1120 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 1121 pds = malloc(sizeof(*pds), M_DEVBUF, M_NOWAIT | M_ZERO); 1122 if (pds == NULL) 1123 return (ENOMEM); 1124 pcidev = NULL; 1125 found.apb = found.ppb = 0; 1126 pci_devclass = devclass_find("pci"); 1127 for (cdev = child; cdev != dev; cdev = pdev) { 1128 pdev = device_get_parent(cdev); 1129 if (pcidev == NULL) { 1130 if (device_get_devclass(pdev) != pci_devclass) 1131 continue; 1132 pcidev = cdev; 1133 continue; 1134 } 1135 /* 1136 * NB: APB would also match as PCI-PCI bridges. 1137 */ 1138 if (pci_get_vendor(cdev) == 0x108e && 1139 pci_get_device(cdev) == 0x5000) { 1140 found.apb = 1; 1141 break; 1142 } 1143 if (pci_get_class(cdev) == PCIC_BRIDGE && 1144 pci_get_subclass(cdev) == PCIS_BRIDGE_PCI) 1145 found.ppb = 1; 1146 } 1147 if (found.apb && found.ppb && pcidev != NULL) { 1148 pds->pds_sc = sc; 1149 pds->pds_arg = arg; 1150 pds->pds_ppb = 1151 device_get_parent(device_get_parent(pcidev)); 1152 pds->pds_bus = pci_get_bus(pcidev); 1153 pds->pds_slot = pci_get_slot(pcidev); 1154 pds->pds_func = pci_get_function(pcidev); 1155 if (bootverbose) 1156 device_printf(dev, "installed DMA sync " 1157 "workaround for device %d.%d on bus %d\n", 1158 pds->pds_slot, pds->pds_func, 1159 pds->pds_bus); 1160 if (intr == NULL) { 1161 pds->pds_handler = filt; 1162 error = bus_generic_setup_intr(dev, child, 1163 ires, flags, psycho_dmasync, intr, pds, 1164 cookiep); 1165 } else { 1166 pds->pds_handler = (driver_filter_t *)intr; 1167 error = bus_generic_setup_intr(dev, child, 1168 ires, flags, filt, 1169 (driver_intr_t *)psycho_dmasync, pds, 1170 cookiep); 1171 } 1172 } else 1173 error = bus_generic_setup_intr(dev, child, ires, 1174 flags, filt, intr, arg, cookiep); 1175 if (error != 0) { 1176 free(pds, M_DEVBUF); 1177 return (error); 1178 } 1179 pds->pds_cookie = *cookiep; 1180 *cookiep = pds; 1181 return (error); 1182 } 1183 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1184 arg, cookiep)); 1185} 1186 1187static int 1188psycho_teardown_intr(device_t dev, device_t child, struct resource *vec, 1189 void *cookie) 1190{ 1191 struct psycho_softc *sc; 1192 struct psycho_dmasync *pds; 1193 int error; 1194 1195 sc = device_get_softc(dev); 1196 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 1197 pds = cookie; 1198 error = bus_generic_teardown_intr(dev, child, vec, 1199 pds->pds_cookie); 1200 if (error == 0) 1201 free(pds, M_DEVBUF); 1202 return (error); 1203 } 1204 return (bus_generic_teardown_intr(dev, child, vec, cookie)); 1205} 1206 1207static struct resource * 1208psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1209 u_long start, u_long end, u_long count, u_int flags) 1210{ 1211 struct psycho_softc *sc; 1212 struct resource *rv; 1213 struct rman *rm; 1214 bus_space_tag_t bt; 1215 bus_space_handle_t bh; 1216 int needactivate = flags & RF_ACTIVE; 1217 1218 flags &= ~RF_ACTIVE; 1219 1220 sc = device_get_softc(bus); 1221 if (type == SYS_RES_IRQ) { 1222 /* 1223 * XXX: Don't accept blank ranges for now, only single 1224 * interrupts. The other case should not happen with the 1225 * MI PCI code... 1226 * XXX: This may return a resource that is out of the 1227 * range that was specified. Is this correct...? 1228 */ 1229 if (start != end) 1230 panic("%s: XXX: interrupt range", __func__); 1231 start = end = INTMAP_VEC(sc->sc_ign, end); 1232 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, 1233 rid, start, end, count, flags)); 1234 } 1235 switch (type) { 1236 case SYS_RES_MEMORY: 1237 rm = &sc->sc_pci_mem_rman; 1238 bt = sc->sc_pci_memt; 1239 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1240 break; 1241 case SYS_RES_IOPORT: 1242 rm = &sc->sc_pci_io_rman; 1243 bt = sc->sc_pci_iot; 1244 bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1245 break; 1246 default: 1247 return (NULL); 1248 } 1249 1250 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1251 if (rv == NULL) 1252 return (NULL); 1253 rman_set_rid(rv, *rid); 1254 bh += rman_get_start(rv); 1255 rman_set_bustag(rv, bt); 1256 rman_set_bushandle(rv, bh); 1257 1258 if (needactivate) { 1259 if (bus_activate_resource(child, type, *rid, rv)) { 1260 rman_release_resource(rv); 1261 return (NULL); 1262 } 1263 } 1264 1265 return (rv); 1266} 1267 1268static int 1269psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1270 struct resource *r) 1271{ 1272 void *p; 1273 int error; 1274 1275 if (type == SYS_RES_IRQ) 1276 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1277 type, rid, r)); 1278 if (type == SYS_RES_MEMORY) { 1279 /* 1280 * Need to memory-map the device space, as some drivers depend 1281 * on the virtual address being set and useable. 1282 */ 1283 error = sparc64_bus_mem_map(rman_get_bustag(r), 1284 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1285 if (error != 0) 1286 return (error); 1287 rman_set_virtual(r, p); 1288 } 1289 return (rman_activate_resource(r)); 1290} 1291 1292static int 1293psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1294 struct resource *r) 1295{ 1296 1297 if (type == SYS_RES_IRQ) 1298 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1299 type, rid, r)); 1300 if (type == SYS_RES_MEMORY) { 1301 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1302 rman_set_virtual(r, NULL); 1303 } 1304 return (rman_deactivate_resource(r)); 1305} 1306 1307static int 1308psycho_release_resource(device_t bus, device_t child, int type, int rid, 1309 struct resource *r) 1310{ 1311 int error; 1312 1313 if (type == SYS_RES_IRQ) 1314 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1315 type, rid, r)); 1316 if (rman_get_flags(r) & RF_ACTIVE) { 1317 error = bus_deactivate_resource(child, type, rid, r); 1318 if (error) 1319 return (error); 1320 } 1321 return (rman_release_resource(r)); 1322} 1323 1324static bus_dma_tag_t 1325psycho_get_dma_tag(device_t bus, device_t child) 1326{ 1327 struct psycho_softc *sc; 1328 1329 sc = device_get_softc(bus); 1330 return (sc->sc_pci_dmat); 1331} 1332 1333static int 1334psycho_intr_pending(device_t dev, ofw_pci_intr_t intr) 1335{ 1336 struct psycho_softc *sc; 1337 u_long diag; 1338 1339 sc = device_get_softc(dev); 1340 if (psycho_find_intrmap(sc, intr, NULL, NULL, &diag) == 0) { 1341 device_printf(dev, "%s: mapping not found for %d\n", __func__, 1342 intr); 1343 return (0); 1344 } 1345 return (diag != 0); 1346} 1347 1348static phandle_t 1349psycho_get_node(device_t bus, device_t dev) 1350{ 1351 struct psycho_softc *sc; 1352 1353 sc = device_get_softc(bus); 1354 /* We only have one child, the PCI bus, which needs our own node. */ 1355 return (sc->sc_node); 1356} 1357 1358static int 1359psycho_alloc_busno(device_t dev) 1360{ 1361 1362 if (psycho_pci_bus_cnt == PCI_BUSMAX) 1363 panic("%s: out of PCI bus numbers", __func__); 1364 return (psycho_pci_bus_cnt++); 1365} 1366 1367static void 1368psycho_adjust_busrange(device_t dev, u_int subbus) 1369{ 1370 struct psycho_softc *sc; 1371 1372 sc = device_get_softc(dev); 1373 /* If necessary, adjust the subordinate bus number register. */ 1374 if (subbus > sc->sc_pci_subbus) { 1375#ifdef PSYCHO_DEBUG 1376 device_printf(dev, 1377 "adjusting subordinate bus number from %d to %d\n", 1378 sc->sc_pci_subbus, subbus); 1379#endif 1380 sc->sc_pci_subbus = subbus; 1381 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, 1382 PCSR_SUBBUS, subbus, 1); 1383 } 1384} 1385 1386static bus_space_tag_t 1387psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1388{ 1389 bus_space_tag_t bt; 1390 1391 bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF, M_NOWAIT | M_ZERO); 1392 if (bt == NULL) 1393 panic("%s: out of memory", __func__); 1394 1395 bt->bst_cookie = sc; 1396 bt->bst_parent = rman_get_bustag(sc->sc_mem_res); 1397 bt->bst_type = type; 1398 return (bt); 1399} 1400