psycho.c revision 170930
1/*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/sparc64/pci/psycho.c 170930 2007-06-18 21:49:42Z marius $"); 35 36/* 37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+' 38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges. 39 */ 40 41#include "opt_ofw_pci.h" 42#include "opt_psycho.h" 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/bus.h> 47#include <sys/kdb.h> 48#include <sys/kernel.h> 49#include <sys/lock.h> 50#include <sys/malloc.h> 51#include <sys/module.h> 52#include <sys/mutex.h> 53#include <sys/pcpu.h> 54#include <sys/reboot.h> 55 56#include <dev/ofw/ofw_bus.h> 57#include <dev/ofw/ofw_pci.h> 58#include <dev/ofw/openfirm.h> 59 60#include <machine/bus.h> 61#include <machine/bus_common.h> 62#include <machine/bus_private.h> 63#include <machine/iommureg.h> 64#include <machine/iommuvar.h> 65#include <machine/ofw_bus.h> 66#include <machine/resource.h> 67#include <machine/ver.h> 68 69#include <sys/rman.h> 70 71#include <dev/pci/pcireg.h> 72#include <dev/pci/pcivar.h> 73 74#include <sparc64/pci/ofw_pci.h> 75#include <sparc64/pci/psychoreg.h> 76#include <sparc64/pci/psychovar.h> 77 78#include "pcib_if.h" 79 80static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *, 81 const char *); 82static const struct psycho_desc *psycho_get_desc(device_t); 83static void psycho_set_intr(struct psycho_softc *, int, bus_addr_t, 84 driver_filter_t, driver_intr_t); 85static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *, 86 bus_addr_t *, u_long *); 87static driver_filter_t psycho_filter_stub; 88static driver_intr_t psycho_intr_stub; 89static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 90 91/* Interrupt handlers */ 92static driver_filter_t psycho_ue; 93static driver_filter_t psycho_ce; 94static driver_filter_t psycho_pci_bus; 95static driver_filter_t psycho_powerfail; 96static driver_intr_t psycho_overtemp; 97#ifdef PSYCHO_MAP_WAKEUP 98static driver_filter_t psycho_wakeup; 99#endif 100 101/* IOMMU support */ 102static void psycho_iommu_init(struct psycho_softc *, int, uint32_t); 103 104/* 105 * Methods 106 */ 107static device_probe_t psycho_probe; 108static device_attach_t psycho_attach; 109static bus_read_ivar_t psycho_read_ivar; 110static bus_setup_intr_t psycho_setup_intr; 111static bus_teardown_intr_t psycho_teardown_intr; 112static bus_alloc_resource_t psycho_alloc_resource; 113static bus_activate_resource_t psycho_activate_resource; 114static bus_deactivate_resource_t psycho_deactivate_resource; 115static bus_release_resource_t psycho_release_resource; 116static bus_get_dma_tag_t psycho_get_dma_tag; 117static pcib_maxslots_t psycho_maxslots; 118static pcib_read_config_t psycho_read_config; 119static pcib_write_config_t psycho_write_config; 120static pcib_route_interrupt_t psycho_route_interrupt; 121static ofw_pci_intr_pending_t psycho_intr_pending; 122static ofw_bus_get_node_t psycho_get_node; 123static ofw_pci_alloc_busno_t psycho_alloc_busno; 124static ofw_pci_adjust_busrange_t psycho_adjust_busrange; 125 126static device_method_t psycho_methods[] = { 127 /* Device interface */ 128 DEVMETHOD(device_probe, psycho_probe), 129 DEVMETHOD(device_attach, psycho_attach), 130 DEVMETHOD(device_shutdown, bus_generic_shutdown), 131 DEVMETHOD(device_suspend, bus_generic_suspend), 132 DEVMETHOD(device_resume, bus_generic_resume), 133 134 /* Bus interface */ 135 DEVMETHOD(bus_print_child, bus_generic_print_child), 136 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 137 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 138 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 139 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 140 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 141 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 142 DEVMETHOD(bus_release_resource, psycho_release_resource), 143 DEVMETHOD(bus_get_dma_tag, psycho_get_dma_tag), 144 145 /* pcib interface */ 146 DEVMETHOD(pcib_maxslots, psycho_maxslots), 147 DEVMETHOD(pcib_read_config, psycho_read_config), 148 DEVMETHOD(pcib_write_config, psycho_write_config), 149 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 150 151 /* ofw_bus interface */ 152 DEVMETHOD(ofw_bus_get_node, psycho_get_node), 153 154 /* ofw_pci interface */ 155 DEVMETHOD(ofw_pci_intr_pending, psycho_intr_pending), 156 DEVMETHOD(ofw_pci_alloc_busno, psycho_alloc_busno), 157 DEVMETHOD(ofw_pci_adjust_busrange, psycho_adjust_busrange), 158 159 { 0, 0 } 160}; 161 162static driver_t psycho_driver = { 163 "pcib", 164 psycho_methods, 165 sizeof(struct psycho_softc), 166}; 167 168static devclass_t psycho_devclass; 169 170DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 171 172static SLIST_HEAD(, psycho_softc) psycho_softcs = 173 SLIST_HEAD_INITIALIZER(psycho_softcs); 174 175static uint8_t psycho_pci_bus_cnt; 176 177struct psycho_clr { 178 struct psycho_softc *pci_sc; 179 bus_addr_t pci_clr; /* clear register */ 180 driver_filter_t *pci_filter; /* filter to call */ 181 driver_intr_t *pci_handler; /* handler to call */ 182 void *pci_arg; /* argument for the handler */ 183 void *pci_cookie; /* parent bus int. cookie */ 184 device_t pci_ppb; /* farest PCI-PCI bridge */ 185 uint8_t pci_bus; /* bus of farest PCI device */ 186 uint8_t pci_slot; /* slot of farest PCI device */ 187 uint8_t pci_func; /* func. of farest PCI device */ 188}; 189 190#define PSYCHO_READ8(sc, off) \ 191 bus_read_8((sc)->sc_mem_res, (off)) 192#define PSYCHO_WRITE8(sc, off, v) \ 193 bus_write_8((sc)->sc_mem_res, (off), (v)) 194#define PCICTL_READ8(sc, off) \ 195 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 196#define PCICTL_WRITE8(sc, off, v) \ 197 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 198 199/* 200 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 201 * single PCI bus and does not have a streaming buffer. It often has an APB 202 * (advanced PCI bridge) connected to it, which was designed specifically for 203 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 204 * appears as two "Simba"'s underneath the Sabre. 205 * 206 * "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's 207 * basically the same as Sabre but without an APB underneath it. 208 * 209 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA bus 210 * and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while 211 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 212 * will usually find a "Psycho+" since I don't think the original "Psycho" 213 * ever shipped, and if it did it would be in the U30. 214 * 215 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are 216 * both part of the same IC, they only have a single register space. As such, 217 * they need to be configured together, even though the autoconfiguration will 218 * attach them separately. 219 * 220 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often 221 * as pci1 and pci2, although they have been implemented with other PCI bus 222 * numbers on some machines. 223 * 224 * On UltraII machines, there can be any number of "Psycho+" ICs, each 225 * providing two PCI buses. 226 */ 227 228#define OFW_PCI_TYPE "pci" 229 230struct psycho_desc { 231 const char *pd_string; 232 int pd_mode; 233 const char *pd_name; 234}; 235 236static const struct psycho_desc psycho_compats[] = { 237 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 238 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" }, 239 { "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" }, 240 { NULL, 0, NULL } 241}; 242 243static const struct psycho_desc psycho_models[] = { 244 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 245 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 246 { NULL, 0, NULL } 247}; 248 249static const struct psycho_desc * 250psycho_find_desc(const struct psycho_desc *table, const char *string) 251{ 252 const struct psycho_desc *desc; 253 254 if (string == NULL) 255 return (NULL); 256 for (desc = table; desc->pd_string != NULL; desc++) 257 if (strcmp(desc->pd_string, string) == 0) 258 return (desc); 259 return (NULL); 260} 261 262static const struct psycho_desc * 263psycho_get_desc(device_t dev) 264{ 265 const struct psycho_desc *rv; 266 267 rv = psycho_find_desc(psycho_models, ofw_bus_get_model(dev)); 268 if (rv == NULL) 269 rv = psycho_find_desc(psycho_compats, ofw_bus_get_compat(dev)); 270 return (rv); 271} 272 273static int 274psycho_probe(device_t dev) 275{ 276 const char *dtype; 277 278 dtype = ofw_bus_get_type(dev); 279 if (dtype != NULL && strcmp(dtype, OFW_PCI_TYPE) == 0 && 280 psycho_get_desc(dev) != NULL) { 281 device_set_desc(dev, "U2P UPA-PCI bridge"); 282 return (0); 283 } 284 285 return (ENXIO); 286} 287 288static int 289psycho_attach(device_t dev) 290{ 291 char name[sizeof("pci108e,1000")]; 292 struct psycho_softc *asc, *sc, *osc; 293 struct ofw_pci_ranges *range; 294 const struct psycho_desc *desc; 295 phandle_t child, node; 296 uint64_t csr, dr; 297 uint32_t dvmabase, psycho_br[2]; 298 int32_t rev; 299 u_int ver; 300 int i, n, nrange, rid; 301#ifdef PSYCHO_DEBUG 302 bus_addr_t map, clr; 303 uint64_t mr; 304#endif 305 306 node = ofw_bus_get_node(dev); 307 sc = device_get_softc(dev); 308 desc = psycho_get_desc(dev); 309 310 sc->sc_node = node; 311 sc->sc_dev = dev; 312 sc->sc_mode = desc->pd_mode; 313 314 /* 315 * The Psycho gets three register banks: 316 * (0) per-PBM configuration and status registers 317 * (1) per-PBM PCI configuration space, containing only the 318 * PBM 256-byte PCI header 319 * (2) the shared Psycho configuration registers 320 */ 321 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 322 rid = 2; 323 sc->sc_pcictl = 324 bus_get_resource_start(dev, SYS_RES_MEMORY, 0) - 325 bus_get_resource_start(dev, SYS_RES_MEMORY, 2); 326 switch (sc->sc_pcictl) { 327 case PSR_PCICTL0: 328 sc->sc_half = 0; 329 break; 330 case PSR_PCICTL1: 331 sc->sc_half = 1; 332 break; 333 default: 334 panic("%s: bogus PCI control register location", 335 __func__); 336 } 337 } else { 338 rid = 0; 339 sc->sc_pcictl = PSR_PCICTL0; 340 sc->sc_half = 0; 341 } 342 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 343 (sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) | 344 RF_ACTIVE); 345 if (sc->sc_mem_res == NULL) 346 panic("%s: could not allocate registers", __func__); 347 348 /* 349 * Match other Psycho's that are already configured against 350 * the base physical address. This will be the same for a 351 * pair of devices that share register space. 352 */ 353 osc = NULL; 354 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 355 if (rman_get_start(asc->sc_mem_res) == 356 rman_get_start(sc->sc_mem_res)) { 357 /* Found partner. */ 358 osc = asc; 359 break; 360 } 361 } 362 if (osc == NULL) { 363 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 364 M_NOWAIT | M_ZERO); 365 if (sc->sc_mtx == NULL) 366 panic("%s: could not malloc mutex", __func__); 367 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 368 } else { 369 if (mtx_initialized(osc->sc_mtx) == 0) 370 panic("%s: mutex not initialized", __func__); 371 sc->sc_mtx = osc->sc_mtx; 372 } 373 374 /* Clear PCI AFSR. */ 375 PCICTL_WRITE8(sc, PCR_AFS, PCIAFSR_ERRMASK); 376 377 csr = PSYCHO_READ8(sc, PSR_CS); 378 ver = PSYCHO_GCSR_VERS(csr); 379 sc->sc_ign = 0x7c0; /* Hummingbird/Sabre IGN is always 0x1f. */ 380 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 381 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << INTMAP_IGN_SHIFT; 382 383 device_printf(dev, "%s, impl %d, version %d, ign %#x, bus %c\n", 384 desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign, 385 'A' + sc->sc_half); 386 387 /* Set up the PCI control and PCI diagnostic registers. */ 388 389 /* 390 * Revision 0 EBus bridges have a bug which prevents them from 391 * working when bus parking is enabled. 392 */ 393 rev = -1; 394 csr = PCICTL_READ8(sc, PCR_CS); 395 csr &= ~PCICTL_ARB_PARK; 396 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 397 if (OF_getprop(child, "name", name, sizeof(name)) == -1) 398 continue; 399 if ((strcmp(name, "ebus") == 0 || 400 strcmp(name, "pci108e,1000") == 0) && 401 OF_getprop(child, "revision-id", &rev, sizeof(rev)) > 0 && 402 rev == 0) 403 break; 404 } 405 if (rev != 0 && OF_getproplen(node, "no-bus-parking") < 0) 406 csr |= PCICTL_ARB_PARK; 407 408 /* Workarounds for version specific bugs. */ 409 dr = PCICTL_READ8(sc, PCR_DIAG); 410 switch (ver) { 411 case 0: 412 dr |= DIAG_RTRY_DIS; 413 dr &= ~DIAG_DWSYNC_DIS; 414 /* XXX need to also disable rerun of the streaming buffers. */ 415 break; 416 case 1: 417 csr &= ~PCICTL_ARB_PARK; 418 dr |= DIAG_RTRY_DIS | DIAG_DWSYNC_DIS; 419 /* XXX need to also disable rerun of the streaming buffers. */ 420 break; 421 default: 422 dr |= DIAG_DWSYNC_DIS; 423 dr &= ~DIAG_RTRY_DIS; 424 break; 425 } 426 427 csr |= PCICTL_SERR | PCICTL_ERRINTEN | PCICTL_ARB_4; 428 csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN); 429#ifdef PSYCHO_DEBUG 430 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 431 (unsigned long long)PCICTL_READ8(sc, PCR_CS), 432 (unsigned long long)csr); 433#endif 434 PCICTL_WRITE8(sc, PCR_CS, csr); 435 436 dr &= ~DIAG_ISYNC_DIS; 437#ifdef PSYCHO_DEBUG 438 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 439 (unsigned long long)PCICTL_READ8(sc, PCR_DIAG), 440 (unsigned long long)dr); 441#endif 442 PCICTL_WRITE8(sc, PCR_DIAG, dr); 443 444 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 445 /* Use the PROM preset for now. */ 446 csr = PCICTL_READ8(sc, PCR_TAS); 447 if (csr == 0) 448 panic("%s: Hummingbird/Sabre TAS not initialized.", 449 __func__); 450 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT; 451 } else 452 dvmabase = -1; 453 454 /* Initialize memory and I/O rmans. */ 455 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 456 sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports"; 457 if (rman_init(&sc->sc_pci_io_rman) != 0 || 458 rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0) 459 panic("%s: failed to set up I/O rman", __func__); 460 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 461 sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory"; 462 if (rman_init(&sc->sc_pci_mem_rman) != 0 || 463 rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 464 panic("%s: failed to set up memory rman", __func__); 465 466 nrange = OF_getprop_alloc(node, "ranges", sizeof(*range), 467 (void **)&range); 468 /* 469 * Make sure that the expected ranges are present. The OFW_PCI_CS_MEM64 470 * one is not currently used though. 471 */ 472 if (nrange != PSYCHO_NRANGE) 473 panic("%s: unsupported number of ranges", __func__); 474 /* 475 * Find the addresses of the various bus spaces. 476 * There should not be multiple ones of one kind. 477 * The physical start addresses of the ranges are the configuration, 478 * memory and I/O handles. 479 */ 480 for (n = 0; n < PSYCHO_NRANGE; n++) { 481 i = OFW_PCI_RANGE_CS(&range[n]); 482 if (sc->sc_pci_bh[i] != 0) 483 panic("%s: duplicate range for space %d", __func__, i); 484 sc->sc_pci_bh[i] = OFW_PCI_RANGE_PHYS(&range[n]); 485 } 486 free(range, M_OFWPROP); 487 488 /* Register the softc, this is needed for paired Psychos. */ 489 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 490 491 /* 492 * Register a PCI bus error interrupt handler according to which 493 * half this is. Hummingbird/Sabre don't have a PCI bus B error 494 * interrupt but they are also only used for PCI bus A. 495 */ 496 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP : 497 PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL); 498 499 /* 500 * If we're a Hummingbird/Sabre or the first of a pair of Psycho's to 501 * arrive here, start up the IOMMU. 502 */ 503 if (osc == NULL) { 504 /* 505 * Establish handlers for interesting interrupts... 506 * 507 * XXX We need to remember these and remove this to support 508 * hotplug on the UPA/FHC bus. 509 * 510 * XXX Not all controllers have these, but installing them 511 * is better than trying to sort through this mess. 512 */ 513 psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL); 514 psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL); 515#ifdef DEBUGGER_ON_POWERFAIL 516 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, psycho_powerfail, 517 NULL); 518#else 519 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL, 520 (driver_intr_t *)psycho_powerfail); 521#endif 522 /* Psycho-specific initialization */ 523 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 524 /* 525 * Hummingbirds/Sabres do not have the following two 526 * interrupts. 527 */ 528 529 /* 530 * The spare hardware interrupt is used for the 531 * over-temperature interrupt. 532 */ 533 psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP, 534 NULL, psycho_overtemp); 535#ifdef PSYCHO_MAP_WAKEUP 536 /* 537 * psycho_wakeup() doesn't do anything useful right 538 * now. 539 */ 540 psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP, 541 psycho_wakeup, NULL); 542#endif /* PSYCHO_MAP_WAKEUP */ 543 544 /* Initialize the counter-timer. */ 545 sparc64_counter_init(rman_get_bustag(sc->sc_mem_res), 546 rman_get_bushandle(sc->sc_mem_res), PSR_TC0); 547 } 548 549 /* 550 * Set up IOMMU and PCI configuration if we're the first 551 * of a pair of Psycho's to arrive here. 552 * 553 * We should calculate a TSB size based on amount of RAM 554 * and number of bus controllers and number and type of 555 * child devices. 556 * 557 * For the moment, 32KB should be more than enough. 558 */ 559 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 560 M_NOWAIT); 561 if (sc->sc_is == NULL) 562 panic("%s: malloc iommu_state failed", __func__); 563 sc->sc_is->is_sb[0] = 0; 564 sc->sc_is->is_sb[1] = 0; 565 if (OF_getproplen(node, "no-streaming-cache") < 0) 566 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 567 psycho_iommu_init(sc, 3, dvmabase); 568 } else { 569 /* Just copy IOMMU state, config tag and address. */ 570 sc->sc_is = osc->sc_is; 571 if (OF_getproplen(node, "no-streaming-cache") < 0) 572 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 573 iommu_reset(sc->sc_is); 574 } 575 576 /* Allocate our tags. */ 577 sc->sc_pci_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 578 sc->sc_pci_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 579 sc->sc_pci_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 580 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, IOMMU_MAXADDR, ~0, 581 NULL, NULL, IOMMU_MAXADDR, 0xff, 0xffffffff, 0, NULL, NULL, 582 &sc->sc_pci_dmat) != 0) 583 panic("%s: bus_dma_tag_create failed", __func__); 584 /* Customize the tag. */ 585 sc->sc_pci_dmat->dt_cookie = sc->sc_is; 586 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 587 588#ifdef PSYCHO_DEBUG 589 /* 590 * Enable all interrupts and clear all interrupt states. 591 * This aids the debugging of interrupt routing problems. 592 */ 593 for (map = PSR_PCIA0_INT_MAP, clr = PSR_PCIA0_INT_CLR, n = 0; 594 map <= PSR_PCIB3_INT_MAP; map += 8, clr += 32, n++) { 595 mr = PSYCHO_READ8(sc, map); 596 device_printf(dev, "intr map (pci) %d: %#lx\n", n, (u_long)mr); 597 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 598 for (i = 0; i < 4; i++) 599 PCICTL_WRITE8(sc, clr + i * 8, 0); 600 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 601 } 602 for (map = PSR_SCSI_INT_MAP, clr = PSR_SCSI_INT_CLR, n = 0; 603 map <= PSR_SERIAL_INT_MAP; map += 8, clr += 8, n++) { 604 mr = PSYCHO_READ8(sc, map); 605 device_printf(dev, "intr map (obio) %d: %#lx, clr: %#lx\n", n, 606 (u_long)mr, (u_long)clr); 607 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 608 PSYCHO_WRITE8(sc, clr, 0); 609 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 610 } 611#endif /* PSYCHO_DEBUG */ 612 613 /* 614 * Get the bus range from the firmware; it is used solely for obtaining 615 * the inital bus number, and cannot be trusted on all machines. 616 */ 617 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br)); 618 if (n == -1) 619 panic("%s: could not get bus-range", __func__); 620 if (n != sizeof(psycho_br)) 621 panic("%s: broken bus-range (%d)", __func__, n); 622 623 /* Clear PCI status error bits. */ 624 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, 625 PCIR_STATUS, PCIM_STATUS_PERR | PCIM_STATUS_RMABORT | 626 PCIM_STATUS_RTABORT | PCIM_STATUS_STABORT | 627 PCIM_STATUS_PERRREPORT, 2); 628 629 /* 630 * Set the latency timer register as this isn't always done by the 631 * firmware. 632 */ 633 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, 634 PCIR_LATTIMER, 64, 1); 635 636 sc->sc_pci_secbus = sc->sc_pci_subbus = psycho_alloc_busno(dev); 637 /* 638 * Program the bus range registers. 639 * NOTE: for the Psycho, the second write changes the bus number the 640 * Psycho itself uses for it's configuration space, so these 641 * writes must be kept in this order! 642 * The Hummingbird/Sabre always uses bus 0, but there only can be one 643 * Hummingbird/Sabre per machine. 644 */ 645 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SUBBUS, 646 sc->sc_pci_subbus, 1); 647 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SECBUS, 648 sc->sc_pci_secbus, 1); 649 650 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 651 /* 652 * On E250 the interrupt map entry for the EBus bridge is wrong, 653 * causing incorrect interrupts to be assigned to some devices on 654 * the EBus. Work around it by changing our copy of the interrupt 655 * map mask to perform a full comparison of the INO. That way 656 * the interrupt map entry for the EBus bridge won't match at all 657 * and the INOs specified in the "interrupts" properties of the 658 * EBus devices will be used directly instead. 659 */ 660 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 && 661 sc->sc_pci_iinfo.opi_imapmsk != NULL) 662 *(ofw_pci_intr_t *)(&sc->sc_pci_iinfo.opi_imapmsk[ 663 sc->sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK; 664 665 device_add_child(dev, "pci", sc->sc_pci_secbus); 666 return (bus_generic_attach(dev)); 667} 668 669static void 670psycho_set_intr(struct psycho_softc *sc, int index, bus_addr_t map, 671 driver_filter_t filt, driver_intr_t intr) 672{ 673 uint64_t mr; 674 int rid; 675 676 rid = index; 677 mr = PSYCHO_READ8(sc, map); 678 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ, 679 &rid, RF_ACTIVE); 680 if (sc->sc_irq_res[index] == NULL || 681 rman_get_start(sc->sc_irq_res[index]) != INTVEC(mr) || 682 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], INTR_TYPE_MISC, 683 filt, intr, sc, &sc->sc_ihand[index]) != 0) 684 panic("%s: failed to set up interrupt %d", __func__, index); 685 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 686} 687 688static int 689psycho_find_intrmap(struct psycho_softc *sc, int ino, bus_addr_t *intrmapptr, 690 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 691{ 692 bus_addr_t intrmap, intrclr; 693 uint64_t im; 694 u_long diag; 695 int found; 696 697 found = 0; 698 /* Hunt thru OBIO first. */ 699 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 700 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 701 intrmap <= PSR_SERIAL_INT_MAP; intrmap += 8, intrclr += 8, 702 diag >>= 2) { 703 im = PSYCHO_READ8(sc, intrmap); 704 if (INTINO(im) == ino) { 705 diag &= 2; 706 found = 1; 707 break; 708 } 709 } 710 711 if (!found) { 712 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 713 /* Now do PCI interrupts. */ 714 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 715 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 716 diag >>= 8) { 717 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 718 (intrmap == PSR_PCIA2_INT_MAP || 719 intrmap == PSR_PCIA3_INT_MAP)) 720 continue; 721 im = PSYCHO_READ8(sc, intrmap); 722 if (((im ^ ino) & 0x3c) == 0) { 723 intrclr += 8 * (ino & 3); 724 diag = (diag >> ((ino & 3) * 2)) & 2; 725 found = 1; 726 break; 727 } 728 } 729 } 730 if (intrmapptr != NULL) 731 *intrmapptr = intrmap; 732 if (intrclrptr != NULL) 733 *intrclrptr = intrclr; 734 if (intrdiagptr != NULL) 735 *intrdiagptr = diag; 736 return (found); 737} 738 739/* 740 * Interrupt handlers 741 */ 742static int 743psycho_ue(void *arg) 744{ 745 struct psycho_softc *sc = arg; 746 uint64_t afar, afsr; 747 748 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 749 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 750 /* 751 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 752 * the AFAR to be set to the physical address of the TTE entry that 753 * was invalid/write protected. Call into the iommu code to have 754 * them decoded to virtual I/O addresses. 755 */ 756 if ((afsr & UEAFSR_P_DTE) != 0) 757 iommu_decode_fault(sc->sc_is, afar); 758 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx", 759 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 760 return (FILTER_HANDLED); 761} 762 763static int 764psycho_ce(void *arg) 765{ 766 struct psycho_softc *sc = arg; 767 uint64_t afar, afsr; 768 769 mtx_lock_spin(sc->sc_mtx); 770 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 771 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 772 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx " 773 "AFSR %#lx\n", (u_long)afar, (u_long)afsr); 774 /* Clear the error bits that we caught. */ 775 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr & CEAFSR_ERRMASK); 776 PSYCHO_WRITE8(sc, PSR_CE_INT_CLR, 0); 777 mtx_unlock_spin(sc->sc_mtx); 778 return (FILTER_HANDLED); 779} 780 781static int 782psycho_pci_bus(void *arg) 783{ 784 struct psycho_softc *sc = arg; 785 uint64_t afar, afsr; 786 787 afar = PCICTL_READ8(sc, PCR_AFA); 788 afsr = PCICTL_READ8(sc, PCR_AFS); 789 panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx", 790 device_get_name(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar, 791 (u_long)afsr); 792 return (FILTER_HANDLED); 793} 794 795static int 796psycho_powerfail(void *arg) 797{ 798#ifdef DEBUGGER_ON_POWERFAIL 799 struct psycho_softc *sc = arg; 800 801 kdb_enter("powerfail"); 802 PSYCHO_WRITE8(sc, PSR_POWER_INT_CLR, 0); 803#else 804 printf("Power Failure Detected: Shutting down NOW.\n"); 805 shutdown_nice(0); 806#endif 807 return (FILTER_HANDLED); 808} 809 810static void 811psycho_overtemp(void *arg) 812{ 813 814 printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n"); 815 shutdown_nice(RB_POWEROFF); 816} 817 818#ifdef PSYCHO_MAP_WAKEUP 819static int 820psycho_wakeup(void *arg) 821{ 822 struct psycho_softc *sc = arg; 823 824 PSYCHO_WRITE8(sc, PSR_PWRMGT_INT_CLR, 0); 825 /* Gee, we don't really have a framework to deal with this properly. */ 826 device_printf(sc->sc_dev, "power management wakeup\n"); 827 return (FILTER_HANDLED); 828} 829#endif /* PSYCHO_MAP_WAKEUP */ 830 831static void 832psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase) 833{ 834 char *name; 835 struct iommu_state *is = sc->sc_is; 836 837 /* Punch in our copies. */ 838 is->is_bustag = rman_get_bustag(sc->sc_mem_res); 839 is->is_bushandle = rman_get_bushandle(sc->sc_mem_res); 840 is->is_iommu = PSR_IOMMU; 841 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 842 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 843 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 844 is->is_dva = PSR_IOMMU_SVADIAG; 845 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 846 847 /* Give us a nice name... */ 848 name = malloc(32, M_DEVBUF, M_NOWAIT); 849 if (name == NULL) 850 panic("%s: could not malloc iommu name", __func__); 851 snprintf(name, 32, "%s dvma", device_get_nameunit(sc->sc_dev)); 852 853 iommu_init(name, is, tsbsize, dvmabase, 0); 854} 855 856static int 857psycho_maxslots(device_t dev) 858{ 859 860 /* XXX: is this correct? */ 861 return (PCI_SLOTMAX); 862} 863 864static uint32_t 865psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 866 int width) 867{ 868 struct psycho_softc *sc; 869 bus_space_handle_t bh; 870 u_long offset = 0; 871 uint8_t byte; 872 uint16_t shrt; 873 uint32_t wrd; 874 uint32_t r; 875 int i; 876 877 sc = device_get_softc(dev); 878 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 879 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 880 switch (width) { 881 case 1: 882 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 883 r = byte; 884 break; 885 case 2: 886 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 887 r = shrt; 888 break; 889 case 4: 890 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 891 r = wrd; 892 break; 893 default: 894 panic("%s: bad width", __func__); 895 } 896 897 if (i) { 898#ifdef PSYCHO_DEBUG 899 printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 900 __func__, bus, slot, func, reg); 901#endif 902 r = -1; 903 } 904 return (r); 905} 906 907static void 908psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 909 uint32_t val, int width) 910{ 911 struct psycho_softc *sc; 912 bus_space_handle_t bh; 913 u_long offset = 0; 914 915 sc = device_get_softc(dev); 916 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 917 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 918 switch (width) { 919 case 1: 920 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 921 break; 922 case 2: 923 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 924 break; 925 case 4: 926 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 927 break; 928 default: 929 panic("%s: bad width", __func__); 930 } 931} 932 933static int 934psycho_route_interrupt(device_t bridge, device_t dev, int pin) 935{ 936 struct psycho_softc *sc; 937 struct ofw_pci_register reg; 938 bus_addr_t intrmap; 939 ofw_pci_intr_t pintr, mintr; 940 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 941 942 sc = device_get_softc(bridge); 943 pintr = pin; 944 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, 945 sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) 946 return (mintr); 947 /* 948 * If this is outside of the range for an intpin, it's likely a full 949 * INO, and no mapping is required at all; this happens on the U30, 950 * where there's no interrupt map at the Psycho node. Fortunately, 951 * there seem to be no INOs in the intpin range on this boxen, so 952 * this easy heuristics will do. 953 */ 954 if (pin > 4) 955 return (pin); 956 /* 957 * Guess the INO; we always assume that this is a non-OBIO 958 * device, and that pin is a "real" intpin number. Determine 959 * the mapping register to be used by the slot number. 960 * We only need to do this on E450s, it seems; here, the slot numbers 961 * for bus A are one-based, while those for bus B seemingly have an 962 * offset of 2 (hence the factor of 3 below). 963 */ 964 intrmap = PSR_PCIA0_INT_MAP + 965 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half); 966 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1; 967 device_printf(bridge, "guessing interrupt %d for device %d.%d pin %d\n", 968 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin); 969 return (mintr); 970} 971 972static int 973psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 974{ 975 struct psycho_softc *sc; 976 977 sc = device_get_softc(dev); 978 switch (which) { 979 case PCIB_IVAR_BUS: 980 *result = sc->sc_pci_secbus; 981 return (0); 982 } 983 return (ENOENT); 984} 985 986static int 987psycho_filter_stub(void *arg) 988{ 989 struct psycho_clr *pc = arg; 990 int res; 991 992 if (pc->pci_filter != NULL) { 993 res = pc->pci_filter(pc->pci_arg); 994 PSYCHO_WRITE8(pc->pci_sc, pc->pci_clr, 0); 995 } else 996 res = FILTER_SCHEDULE_THREAD; 997 return (res); 998} 999 1000static void 1001psycho_intr_stub(void *arg) 1002{ 1003 struct psycho_clr *pc = arg; 1004 1005 if (pc->pci_ppb != NULL) { 1006 (void)PCIB_READ_CONFIG(pc->pci_ppb, pc->pci_bus, pc->pci_slot, 1007 pc->pci_func, PCIR_VENDOR, 2); 1008 (void)PSYCHO_READ8(pc->pci_sc, PSR_DMA_WRITE_SYNC); 1009 } 1010 pc->pci_handler(pc->pci_arg); 1011 if (pc->pci_filter == NULL) 1012 PSYCHO_WRITE8(pc->pci_sc, pc->pci_clr, 0); 1013} 1014 1015static int 1016psycho_setup_intr(device_t dev, device_t child, struct resource *ires, 1017 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1018 void **cookiep) 1019{ 1020 struct { 1021 int apb:1; 1022 int ppb:1; 1023 } found; 1024 devclass_t pci_devclass; 1025 device_t cdev, pdev, pcidev; 1026 struct psycho_softc *sc; 1027 struct psycho_clr *pc; 1028 bus_addr_t intrmapptr, intrclrptr; 1029 long vec; 1030 uint64_t mr; 1031 int error, ino; 1032 1033 if (filt != NULL && intr != NULL) 1034 return (EINVAL); 1035 1036 sc = device_get_softc(dev); 1037 pc = malloc(sizeof(*pc), M_DEVBUF, M_NOWAIT | M_ZERO); 1038 if (pc == NULL) 1039 return (ENOMEM); 1040 1041 /* 1042 * Hunt through all the interrupt mapping regs to look for our 1043 * interrupt vector. 1044 * 1045 * XXX We only compare INOs rather than IGNs since the firmware may 1046 * not provide the IGN and the IGN is constant for all devices on that 1047 * PCI controller. This could cause problems for the FFB/external 1048 * interrupt which has a full vector that can be set arbitrarily. 1049 */ 1050 vec = rman_get_start(ires); 1051 ino = INTINO(vec); 1052 if (!psycho_find_intrmap(sc, ino, &intrmapptr, &intrclrptr, NULL)) { 1053 device_printf(dev, "cannot find interrupt vector 0x%lx\n", vec); 1054 free(pc, M_DEVBUF); 1055 return (EINVAL); 1056 } 1057 1058#ifdef PSYCHO_DEBUG 1059 device_printf(dev, "%s: INO %d, map %#lx, clr %#lx\n", __func__, ino, 1060 (u_long)intrmapptr, (u_long)intrclrptr); 1061#endif 1062 1063 pc->pci_sc = sc; 1064 pc->pci_arg = arg; 1065 pc->pci_filter = filt; 1066 pc->pci_handler = intr; 1067 pc->pci_clr = intrclrptr; 1068 1069 /* 1070 * The Sabre-APB-combination has a bug where it does not drain 1071 * DMA write data for devices behind additional PCI-PCI bridges 1072 * underneath the APB PCI-PCI bridge. The workaround is to do 1073 * a read on the farest PCI-PCI bridge followed by a read of the 1074 * PCI DMA write sync register of the Sabre. 1075 * XXX installing the workaround for an affected device and the 1076 * actual workaround in psycho_intr_stub() should be moved to 1077 * psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() 1078 * methods, respectively, once we make use of BUS_GET_DMA_TAG(), 1079 * so the workaround isn't only applied for interrupt handlers 1080 * but also for polling(4) callbacks. 1081 */ 1082 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 1083 pcidev = NULL; 1084 found.apb = found.ppb = 0; 1085 pci_devclass = devclass_find("pci"); 1086 for (cdev = child; cdev != dev; cdev = pdev) { 1087 pdev = device_get_parent(cdev); 1088 if (pcidev == NULL) { 1089 if (device_get_devclass(pdev) != pci_devclass) 1090 continue; 1091 pcidev = cdev; 1092 continue; 1093 } 1094 /* 1095 * NB: APB would also match as PCI-PCI bridges. 1096 */ 1097 if (pci_get_vendor(cdev) == 0x108e && 1098 pci_get_device(cdev) == 0x5000) { 1099 found.apb = 1; 1100 break; 1101 } 1102 if (pci_get_class(cdev) == PCIC_BRIDGE && 1103 pci_get_subclass(cdev) == PCIS_BRIDGE_PCI) 1104 found.ppb = 1; 1105 } 1106 if (found.apb && found.ppb && pcidev != NULL) { 1107 pc->pci_ppb = 1108 device_get_parent(device_get_parent(pcidev)); 1109 pc->pci_bus = pci_get_bus(pcidev); 1110 pc->pci_slot = pci_get_slot(pcidev); 1111 pc->pci_func = pci_get_function(pcidev); 1112 if (bootverbose) 1113 device_printf(dev, "installed DMA sync " 1114 "workaround for device %d.%d on bus %d\n", 1115 pc->pci_slot, pc->pci_func, pc->pci_bus); 1116 } 1117 } 1118 1119 /* Disable the interrupt while we fiddle with it. */ 1120 mr = PSYCHO_READ8(sc, intrmapptr); 1121 PSYCHO_WRITE8(sc, intrmapptr, mr & ~INTMAP_V); 1122 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 1123 psycho_filter_stub, psycho_intr_stub, pc, cookiep); 1124 if (error != 0) { 1125 free(pc, M_DEVBUF); 1126 return (error); 1127 } 1128 pc->pci_cookie = *cookiep; 1129 *cookiep = pc; 1130 1131 /* 1132 * Clear the interrupt, it might have been triggered before it was 1133 * set up. 1134 */ 1135 PSYCHO_WRITE8(sc, intrclrptr, 0); 1136 /* 1137 * Enable the interrupt and program the target module now we have the 1138 * handler installed. 1139 */ 1140 PSYCHO_WRITE8(sc, intrmapptr, INTMAP_ENABLE(mr, PCPU_GET(mid))); 1141 return (error); 1142} 1143 1144static int 1145psycho_teardown_intr(device_t dev, device_t child, struct resource *vec, 1146 void *cookie) 1147{ 1148 struct psycho_clr *pc = cookie; 1149 int error; 1150 1151 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 1152 pc->pci_cookie); 1153 /* 1154 * Don't disable the interrupt for now, so that stray interupts get 1155 * detected... 1156 */ 1157 if (error != 0) 1158 free(pc, M_DEVBUF); 1159 return (error); 1160} 1161 1162static struct resource * 1163psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1164 u_long start, u_long end, u_long count, u_int flags) 1165{ 1166 struct psycho_softc *sc; 1167 struct resource *rv; 1168 struct rman *rm; 1169 bus_space_tag_t bt; 1170 bus_space_handle_t bh; 1171 int needactivate = flags & RF_ACTIVE; 1172 1173 flags &= ~RF_ACTIVE; 1174 1175 sc = device_get_softc(bus); 1176 if (type == SYS_RES_IRQ) { 1177 /* 1178 * XXX: Don't accept blank ranges for now, only single 1179 * interrupts. The other case should not happen with the 1180 * MI PCI code... 1181 * XXX: This may return a resource that is out of the 1182 * range that was specified. Is this correct...? 1183 */ 1184 if (start != end) 1185 panic("%s: XXX: interrupt range", __func__); 1186 start = end |= sc->sc_ign; 1187 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, 1188 rid, start, end, count, flags)); 1189 } 1190 switch (type) { 1191 case SYS_RES_MEMORY: 1192 rm = &sc->sc_pci_mem_rman; 1193 bt = sc->sc_pci_memt; 1194 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1195 break; 1196 case SYS_RES_IOPORT: 1197 rm = &sc->sc_pci_io_rman; 1198 bt = sc->sc_pci_iot; 1199 bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1200 break; 1201 default: 1202 return (NULL); 1203 } 1204 1205 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1206 if (rv == NULL) 1207 return (NULL); 1208 rman_set_rid(rv, *rid); 1209 bh += rman_get_start(rv); 1210 rman_set_bustag(rv, bt); 1211 rman_set_bushandle(rv, bh); 1212 1213 if (needactivate) { 1214 if (bus_activate_resource(child, type, *rid, rv)) { 1215 rman_release_resource(rv); 1216 return (NULL); 1217 } 1218 } 1219 1220 return (rv); 1221} 1222 1223static int 1224psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1225 struct resource *r) 1226{ 1227 void *p; 1228 int error; 1229 1230 if (type == SYS_RES_IRQ) 1231 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1232 type, rid, r)); 1233 if (type == SYS_RES_MEMORY) { 1234 /* 1235 * Need to memory-map the device space, as some drivers depend 1236 * on the virtual address being set and useable. 1237 */ 1238 error = sparc64_bus_mem_map(rman_get_bustag(r), 1239 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1240 if (error != 0) 1241 return (error); 1242 rman_set_virtual(r, p); 1243 } 1244 return (rman_activate_resource(r)); 1245} 1246 1247static int 1248psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1249 struct resource *r) 1250{ 1251 1252 if (type == SYS_RES_IRQ) 1253 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1254 type, rid, r)); 1255 if (type == SYS_RES_MEMORY) { 1256 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1257 rman_set_virtual(r, NULL); 1258 } 1259 return (rman_deactivate_resource(r)); 1260} 1261 1262static int 1263psycho_release_resource(device_t bus, device_t child, int type, int rid, 1264 struct resource *r) 1265{ 1266 int error; 1267 1268 if (type == SYS_RES_IRQ) 1269 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1270 type, rid, r)); 1271 if (rman_get_flags(r) & RF_ACTIVE) { 1272 error = bus_deactivate_resource(child, type, rid, r); 1273 if (error) 1274 return error; 1275 } 1276 return (rman_release_resource(r)); 1277} 1278 1279static bus_dma_tag_t 1280psycho_get_dma_tag(device_t bus, device_t child) 1281{ 1282 struct psycho_softc *sc; 1283 1284 sc = device_get_softc(bus); 1285 return (sc->sc_pci_dmat); 1286} 1287 1288static int 1289psycho_intr_pending(device_t dev, ofw_pci_intr_t intr) 1290{ 1291 struct psycho_softc *sc; 1292 u_long diag; 1293 1294 sc = device_get_softc(dev); 1295 if (!psycho_find_intrmap(sc, intr, NULL, NULL, &diag)) { 1296 device_printf(dev, "%s: mapping not found for %d\n", __func__, 1297 intr); 1298 return (0); 1299 } 1300 return (diag != 0); 1301} 1302 1303static phandle_t 1304psycho_get_node(device_t bus, device_t dev) 1305{ 1306 struct psycho_softc *sc; 1307 1308 sc = device_get_softc(bus); 1309 /* We only have one child, the PCI bus, which needs our own node. */ 1310 return (sc->sc_node); 1311} 1312 1313static int 1314psycho_alloc_busno(device_t dev) 1315{ 1316 1317 if (psycho_pci_bus_cnt == PCI_BUSMAX) 1318 panic("%s: out of PCI bus numbers", __func__); 1319 return (psycho_pci_bus_cnt++); 1320} 1321 1322static void 1323psycho_adjust_busrange(device_t dev, u_int subbus) 1324{ 1325 struct psycho_softc *sc; 1326 1327 sc = device_get_softc(dev); 1328 /* If necessary, adjust the subordinate bus number register. */ 1329 if (subbus > sc->sc_pci_subbus) { 1330#ifdef PSYCHO_DEBUG 1331 device_printf(dev, 1332 "adjusting subordinate bus number from %d to %d\n", 1333 sc->sc_pci_subbus, subbus); 1334#endif 1335 sc->sc_pci_subbus = subbus; 1336 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, 1337 PCSR_SUBBUS, subbus, 1); 1338 } 1339} 1340 1341static bus_space_tag_t 1342psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1343{ 1344 bus_space_tag_t bt; 1345 1346 bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF, M_NOWAIT | M_ZERO); 1347 if (bt == NULL) 1348 panic("%s: out of memory", __func__); 1349 1350 bt->bst_cookie = sc; 1351 bt->bst_parent = rman_get_bustag(sc->sc_mem_res); 1352 bt->bst_type = type; 1353 return (bt); 1354} 1355