psycho.c revision 170851
1/*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/sparc64/pci/psycho.c 170851 2007-06-16 23:46:41Z marius $"); 35 36/* 37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+' 38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges. 39 */ 40 41#include "opt_ofw_pci.h" 42#include "opt_psycho.h" 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/bus.h> 47#include <sys/kdb.h> 48#include <sys/kernel.h> 49#include <sys/lock.h> 50#include <sys/malloc.h> 51#include <sys/module.h> 52#include <sys/mutex.h> 53#include <sys/pcpu.h> 54#include <sys/reboot.h> 55 56#include <dev/ofw/ofw_bus.h> 57#include <dev/ofw/ofw_pci.h> 58#include <dev/ofw/openfirm.h> 59 60#include <machine/bus.h> 61#include <machine/bus_common.h> 62#include <machine/bus_private.h> 63#include <machine/iommureg.h> 64#include <machine/iommuvar.h> 65#include <machine/ofw_bus.h> 66#include <machine/resource.h> 67#include <machine/ver.h> 68 69#include <sys/rman.h> 70 71#include <dev/pci/pcireg.h> 72#include <dev/pci/pcivar.h> 73 74#include <sparc64/pci/ofw_pci.h> 75#include <sparc64/pci/psychoreg.h> 76#include <sparc64/pci/psychovar.h> 77 78#include "pcib_if.h" 79 80static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *, 81 const char *); 82static const struct psycho_desc *psycho_get_desc(device_t); 83static void psycho_set_intr(struct psycho_softc *, int, bus_addr_t, 84 driver_filter_t, driver_intr_t); 85static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *, 86 bus_addr_t *, u_long *); 87static driver_filter_t psycho_filter_stub; 88static driver_intr_t psycho_intr_stub; 89static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 90 91/* Interrupt handlers */ 92static driver_filter_t psycho_ue; 93static driver_filter_t psycho_ce; 94static driver_filter_t psycho_pci_bus; 95static driver_filter_t psycho_powerfail; 96static driver_intr_t psycho_overtemp; 97#ifdef PSYCHO_MAP_WAKEUP 98static driver_filter_t psycho_wakeup; 99#endif 100 101/* IOMMU support */ 102static void psycho_iommu_init(struct psycho_softc *, int, uint32_t); 103 104/* 105 * Methods 106 */ 107static device_probe_t psycho_probe; 108static device_attach_t psycho_attach; 109static bus_read_ivar_t psycho_read_ivar; 110static bus_setup_intr_t psycho_setup_intr; 111static bus_teardown_intr_t psycho_teardown_intr; 112static bus_alloc_resource_t psycho_alloc_resource; 113static bus_activate_resource_t psycho_activate_resource; 114static bus_deactivate_resource_t psycho_deactivate_resource; 115static bus_release_resource_t psycho_release_resource; 116static bus_get_dma_tag_t psycho_get_dma_tag; 117static pcib_maxslots_t psycho_maxslots; 118static pcib_read_config_t psycho_read_config; 119static pcib_write_config_t psycho_write_config; 120static pcib_route_interrupt_t psycho_route_interrupt; 121static ofw_pci_intr_pending_t psycho_intr_pending; 122static ofw_bus_get_node_t psycho_get_node; 123static ofw_pci_adjust_busrange_t psycho_adjust_busrange; 124 125static device_method_t psycho_methods[] = { 126 /* Device interface */ 127 DEVMETHOD(device_probe, psycho_probe), 128 DEVMETHOD(device_attach, psycho_attach), 129 DEVMETHOD(device_shutdown, bus_generic_shutdown), 130 DEVMETHOD(device_suspend, bus_generic_suspend), 131 DEVMETHOD(device_resume, bus_generic_resume), 132 133 /* Bus interface */ 134 DEVMETHOD(bus_print_child, bus_generic_print_child), 135 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 136 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 137 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 138 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 139 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 140 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 141 DEVMETHOD(bus_release_resource, psycho_release_resource), 142 DEVMETHOD(bus_get_dma_tag, psycho_get_dma_tag), 143 144 /* pcib interface */ 145 DEVMETHOD(pcib_maxslots, psycho_maxslots), 146 DEVMETHOD(pcib_read_config, psycho_read_config), 147 DEVMETHOD(pcib_write_config, psycho_write_config), 148 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 149 150 /* ofw_bus interface */ 151 DEVMETHOD(ofw_bus_get_node, psycho_get_node), 152 153 /* ofw_pci interface */ 154 DEVMETHOD(ofw_pci_intr_pending, psycho_intr_pending), 155 DEVMETHOD(ofw_pci_adjust_busrange, psycho_adjust_busrange), 156 157 { 0, 0 } 158}; 159 160static driver_t psycho_driver = { 161 "pcib", 162 psycho_methods, 163 sizeof(struct psycho_softc), 164}; 165 166static devclass_t psycho_devclass; 167 168DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 169 170SLIST_HEAD(, psycho_softc) psycho_softcs = 171 SLIST_HEAD_INITIALIZER(psycho_softcs); 172 173struct psycho_clr { 174 struct psycho_softc *pci_sc; 175 bus_addr_t pci_clr; /* clear register */ 176 driver_filter_t *pci_filter; /* filter to call */ 177 driver_intr_t *pci_handler; /* handler to call */ 178 void *pci_arg; /* argument for the handler */ 179 void *pci_cookie; /* parent bus int. cookie */ 180 device_t pci_ppb; /* farest PCI-PCI bridge */ 181 uint8_t pci_bus; /* bus of farest PCI device */ 182 uint8_t pci_slot; /* slot of farest PCI device */ 183 uint8_t pci_func; /* func. of farest PCI device */ 184}; 185 186#define PSYCHO_READ8(sc, off) \ 187 bus_read_8((sc)->sc_mem_res, (off)) 188#define PSYCHO_WRITE8(sc, off, v) \ 189 bus_write_8((sc)->sc_mem_res, (off), (v)) 190#define PCICTL_READ8(sc, off) \ 191 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 192#define PCICTL_WRITE8(sc, off, v) \ 193 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 194 195/* 196 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 197 * single PCI bus and does not have a streaming buffer. It often has an APB 198 * (advanced PCI bridge) connected to it, which was designed specifically for 199 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 200 * appears as two "Simba"'s underneath the Sabre. 201 * 202 * "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's 203 * basically the same as Sabre but without an APB underneath it. 204 * 205 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA bus 206 * and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while 207 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 208 * will usually find a "Psycho+" since I don't think the original "Psycho" 209 * ever shipped, and if it did it would be in the U30. 210 * 211 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are 212 * both part of the same IC, they only have a single register space. As such, 213 * they need to be configured together, even though the autoconfiguration will 214 * attach them separately. 215 * 216 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often 217 * as pci1 and pci2, although they have been implemented with other PCI bus 218 * numbers on some machines. 219 * 220 * On UltraII machines, there can be any number of "Psycho+" ICs, each 221 * providing two PCI buses. 222 */ 223 224#define OFW_PCI_TYPE "pci" 225 226struct psycho_desc { 227 const char *pd_string; 228 int pd_mode; 229 const char *pd_name; 230}; 231 232static const struct psycho_desc psycho_compats[] = { 233 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 234 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" }, 235 { "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" }, 236 { NULL, 0, NULL } 237}; 238 239static const struct psycho_desc psycho_models[] = { 240 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 241 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 242 { NULL, 0, NULL } 243}; 244 245static const struct psycho_desc * 246psycho_find_desc(const struct psycho_desc *table, const char *string) 247{ 248 const struct psycho_desc *desc; 249 250 if (string == NULL) 251 return (NULL); 252 for (desc = table; desc->pd_string != NULL; desc++) 253 if (strcmp(desc->pd_string, string) == 0) 254 return (desc); 255 return (NULL); 256} 257 258static const struct psycho_desc * 259psycho_get_desc(device_t dev) 260{ 261 const struct psycho_desc *rv; 262 263 rv = psycho_find_desc(psycho_models, ofw_bus_get_model(dev)); 264 if (rv == NULL) 265 rv = psycho_find_desc(psycho_compats, ofw_bus_get_compat(dev)); 266 return (rv); 267} 268 269static int 270psycho_probe(device_t dev) 271{ 272 const char *dtype; 273 274 dtype = ofw_bus_get_type(dev); 275 if (dtype != NULL && strcmp(dtype, OFW_PCI_TYPE) == 0 && 276 psycho_get_desc(dev) != NULL) { 277 device_set_desc(dev, "U2P UPA-PCI bridge"); 278 return (0); 279 } 280 281 return (ENXIO); 282} 283 284static int 285psycho_attach(device_t dev) 286{ 287 char name[sizeof("pci108e,1000")]; 288 struct psycho_softc *asc, *sc, *osc; 289 struct ofw_pci_ranges *range; 290 const struct psycho_desc *desc; 291 phandle_t child, node; 292 uint64_t csr, dr; 293 uint32_t dvmabase, psycho_br[2]; 294 int32_t rev; 295 u_int ver; 296 int i, n, nrange, rid; 297#ifdef PSYCHO_DEBUG 298 bus_addr_t map, clr; 299 uint64_t mr; 300#endif 301 302 node = ofw_bus_get_node(dev); 303 sc = device_get_softc(dev); 304 desc = psycho_get_desc(dev); 305 306 sc->sc_node = node; 307 sc->sc_dev = dev; 308 sc->sc_mode = desc->pd_mode; 309 310 /* 311 * The Psycho gets three register banks: 312 * (0) per-PBM configuration and status registers 313 * (1) per-PBM PCI configuration space, containing only the 314 * PBM 256-byte PCI header 315 * (2) the shared Psycho configuration registers 316 */ 317 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 318 rid = 2; 319 sc->sc_pcictl = 320 bus_get_resource_start(dev, SYS_RES_MEMORY, 0) - 321 bus_get_resource_start(dev, SYS_RES_MEMORY, 2); 322 switch (sc->sc_pcictl) { 323 case PSR_PCICTL0: 324 sc->sc_half = 0; 325 break; 326 case PSR_PCICTL1: 327 sc->sc_half = 1; 328 break; 329 default: 330 panic("%s: bogus PCI control register location", 331 __func__); 332 } 333 } else { 334 rid = 0; 335 sc->sc_pcictl = PSR_PCICTL0; 336 sc->sc_half = 0; 337 } 338 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 339 (sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) | 340 RF_ACTIVE); 341 if (sc->sc_mem_res == NULL) 342 panic("%s: could not allocate registers", __func__); 343 344 /* 345 * Match other Psycho's that are already configured against 346 * the base physical address. This will be the same for a 347 * pair of devices that share register space. 348 */ 349 osc = NULL; 350 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 351 if (rman_get_start(asc->sc_mem_res) == 352 rman_get_start(sc->sc_mem_res)) { 353 /* Found partner. */ 354 osc = asc; 355 break; 356 } 357 } 358 if (osc == NULL) { 359 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 360 M_NOWAIT | M_ZERO); 361 if (sc->sc_mtx == NULL) 362 panic("%s: could not malloc mutex", __func__); 363 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 364 } else { 365 if (mtx_initialized(osc->sc_mtx) == 0) 366 panic("%s: mutex not initialized", __func__); 367 sc->sc_mtx = osc->sc_mtx; 368 } 369 370 /* Clear PCI AFSR. */ 371 PCICTL_WRITE8(sc, PCR_AFS, PCIAFSR_ERRMASK); 372 373 csr = PSYCHO_READ8(sc, PSR_CS); 374 ver = PSYCHO_GCSR_VERS(csr); 375 sc->sc_ign = 0x7c0; /* Hummingbird/Sabre IGN is always 0x1f. */ 376 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 377 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << INTMAP_IGN_SHIFT; 378 379 device_printf(dev, "%s, impl %d, version %d, ign %#x, bus %c\n", 380 desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign, 381 'A' + sc->sc_half); 382 383 /* Set up the PCI control and PCI diagnostic registers. */ 384 385 /* 386 * Revision 0 EBus bridges have a bug which prevents them from 387 * working when bus parking is enabled. 388 */ 389 rev = -1; 390 csr = PCICTL_READ8(sc, PCR_CS); 391 csr &= ~PCICTL_ARB_PARK; 392 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 393 if (OF_getprop(child, "name", name, sizeof(name)) == -1) 394 continue; 395 if ((strcmp(name, "ebus") == 0 || 396 strcmp(name, "pci108e,1000") == 0) && 397 OF_getprop(child, "revision-id", &rev, sizeof(rev)) > 0 && 398 rev == 0) 399 break; 400 } 401 if (rev != 0 && OF_getproplen(node, "no-bus-parking") < 0) 402 csr |= PCICTL_ARB_PARK; 403 404 /* Workarounds for version specific bugs. */ 405 dr = PCICTL_READ8(sc, PCR_DIAG); 406 switch (ver) { 407 case 0: 408 dr |= DIAG_RTRY_DIS; 409 dr &= ~DIAG_DWSYNC_DIS; 410 /* XXX need to also disable rerun of the streaming buffers. */ 411 break; 412 case 1: 413 csr &= ~PCICTL_ARB_PARK; 414 dr |= DIAG_RTRY_DIS | DIAG_DWSYNC_DIS; 415 /* XXX need to also disable rerun of the streaming buffers. */ 416 break; 417 default: 418 dr |= DIAG_DWSYNC_DIS; 419 dr &= ~DIAG_RTRY_DIS; 420 break; 421 } 422 423 csr |= PCICTL_SERR | PCICTL_ERRINTEN | PCICTL_ARB_4; 424 csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN); 425#ifdef PSYCHO_DEBUG 426 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 427 (unsigned long long)PCICTL_READ8(sc, PCR_CS), 428 (unsigned long long)csr); 429#endif 430 PCICTL_WRITE8(sc, PCR_CS, csr); 431 432 dr &= ~DIAG_ISYNC_DIS; 433#ifdef PSYCHO_DEBUG 434 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 435 (unsigned long long)PCICTL_READ8(sc, PCR_DIAG), 436 (unsigned long long)dr); 437#endif 438 PCICTL_WRITE8(sc, PCR_DIAG, dr); 439 440 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 441 /* Use the PROM preset for now. */ 442 csr = PCICTL_READ8(sc, PCR_TAS); 443 if (csr == 0) 444 panic("%s: Hummingbird/Sabre TAS not initialized.", 445 __func__); 446 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT; 447 } else 448 dvmabase = -1; 449 450 /* Initialize memory and I/O rmans. */ 451 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 452 sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports"; 453 if (rman_init(&sc->sc_pci_io_rman) != 0 || 454 rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0) 455 panic("%s: failed to set up I/O rman", __func__); 456 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 457 sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory"; 458 if (rman_init(&sc->sc_pci_mem_rman) != 0 || 459 rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 460 panic("%s: failed to set up memory rman", __func__); 461 462 nrange = OF_getprop_alloc(node, "ranges", sizeof(*range), 463 (void **)&range); 464 /* 465 * Make sure that the expected ranges are present. The OFW_PCI_CS_MEM64 466 * one is not currently used though. 467 */ 468 if (nrange != PSYCHO_NRANGE) 469 panic("%s: unsupported number of ranges", __func__); 470 /* 471 * Find the addresses of the various bus spaces. 472 * There should not be multiple ones of one kind. 473 * The physical start addresses of the ranges are the configuration, 474 * memory and I/O handles. 475 */ 476 for (n = 0; n < PSYCHO_NRANGE; n++) { 477 i = OFW_PCI_RANGE_CS(&range[n]); 478 if (sc->sc_pci_bh[i] != 0) 479 panic("%s: duplicate range for space %d", __func__, i); 480 sc->sc_pci_bh[i] = OFW_PCI_RANGE_PHYS(&range[n]); 481 } 482 free(range, M_OFWPROP); 483 484 /* Register the softc, this is needed for paired Psychos. */ 485 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 486 487 /* 488 * Register a PCI bus error interrupt handler according to which 489 * half this is. Hummingbird/Sabre don't have a PCI bus B error 490 * interrupt but they are also only used for PCI bus A. 491 */ 492 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP : 493 PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL); 494 495 /* 496 * If we're a Hummingbird/Sabre or the first of a pair of Psycho's to 497 * arrive here, start up the IOMMU. 498 */ 499 if (osc == NULL) { 500 /* 501 * Establish handlers for interesting interrupts... 502 * 503 * XXX We need to remember these and remove this to support 504 * hotplug on the UPA/FHC bus. 505 * 506 * XXX Not all controllers have these, but installing them 507 * is better than trying to sort through this mess. 508 */ 509 psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL); 510 psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL); 511#ifdef DEBUGGER_ON_POWERFAIL 512 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, psycho_powerfail, 513 NULL); 514#else 515 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL, 516 (driver_intr_t *)psycho_powerfail); 517#endif 518 /* Psycho-specific initialization */ 519 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 520 /* 521 * Hummingbirds/Sabres do not have the following two 522 * interrupts. 523 */ 524 525 /* 526 * The spare hardware interrupt is used for the 527 * over-temperature interrupt. 528 */ 529 psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP, 530 NULL, psycho_overtemp); 531#ifdef PSYCHO_MAP_WAKEUP 532 /* 533 * psycho_wakeup() doesn't do anything useful right 534 * now. 535 */ 536 psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP, 537 psycho_wakeup, NULL); 538#endif /* PSYCHO_MAP_WAKEUP */ 539 540 /* Initialize the counter-timer. */ 541 sparc64_counter_init(rman_get_bustag(sc->sc_mem_res), 542 rman_get_bushandle(sc->sc_mem_res), PSR_TC0); 543 } 544 545 /* 546 * Set up IOMMU and PCI configuration if we're the first 547 * of a pair of Psycho's to arrive here. 548 * 549 * We should calculate a TSB size based on amount of RAM 550 * and number of bus controllers and number and type of 551 * child devices. 552 * 553 * For the moment, 32KB should be more than enough. 554 */ 555 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 556 M_NOWAIT); 557 if (sc->sc_is == NULL) 558 panic("%s: malloc iommu_state failed", __func__); 559 sc->sc_is->is_sb[0] = 0; 560 sc->sc_is->is_sb[1] = 0; 561 if (OF_getproplen(node, "no-streaming-cache") < 0) 562 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 563 psycho_iommu_init(sc, 3, dvmabase); 564 } else { 565 /* Just copy IOMMU state, config tag and address. */ 566 sc->sc_is = osc->sc_is; 567 if (OF_getproplen(node, "no-streaming-cache") < 0) 568 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 569 iommu_reset(sc->sc_is); 570 } 571 572 /* Allocate our tags. */ 573 sc->sc_pci_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 574 sc->sc_pci_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 575 sc->sc_pci_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 576 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, IOMMU_MAXADDR, ~0, 577 NULL, NULL, IOMMU_MAXADDR, 0xff, 0xffffffff, 0, NULL, NULL, 578 &sc->sc_pci_dmat) != 0) 579 panic("%s: bus_dma_tag_create failed", __func__); 580 /* Customize the tag. */ 581 sc->sc_pci_dmat->dt_cookie = sc->sc_is; 582 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 583 584#ifdef PSYCHO_DEBUG 585 /* 586 * Enable all interrupts and clear all interrupt states. 587 * This aids the debugging of interrupt routing problems. 588 */ 589 for (map = PSR_PCIA0_INT_MAP, clr = PSR_PCIA0_INT_CLR, n = 0; 590 map <= PSR_PCIB3_INT_MAP; map += 8, clr += 32, n++) { 591 mr = PSYCHO_READ8(sc, map); 592 device_printf(dev, "intr map (pci) %d: %#lx\n", n, (u_long)mr); 593 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 594 for (i = 0; i < 4; i++) 595 PCICTL_WRITE8(sc, clr + i * 8, 0); 596 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 597 } 598 for (map = PSR_SCSI_INT_MAP, clr = PSR_SCSI_INT_CLR, n = 0; 599 map <= PSR_SERIAL_INT_MAP; map += 8, clr += 8, n++) { 600 mr = PSYCHO_READ8(sc, map); 601 device_printf(dev, "intr map (obio) %d: %#lx, clr: %#lx\n", n, 602 (u_long)mr, (u_long)clr); 603 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 604 PSYCHO_WRITE8(sc, clr, 0); 605 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 606 } 607#endif /* PSYCHO_DEBUG */ 608 609 /* 610 * Get the bus range from the firmware; it is used solely for obtaining 611 * the inital bus number, and cannot be trusted on all machines. 612 */ 613 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br)); 614 if (n == -1) 615 panic("%s: could not get bus-range", __func__); 616 if (n != sizeof(psycho_br)) 617 panic("%s: broken bus-range (%d)", __func__, n); 618 619 /* Clear PCI status error bits. */ 620 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, 621 PCIR_STATUS, PCIM_STATUS_PERR | PCIM_STATUS_RMABORT | 622 PCIM_STATUS_RTABORT | PCIM_STATUS_STABORT | 623 PCIM_STATUS_PERRREPORT, 2); 624 625 /* 626 * Set the latency timer register as this isn't always done by the 627 * firmware. 628 */ 629 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, 630 PCIR_LATTIMER, 64, 1); 631 632 sc->sc_pci_secbus = sc->sc_pci_subbus = ofw_pci_alloc_busno(node); 633 /* 634 * Program the bus range registers. 635 * NOTE: for the Psycho, the second write changes the bus number the 636 * Psycho itself uses for it's configuration space, so these 637 * writes must be kept in this order! 638 * The Hummingbird/Sabre always uses bus 0, but there only can be one 639 * Hummingbird/Sabre per machine. 640 */ 641 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SUBBUS, 642 sc->sc_pci_subbus, 1); 643 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SECBUS, 644 sc->sc_pci_secbus, 1); 645 646 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 647 /* 648 * On E250 the interrupt map entry for the EBus bridge is wrong, 649 * causing incorrect interrupts to be assigned to some devices on 650 * the EBus. Work around it by changing our copy of the interrupt 651 * map mask to perform a full comparison of the INO. That way 652 * the interrupt map entry for the EBus bridge won't match at all 653 * and the INOs specified in the "interrupts" properties of the 654 * EBus devices will be used directly instead. 655 */ 656 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 && 657 sc->sc_pci_iinfo.opi_imapmsk != NULL) 658 *(ofw_pci_intr_t *)(&sc->sc_pci_iinfo.opi_imapmsk[ 659 sc->sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK; 660 661 device_add_child(dev, "pci", sc->sc_pci_secbus); 662 return (bus_generic_attach(dev)); 663} 664 665static void 666psycho_set_intr(struct psycho_softc *sc, int index, bus_addr_t map, 667 driver_filter_t filt, driver_intr_t intr) 668{ 669 uint64_t mr; 670 int rid; 671 672 rid = index; 673 mr = PSYCHO_READ8(sc, map); 674 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ, 675 &rid, RF_ACTIVE); 676 if (sc->sc_irq_res[index] == NULL || 677 rman_get_start(sc->sc_irq_res[index]) != INTVEC(mr) || 678 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], INTR_TYPE_MISC, 679 filt, intr, sc, &sc->sc_ihand[index]) != 0) 680 panic("%s: failed to set up interrupt %d", __func__, index); 681 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 682} 683 684static int 685psycho_find_intrmap(struct psycho_softc *sc, int ino, bus_addr_t *intrmapptr, 686 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 687{ 688 bus_addr_t intrmap, intrclr; 689 uint64_t im; 690 u_long diag; 691 int found; 692 693 found = 0; 694 /* Hunt thru OBIO first. */ 695 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 696 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 697 intrmap <= PSR_SERIAL_INT_MAP; intrmap += 8, intrclr += 8, 698 diag >>= 2) { 699 im = PSYCHO_READ8(sc, intrmap); 700 if (INTINO(im) == ino) { 701 diag &= 2; 702 found = 1; 703 break; 704 } 705 } 706 707 if (!found) { 708 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 709 /* Now do PCI interrupts. */ 710 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 711 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 712 diag >>= 8) { 713 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 714 (intrmap == PSR_PCIA2_INT_MAP || 715 intrmap == PSR_PCIA3_INT_MAP)) 716 continue; 717 im = PSYCHO_READ8(sc, intrmap); 718 if (((im ^ ino) & 0x3c) == 0) { 719 intrclr += 8 * (ino & 3); 720 diag = (diag >> ((ino & 3) * 2)) & 2; 721 found = 1; 722 break; 723 } 724 } 725 } 726 if (intrmapptr != NULL) 727 *intrmapptr = intrmap; 728 if (intrclrptr != NULL) 729 *intrclrptr = intrclr; 730 if (intrdiagptr != NULL) 731 *intrdiagptr = diag; 732 return (found); 733} 734 735/* 736 * Interrupt handlers 737 */ 738static int 739psycho_ue(void *arg) 740{ 741 struct psycho_softc *sc = arg; 742 uint64_t afar, afsr; 743 744 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 745 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 746 /* 747 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 748 * the AFAR to be set to the physical address of the TTE entry that 749 * was invalid/write protected. Call into the iommu code to have 750 * them decoded to virtual I/O addresses. 751 */ 752 if ((afsr & UEAFSR_P_DTE) != 0) 753 iommu_decode_fault(sc->sc_is, afar); 754 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx", 755 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 756 return (FILTER_HANDLED); 757} 758 759static int 760psycho_ce(void *arg) 761{ 762 struct psycho_softc *sc = arg; 763 uint64_t afar, afsr; 764 765 mtx_lock_spin(sc->sc_mtx); 766 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 767 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 768 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx " 769 "AFSR %#lx\n", (u_long)afar, (u_long)afsr); 770 /* Clear the error bits that we caught. */ 771 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr & CEAFSR_ERRMASK); 772 PSYCHO_WRITE8(sc, PSR_CE_INT_CLR, 0); 773 mtx_unlock_spin(sc->sc_mtx); 774 return (FILTER_HANDLED); 775} 776 777static int 778psycho_pci_bus(void *arg) 779{ 780 struct psycho_softc *sc = arg; 781 uint64_t afar, afsr; 782 783 afar = PCICTL_READ8(sc, PCR_AFA); 784 afsr = PCICTL_READ8(sc, PCR_AFS); 785 panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx", 786 device_get_name(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar, 787 (u_long)afsr); 788 return (FILTER_HANDLED); 789} 790 791static int 792psycho_powerfail(void *arg) 793{ 794#ifdef DEBUGGER_ON_POWERFAIL 795 struct psycho_softc *sc = arg; 796 797 kdb_enter("powerfail"); 798 PSYCHO_WRITE8(sc, PSR_POWER_INT_CLR, 0); 799#else 800 printf("Power Failure Detected: Shutting down NOW.\n"); 801 shutdown_nice(0); 802#endif 803 return (FILTER_HANDLED); 804} 805 806static void 807psycho_overtemp(void *arg) 808{ 809 810 printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n"); 811 shutdown_nice(RB_POWEROFF); 812} 813 814#ifdef PSYCHO_MAP_WAKEUP 815static int 816psycho_wakeup(void *arg) 817{ 818 struct psycho_softc *sc = arg; 819 820 PSYCHO_WRITE8(sc, PSR_PWRMGT_INT_CLR, 0); 821 /* Gee, we don't really have a framework to deal with this properly. */ 822 device_printf(sc->sc_dev, "power management wakeup\n"); 823 return (FILTER_HANDLED); 824} 825#endif /* PSYCHO_MAP_WAKEUP */ 826 827static void 828psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase) 829{ 830 char *name; 831 struct iommu_state *is = sc->sc_is; 832 833 /* Punch in our copies. */ 834 is->is_bustag = rman_get_bustag(sc->sc_mem_res); 835 is->is_bushandle = rman_get_bushandle(sc->sc_mem_res); 836 is->is_iommu = PSR_IOMMU; 837 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 838 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 839 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 840 is->is_dva = PSR_IOMMU_SVADIAG; 841 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 842 843 /* Give us a nice name... */ 844 name = malloc(32, M_DEVBUF, M_NOWAIT); 845 if (name == NULL) 846 panic("%s: could not malloc iommu name", __func__); 847 snprintf(name, 32, "%s dvma", device_get_nameunit(sc->sc_dev)); 848 849 iommu_init(name, is, tsbsize, dvmabase, 0); 850} 851 852static int 853psycho_maxslots(device_t dev) 854{ 855 856 /* XXX: is this correct? */ 857 return (PCI_SLOTMAX); 858} 859 860static uint32_t 861psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 862 int width) 863{ 864 struct psycho_softc *sc; 865 bus_space_handle_t bh; 866 u_long offset = 0; 867 uint8_t byte; 868 uint16_t shrt; 869 uint32_t wrd; 870 uint32_t r; 871 int i; 872 873 sc = device_get_softc(dev); 874 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 875 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 876 switch (width) { 877 case 1: 878 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 879 r = byte; 880 break; 881 case 2: 882 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 883 r = shrt; 884 break; 885 case 4: 886 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 887 r = wrd; 888 break; 889 default: 890 panic("%s: bad width", __func__); 891 } 892 893 if (i) { 894#ifdef PSYCHO_DEBUG 895 printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 896 __func__, bus, slot, func, reg); 897#endif 898 r = -1; 899 } 900 return (r); 901} 902 903static void 904psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 905 uint32_t val, int width) 906{ 907 struct psycho_softc *sc; 908 bus_space_handle_t bh; 909 u_long offset = 0; 910 911 sc = device_get_softc(dev); 912 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 913 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 914 switch (width) { 915 case 1: 916 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 917 break; 918 case 2: 919 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 920 break; 921 case 4: 922 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 923 break; 924 default: 925 panic("%s: bad width", __func__); 926 } 927} 928 929static int 930psycho_route_interrupt(device_t bridge, device_t dev, int pin) 931{ 932 struct psycho_softc *sc; 933 struct ofw_pci_register reg; 934 bus_addr_t intrmap; 935 ofw_pci_intr_t pintr, mintr; 936 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 937 938 sc = device_get_softc(bridge); 939 pintr = pin; 940 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, 941 sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) 942 return (mintr); 943 /* 944 * If this is outside of the range for an intpin, it's likely a full 945 * INO, and no mapping is required at all; this happens on the U30, 946 * where there's no interrupt map at the Psycho node. Fortunately, 947 * there seem to be no INOs in the intpin range on this boxen, so 948 * this easy heuristics will do. 949 */ 950 if (pin > 4) 951 return (pin); 952 /* 953 * Guess the INO; we always assume that this is a non-OBIO 954 * device, and that pin is a "real" intpin number. Determine 955 * the mapping register to be used by the slot number. 956 * We only need to do this on E450s, it seems; here, the slot numbers 957 * for bus A are one-based, while those for bus B seemingly have an 958 * offset of 2 (hence the factor of 3 below). 959 */ 960 intrmap = PSR_PCIA0_INT_MAP + 961 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half); 962 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1; 963 device_printf(bridge, "guessing interrupt %d for device %d.%d pin %d\n", 964 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin); 965 return (mintr); 966} 967 968static int 969psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 970{ 971 struct psycho_softc *sc; 972 973 sc = device_get_softc(dev); 974 switch (which) { 975 case PCIB_IVAR_BUS: 976 *result = sc->sc_pci_secbus; 977 return (0); 978 } 979 return (ENOENT); 980} 981 982static int 983psycho_filter_stub(void *arg) 984{ 985 struct psycho_clr *pc = arg; 986 int res; 987 988 if (pc->pci_filter != NULL) { 989 res = pc->pci_filter(pc->pci_arg); 990 PSYCHO_WRITE8(pc->pci_sc, pc->pci_clr, 0); 991 } else 992 res = FILTER_SCHEDULE_THREAD; 993 return (res); 994} 995 996static void 997psycho_intr_stub(void *arg) 998{ 999 struct psycho_clr *pc = arg; 1000 1001 if (pc->pci_ppb != NULL) { 1002 (void)PCIB_READ_CONFIG(pc->pci_ppb, pc->pci_bus, pc->pci_slot, 1003 pc->pci_func, PCIR_VENDOR, 2); 1004 (void)PSYCHO_READ8(pc->pci_sc, PSR_DMA_WRITE_SYNC); 1005 } 1006 pc->pci_handler(pc->pci_arg); 1007 if (pc->pci_filter == NULL) 1008 PSYCHO_WRITE8(pc->pci_sc, pc->pci_clr, 0); 1009} 1010 1011static int 1012psycho_setup_intr(device_t dev, device_t child, struct resource *ires, 1013 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1014 void **cookiep) 1015{ 1016 struct { 1017 int apb:1; 1018 int ppb:1; 1019 } found; 1020 devclass_t pci_devclass; 1021 device_t cdev, pdev, pcidev; 1022 struct psycho_softc *sc; 1023 struct psycho_clr *pc; 1024 bus_addr_t intrmapptr, intrclrptr; 1025 long vec; 1026 uint64_t mr; 1027 int error, ino; 1028 1029 if (filt != NULL && intr != NULL) 1030 return (EINVAL); 1031 1032 sc = device_get_softc(dev); 1033 pc = malloc(sizeof(*pc), M_DEVBUF, M_NOWAIT | M_ZERO); 1034 if (pc == NULL) 1035 return (ENOMEM); 1036 1037 /* 1038 * Hunt through all the interrupt mapping regs to look for our 1039 * interrupt vector. 1040 * 1041 * XXX We only compare INOs rather than IGNs since the firmware may 1042 * not provide the IGN and the IGN is constant for all devices on that 1043 * PCI controller. This could cause problems for the FFB/external 1044 * interrupt which has a full vector that can be set arbitrarily. 1045 */ 1046 vec = rman_get_start(ires); 1047 ino = INTINO(vec); 1048 if (!psycho_find_intrmap(sc, ino, &intrmapptr, &intrclrptr, NULL)) { 1049 device_printf(dev, "cannot find interrupt vector 0x%lx\n", vec); 1050 free(pc, M_DEVBUF); 1051 return (EINVAL); 1052 } 1053 1054#ifdef PSYCHO_DEBUG 1055 device_printf(dev, "%s: INO %d, map %#lx, clr %#lx\n", __func__, ino, 1056 (u_long)intrmapptr, (u_long)intrclrptr); 1057#endif 1058 1059 pc->pci_sc = sc; 1060 pc->pci_arg = arg; 1061 pc->pci_filter = filt; 1062 pc->pci_handler = intr; 1063 pc->pci_clr = intrclrptr; 1064 1065 /* 1066 * The Sabre-APB-combination has a bug where it does not drain 1067 * DMA write data for devices behind additional PCI-PCI bridges 1068 * underneath the APB PCI-PCI bridge. The workaround is to do 1069 * a read on the farest PCI-PCI bridge followed by a read of the 1070 * PCI DMA write sync register of the Sabre. 1071 * XXX installing the workaround for an affected device and the 1072 * actual workaround in psycho_intr_stub() should be moved to 1073 * psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() 1074 * methods, respectively, once we make use of BUS_GET_DMA_TAG(), 1075 * so the workaround isn't only applied for interrupt handlers 1076 * but also for polling(4) callbacks. 1077 */ 1078 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 1079 pcidev = NULL; 1080 found.apb = found.ppb = 0; 1081 pci_devclass = devclass_find("pci"); 1082 for (cdev = child; cdev != dev; cdev = pdev) { 1083 pdev = device_get_parent(cdev); 1084 if (pcidev == NULL) { 1085 if (device_get_devclass(pdev) != pci_devclass) 1086 continue; 1087 pcidev = cdev; 1088 continue; 1089 } 1090 /* 1091 * NB: APB would also match as PCI-PCI bridges. 1092 */ 1093 if (pci_get_vendor(cdev) == 0x108e && 1094 pci_get_device(cdev) == 0x5000) { 1095 found.apb = 1; 1096 break; 1097 } 1098 if (pci_get_class(cdev) == PCIC_BRIDGE && 1099 pci_get_subclass(cdev) == PCIS_BRIDGE_PCI) 1100 found.ppb = 1; 1101 } 1102 if (found.apb && found.ppb && pcidev != NULL) { 1103 pc->pci_ppb = 1104 device_get_parent(device_get_parent(pcidev)); 1105 pc->pci_bus = pci_get_bus(pcidev); 1106 pc->pci_slot = pci_get_slot(pcidev); 1107 pc->pci_func = pci_get_function(pcidev); 1108 if (bootverbose) 1109 device_printf(dev, "installed DMA sync " 1110 "workaround for device %d.%d on bus %d\n", 1111 pc->pci_slot, pc->pci_func, pc->pci_bus); 1112 } 1113 } 1114 1115 /* Disable the interrupt while we fiddle with it. */ 1116 mr = PSYCHO_READ8(sc, intrmapptr); 1117 PSYCHO_WRITE8(sc, intrmapptr, mr & ~INTMAP_V); 1118 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 1119 psycho_filter_stub, psycho_intr_stub, pc, cookiep); 1120 if (error != 0) { 1121 free(pc, M_DEVBUF); 1122 return (error); 1123 } 1124 pc->pci_cookie = *cookiep; 1125 *cookiep = pc; 1126 1127 /* 1128 * Clear the interrupt, it might have been triggered before it was 1129 * set up. 1130 */ 1131 PSYCHO_WRITE8(sc, intrclrptr, 0); 1132 /* 1133 * Enable the interrupt and program the target module now we have the 1134 * handler installed. 1135 */ 1136 PSYCHO_WRITE8(sc, intrmapptr, INTMAP_ENABLE(mr, PCPU_GET(mid))); 1137 return (error); 1138} 1139 1140static int 1141psycho_teardown_intr(device_t dev, device_t child, struct resource *vec, 1142 void *cookie) 1143{ 1144 struct psycho_clr *pc = cookie; 1145 int error; 1146 1147 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 1148 pc->pci_cookie); 1149 /* 1150 * Don't disable the interrupt for now, so that stray interupts get 1151 * detected... 1152 */ 1153 if (error != 0) 1154 free(pc, M_DEVBUF); 1155 return (error); 1156} 1157 1158static struct resource * 1159psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1160 u_long start, u_long end, u_long count, u_int flags) 1161{ 1162 struct psycho_softc *sc; 1163 struct resource *rv; 1164 struct rman *rm; 1165 bus_space_tag_t bt; 1166 bus_space_handle_t bh; 1167 int needactivate = flags & RF_ACTIVE; 1168 1169 flags &= ~RF_ACTIVE; 1170 1171 sc = device_get_softc(bus); 1172 if (type == SYS_RES_IRQ) { 1173 /* 1174 * XXX: Don't accept blank ranges for now, only single 1175 * interrupts. The other case should not happen with the 1176 * MI PCI code... 1177 * XXX: This may return a resource that is out of the 1178 * range that was specified. Is this correct...? 1179 */ 1180 if (start != end) 1181 panic("%s: XXX: interrupt range", __func__); 1182 start = end |= sc->sc_ign; 1183 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, 1184 rid, start, end, count, flags)); 1185 } 1186 switch (type) { 1187 case SYS_RES_MEMORY: 1188 rm = &sc->sc_pci_mem_rman; 1189 bt = sc->sc_pci_memt; 1190 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1191 break; 1192 case SYS_RES_IOPORT: 1193 rm = &sc->sc_pci_io_rman; 1194 bt = sc->sc_pci_iot; 1195 bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1196 break; 1197 default: 1198 return (NULL); 1199 } 1200 1201 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1202 if (rv == NULL) 1203 return (NULL); 1204 rman_set_rid(rv, *rid); 1205 bh += rman_get_start(rv); 1206 rman_set_bustag(rv, bt); 1207 rman_set_bushandle(rv, bh); 1208 1209 if (needactivate) { 1210 if (bus_activate_resource(child, type, *rid, rv)) { 1211 rman_release_resource(rv); 1212 return (NULL); 1213 } 1214 } 1215 1216 return (rv); 1217} 1218 1219static int 1220psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1221 struct resource *r) 1222{ 1223 void *p; 1224 int error; 1225 1226 if (type == SYS_RES_IRQ) 1227 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1228 type, rid, r)); 1229 if (type == SYS_RES_MEMORY) { 1230 /* 1231 * Need to memory-map the device space, as some drivers depend 1232 * on the virtual address being set and useable. 1233 */ 1234 error = sparc64_bus_mem_map(rman_get_bustag(r), 1235 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1236 if (error != 0) 1237 return (error); 1238 rman_set_virtual(r, p); 1239 } 1240 return (rman_activate_resource(r)); 1241} 1242 1243static int 1244psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1245 struct resource *r) 1246{ 1247 1248 if (type == SYS_RES_IRQ) 1249 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1250 type, rid, r)); 1251 if (type == SYS_RES_MEMORY) { 1252 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1253 rman_set_virtual(r, NULL); 1254 } 1255 return (rman_deactivate_resource(r)); 1256} 1257 1258static int 1259psycho_release_resource(device_t bus, device_t child, int type, int rid, 1260 struct resource *r) 1261{ 1262 int error; 1263 1264 if (type == SYS_RES_IRQ) 1265 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1266 type, rid, r)); 1267 if (rman_get_flags(r) & RF_ACTIVE) { 1268 error = bus_deactivate_resource(child, type, rid, r); 1269 if (error) 1270 return error; 1271 } 1272 return (rman_release_resource(r)); 1273} 1274 1275static bus_dma_tag_t 1276psycho_get_dma_tag(device_t bus, device_t child) 1277{ 1278 struct psycho_softc *sc; 1279 1280 sc = device_get_softc(bus); 1281 return (sc->sc_pci_dmat); 1282} 1283 1284static int 1285psycho_intr_pending(device_t dev, ofw_pci_intr_t intr) 1286{ 1287 struct psycho_softc *sc; 1288 u_long diag; 1289 1290 sc = device_get_softc(dev); 1291 if (!psycho_find_intrmap(sc, intr, NULL, NULL, &diag)) { 1292 device_printf(dev, "%s: mapping not found for %d\n", __func__, 1293 intr); 1294 return (0); 1295 } 1296 return (diag != 0); 1297} 1298 1299static phandle_t 1300psycho_get_node(device_t bus, device_t dev) 1301{ 1302 struct psycho_softc *sc; 1303 1304 sc = device_get_softc(bus); 1305 /* We only have one child, the PCI bus, which needs our own node. */ 1306 return (sc->sc_node); 1307} 1308 1309static void 1310psycho_adjust_busrange(device_t dev, u_int subbus) 1311{ 1312 struct psycho_softc *sc; 1313 1314 sc = device_get_softc(dev); 1315 /* If necessary, adjust the subordinate bus number register. */ 1316 if (subbus > sc->sc_pci_subbus) { 1317#ifdef PSYCHO_DEBUG 1318 device_printf(dev, 1319 "adjusting subordinate bus number from %d to %d\n", 1320 sc->sc_pci_subbus, subbus); 1321#endif 1322 sc->sc_pci_subbus = subbus; 1323 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, 1324 PCSR_SUBBUS, subbus, 1); 1325 } 1326} 1327 1328static bus_space_tag_t 1329psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1330{ 1331 bus_space_tag_t bt; 1332 1333 bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF, M_NOWAIT | M_ZERO); 1334 if (bt == NULL) 1335 panic("%s: out of memory", __func__); 1336 1337 bt->bst_cookie = sc; 1338 bt->bst_parent = rman_get_bustag(sc->sc_mem_res); 1339 bt->bst_type = type; 1340 return (bt); 1341} 1342