psycho.c revision 166901
1/*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: head/sys/sparc64/pci/psycho.c 166901 2007-02-23 12:19:07Z piso $"); 34 35/* 36 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+' 37 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges. 38 */ 39 40#include "opt_ofw_pci.h" 41#include "opt_psycho.h" 42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/bus.h> 46#include <sys/kdb.h> 47#include <sys/kernel.h> 48#include <sys/module.h> 49#include <sys/malloc.h> 50#include <sys/pcpu.h> 51#include <sys/reboot.h> 52 53#include <dev/ofw/ofw_bus.h> 54#include <dev/ofw/ofw_pci.h> 55#include <dev/ofw/openfirm.h> 56 57#include <machine/bus.h> 58#include <machine/bus_private.h> 59#include <machine/bus_common.h> 60#include <machine/iommureg.h> 61#include <machine/nexusvar.h> 62#include <machine/ofw_bus.h> 63#include <machine/ofw_upa.h> 64#include <machine/resource.h> 65#include <machine/ver.h> 66 67#include <sys/rman.h> 68 69#include <machine/iommuvar.h> 70 71#include <dev/pci/pcireg.h> 72#include <dev/pci/pcivar.h> 73 74#include <sparc64/pci/ofw_pci.h> 75#include <sparc64/pci/psychoreg.h> 76#include <sparc64/pci/psychovar.h> 77 78#include "pcib_if.h" 79 80static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *, 81 const char *); 82static const struct psycho_desc *psycho_get_desc(phandle_t, const char *); 83static void psycho_set_intr(struct psycho_softc *, int, bus_addr_t, int, 84 driver_filter_t); 85static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *, 86 bus_addr_t *, u_long *); 87static int psycho_intr_stub(void *); 88static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 89 90/* Interrupt handlers */ 91static int psycho_ue(void *); 92static int psycho_ce(void *); 93static int psycho_pci_bus(void *); 94static int psycho_powerfail(void *); 95static int psycho_overtemp(void *); 96#ifdef PSYCHO_MAP_WAKEUP 97static int psycho_wakeup(void *); 98#endif 99 100/* IOMMU support */ 101static void psycho_iommu_init(struct psycho_softc *, int, uint32_t); 102 103/* 104 * Methods 105 */ 106static device_probe_t psycho_probe; 107static device_attach_t psycho_attach; 108static bus_read_ivar_t psycho_read_ivar; 109static bus_setup_intr_t psycho_setup_intr; 110static bus_teardown_intr_t psycho_teardown_intr; 111static bus_alloc_resource_t psycho_alloc_resource; 112static bus_activate_resource_t psycho_activate_resource; 113static bus_deactivate_resource_t psycho_deactivate_resource; 114static bus_release_resource_t psycho_release_resource; 115static pcib_maxslots_t psycho_maxslots; 116static pcib_read_config_t psycho_read_config; 117static pcib_write_config_t psycho_write_config; 118static pcib_route_interrupt_t psycho_route_interrupt; 119static ofw_pci_intr_pending_t psycho_intr_pending; 120static ofw_bus_get_node_t psycho_get_node; 121static ofw_pci_adjust_busrange_t psycho_adjust_busrange; 122 123static device_method_t psycho_methods[] = { 124 /* Device interface */ 125 DEVMETHOD(device_probe, psycho_probe), 126 DEVMETHOD(device_attach, psycho_attach), 127 DEVMETHOD(device_shutdown, bus_generic_shutdown), 128 DEVMETHOD(device_suspend, bus_generic_suspend), 129 DEVMETHOD(device_resume, bus_generic_resume), 130 131 /* Bus interface */ 132 DEVMETHOD(bus_print_child, bus_generic_print_child), 133 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 134 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 135 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 136 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 137 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 138 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 139 DEVMETHOD(bus_release_resource, psycho_release_resource), 140 141 /* pcib interface */ 142 DEVMETHOD(pcib_maxslots, psycho_maxslots), 143 DEVMETHOD(pcib_read_config, psycho_read_config), 144 DEVMETHOD(pcib_write_config, psycho_write_config), 145 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 146 147 /* ofw_bus interface */ 148 DEVMETHOD(ofw_bus_get_node, psycho_get_node), 149 150 /* ofw_pci interface */ 151 DEVMETHOD(ofw_pci_intr_pending, psycho_intr_pending), 152 DEVMETHOD(ofw_pci_adjust_busrange, psycho_adjust_busrange), 153 154 { 0, 0 } 155}; 156 157static driver_t psycho_driver = { 158 "pcib", 159 psycho_methods, 160 sizeof(struct psycho_softc), 161}; 162 163static devclass_t psycho_devclass; 164 165DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 166 167SLIST_HEAD(, psycho_softc) psycho_softcs = 168 SLIST_HEAD_INITIALIZER(psycho_softcs); 169 170struct psycho_clr { 171 struct psycho_softc *pci_sc; 172 bus_addr_t pci_clr; /* clear register */ 173 driver_filter_t *pci_handler; /* handler to call */ 174 void *pci_arg; /* argument for the handler */ 175 void *pci_cookie; /* parent bus int. cookie */ 176 device_t pci_ppb; /* farest PCI-PCI bridge */ 177 uint8_t pci_bus; /* bus of farest PCI device */ 178 uint8_t pci_slot; /* slot of farest PCI device */ 179 uint8_t pci_func; /* func. of farest PCI device */ 180}; 181 182#define PSYCHO_READ8(sc, off) \ 183 bus_space_read_8((sc)->sc_bustag, (sc)->sc_bushandle, (off)) 184#define PSYCHO_WRITE8(sc, off, v) \ 185 bus_space_write_8((sc)->sc_bustag, (sc)->sc_bushandle, (off), (v)) 186#define PCICTL_READ8(sc, off) \ 187 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 188#define PCICTL_WRITE8(sc, off, v) \ 189 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 190 191/* 192 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 193 * single PCI bus and does not have a streaming buffer. It often has an APB 194 * (advanced PCI bridge) connected to it, which was designed specifically for 195 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 196 * appears as two "Simba"'s underneath the Sabre. 197 * 198 * "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's 199 * basically the same as Sabre but without an APB underneath it. 200 * 201 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA bus 202 * and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while 203 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 204 * will usually find a "Psycho+" since I don't think the original "Psycho" 205 * ever shipped, and if it did it would be in the U30. 206 * 207 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are 208 * both part of the same IC, they only have a single register space. As such, 209 * they need to be configured together, even though the autoconfiguration will 210 * attach them separately. 211 * 212 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often 213 * as pci1 and pci2, although they have been implemented with other PCI bus 214 * numbers on some machines. 215 * 216 * On UltraII machines, there can be any number of "Psycho+" ICs, each 217 * providing two PCI buses. 218 */ 219 220#define FAST 0x66600000 221 222#ifdef DEBUGGER_ON_POWERFAIL 223#define PSYCHO_PWRFAIL_INT_FLAGS FAST 224#else 225#define PSYCHO_PWRFAIL_INT_FLAGS 0 226#endif 227 228#define OFW_PCI_TYPE "pci" 229 230struct psycho_desc { 231 const char *pd_string; 232 int pd_mode; 233 const char *pd_name; 234}; 235 236static const struct psycho_desc psycho_compats[] = { 237 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 238 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" }, 239 { "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" }, 240 { NULL, 0, NULL } 241}; 242 243static const struct psycho_desc psycho_models[] = { 244 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 245 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 246 { NULL, 0, NULL } 247}; 248 249static const struct psycho_desc * 250psycho_find_desc(const struct psycho_desc *table, const char *string) 251{ 252 const struct psycho_desc *desc; 253 254 for (desc = table; desc->pd_string != NULL; desc++) { 255 if (strcmp(desc->pd_string, string) == 0) 256 return (desc); 257 } 258 return (NULL); 259} 260 261static const struct psycho_desc * 262psycho_get_desc(phandle_t node, const char *model) 263{ 264 const struct psycho_desc *rv; 265 char compat[32]; 266 267 rv = NULL; 268 if (model != NULL) 269 rv = psycho_find_desc(psycho_models, model); 270 if (rv == NULL && 271 OF_getprop(node, "compatible", compat, sizeof(compat)) != -1) 272 rv = psycho_find_desc(psycho_compats, compat); 273 return (rv); 274} 275 276static int 277psycho_probe(device_t dev) 278{ 279 const char *dtype; 280 281 dtype = nexus_get_device_type(dev); 282 if (nexus_get_reg(dev) != NULL && dtype != NULL && 283 strcmp(dtype, OFW_PCI_TYPE) == 0 && 284 psycho_get_desc(nexus_get_node(dev), 285 nexus_get_model(dev)) != NULL) { 286 device_set_desc(dev, "U2P UPA-PCI bridge"); 287 return (0); 288 } 289 290 return (ENXIO); 291} 292 293static int 294psycho_attach(device_t dev) 295{ 296 char name[sizeof("pci108e,1000")]; 297 struct psycho_softc *asc, *sc, *osc; 298 struct ofw_pci_ranges *range; 299 struct upa_regs *reg; 300 const struct psycho_desc *desc; 301 phandle_t child, node; 302 uint64_t csr, dr; 303 uint32_t dvmabase, psycho_br[2]; 304 int32_t rev; 305 u_long mlen; 306 u_int ver; 307 int n, i, nrange, nreg, rid; 308#ifdef PSYCHO_DEBUG 309 bus_addr_t map, clr; 310 uint64_t mr; 311#endif 312 313 node = nexus_get_node(dev); 314 sc = device_get_softc(dev); 315 desc = psycho_get_desc(node, nexus_get_model(dev)); 316 317 sc->sc_node = node; 318 sc->sc_dev = dev; 319 sc->sc_mode = desc->pd_mode; 320 321 /* 322 * The Psycho gets three register banks: 323 * (0) per-PBM configuration and status registers 324 * (1) per-PBM PCI configuration space, containing only the 325 * PBM 256-byte PCI header 326 * (2) the shared Psycho configuration registers 327 */ 328 reg = nexus_get_reg(dev); 329 nreg = nexus_get_nreg(dev); 330 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 331 if (nreg <= 2) 332 panic("%s: %d not enough registers", __func__, nreg); 333 sc->sc_basepaddr = (vm_paddr_t)UPA_REG_PHYS(®[2]); 334 mlen = UPA_REG_SIZE(®[2]); 335 sc->sc_pcictl = UPA_REG_PHYS(®[0]) - sc->sc_basepaddr; 336 switch (sc->sc_pcictl) { 337 case PSR_PCICTL0: 338 sc->sc_half = 0; 339 break; 340 case PSR_PCICTL1: 341 sc->sc_half = 1; 342 break; 343 default: 344 panic("%s: bogus PCI control register location", 345 __func__); 346 } 347 } else { 348 if (nreg <= 0) 349 panic("%s: %d not enough registers", __func__, nreg); 350 sc->sc_basepaddr = (vm_paddr_t)UPA_REG_PHYS(®[0]); 351 mlen = UPA_REG_SIZE(reg); 352 sc->sc_pcictl = PSR_PCICTL0; 353 sc->sc_half = 0; 354 } 355 356 /* 357 * Match other Psycho's that are already configured against 358 * the base physical address. This will be the same for a 359 * pair of devices that share register space. 360 */ 361 osc = NULL; 362 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 363 if (asc->sc_basepaddr == sc->sc_basepaddr) { 364 /* Found partner. */ 365 osc = asc; 366 break; 367 } 368 } 369 370 if (osc == NULL) { 371 rid = 0; 372 sc->sc_mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 373 sc->sc_basepaddr, sc->sc_basepaddr + mlen - 1, mlen, 374 RF_ACTIVE); 375 if (sc->sc_mem_res == NULL || 376 rman_get_start(sc->sc_mem_res) != sc->sc_basepaddr) 377 panic("%s: could not allocate device memory", __func__); 378 sc->sc_bustag = rman_get_bustag(sc->sc_mem_res); 379 sc->sc_bushandle = rman_get_bushandle(sc->sc_mem_res); 380 } else { 381 /* 382 * There's another Psycho using the same register space. 383 * Copy the relevant stuff. 384 */ 385 sc->sc_mem_res = NULL; 386 sc->sc_bustag = osc->sc_bustag; 387 sc->sc_bushandle = osc->sc_bushandle; 388 } 389 390 /* Clear PCI AFSR. */ 391 PCICTL_WRITE8(sc, PCR_AFS, PCIAFSR_ERRMASK); 392 393 csr = PSYCHO_READ8(sc, PSR_CS); 394 ver = PSYCHO_GCSR_VERS(csr); 395 sc->sc_ign = 0x7c0; /* Hummingbird/Sabre IGN is always 0x1f. */ 396 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 397 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << INTMAP_IGN_SHIFT; 398 399 device_printf(dev, "%s, impl %d, version %d, ign %#x, bus %c\n", 400 desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign, 401 'A' + sc->sc_half); 402 403 /* Set up the PCI control and PCI diagnostic registers. */ 404 405 /* 406 * Revision 0 EBus bridges have a bug which prevents them from 407 * working when bus parking is enabled. 408 */ 409 rev = -1; 410 csr = PCICTL_READ8(sc, PCR_CS); 411 csr &= ~PCICTL_ARB_PARK; 412 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 413 if (OF_getprop(child, "name", name, sizeof(name)) == -1) 414 continue; 415 if ((strcmp(name, "ebus") == 0 || 416 strcmp(name, "pci108e,1000") == 0) && 417 OF_getprop(child, "revision-id", &rev, sizeof(rev)) > 0 && 418 rev == 0) 419 break; 420 } 421 if (rev != 0 && OF_getproplen(node, "no-bus-parking") < 0) 422 csr |= PCICTL_ARB_PARK; 423 424 /* Workarounds for version specific bugs. */ 425 dr = PCICTL_READ8(sc, PCR_DIAG); 426 switch (ver) { 427 case 0: 428 dr |= DIAG_RTRY_DIS; 429 dr &= ~DIAG_DWSYNC_DIS; 430 /* XXX need to also disable rerun of the streaming buffers. */ 431 break; 432 case 1: 433 csr &= ~PCICTL_ARB_PARK; 434 dr |= DIAG_RTRY_DIS | DIAG_DWSYNC_DIS; 435 /* XXX need to also disable rerun of the streaming buffers. */ 436 break; 437 default: 438 dr |= DIAG_DWSYNC_DIS; 439 dr &= ~DIAG_RTRY_DIS; 440 break; 441 } 442 443 csr |= PCICTL_SERR | PCICTL_ERRINTEN | PCICTL_ARB_4; 444 csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN); 445#ifdef PSYCHO_DEBUG 446 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 447 (unsigned long long)PCICTL_READ8(sc, PCR_CS), 448 (unsigned long long)csr); 449#endif 450 PCICTL_WRITE8(sc, PCR_CS, csr); 451 452 dr &= ~DIAG_ISYNC_DIS; 453#ifdef PSYCHO_DEBUG 454 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 455 (unsigned long long)PCICTL_READ8(sc, PCR_DIAG), 456 (unsigned long long)dr); 457#endif 458 PCICTL_WRITE8(sc, PCR_DIAG, dr); 459 460 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 461 /* Use the PROM preset for now. */ 462 csr = PCICTL_READ8(sc, PCR_TAS); 463 if (csr == 0) 464 panic("%s: Hummingbird/Sabre TAS not initialized.", 465 __func__); 466 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT; 467 } else 468 dvmabase = -1; 469 470 /* Initialize memory and I/O rmans. */ 471 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 472 sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports"; 473 if (rman_init(&sc->sc_pci_io_rman) != 0 || 474 rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0) 475 panic("%s: failed to set up I/O rman", __func__); 476 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 477 sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory"; 478 if (rman_init(&sc->sc_pci_mem_rman) != 0 || 479 rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 480 panic("%s: failed to set up memory rman", __func__); 481 482 nrange = OF_getprop_alloc(node, "ranges", sizeof(*range), 483 (void **)&range); 484 /* 485 * Make sure that the expected ranges are present. The OFW_PCI_CS_MEM64 486 * one is not currently used though. 487 */ 488 if (nrange != PSYCHO_NRANGE) 489 panic("%s: unsupported number of ranges", __func__); 490 /* 491 * Find the addresses of the various bus spaces. 492 * There should not be multiple ones of one kind. 493 * The physical start addresses of the ranges are the configuration, 494 * memory and I/O handles. 495 */ 496 for (n = 0; n < PSYCHO_NRANGE; n++) { 497 i = OFW_PCI_RANGE_CS(&range[n]); 498 if (sc->sc_pci_bh[i] != 0) 499 panic("%s: duplicate range for space %d", __func__, i); 500 sc->sc_pci_bh[i] = OFW_PCI_RANGE_PHYS(&range[n]); 501 } 502 free(range, M_OFWPROP); 503 504 /* Register the softc, this is needed for paired Psychos. */ 505 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 506 507 /* 508 * Register a PCI bus error interrupt handler according to which 509 * half this is. Hummingbird/Sabre don't have a PCI bus B error 510 * interrupt but they are also only used for PCI bus A. 511 */ 512 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP : 513 PSR_PCIBERR_INT_MAP, FAST, psycho_pci_bus); 514 515 /* 516 * If we're a Hummingbird/Sabre or the first of a pair of Psycho's to 517 * arrive here, start up the IOMMU. 518 */ 519 if (osc == NULL) { 520 /* 521 * Establish handlers for interesting interrupts... 522 * 523 * XXX We need to remember these and remove this to support 524 * hotplug on the UPA/FHC bus. 525 * 526 * XXX Not all controllers have these, but installing them 527 * is better than trying to sort through this mess. 528 */ 529 psycho_set_intr(sc, 1, PSR_UE_INT_MAP, FAST, psycho_ue); 530 psycho_set_intr(sc, 2, PSR_CE_INT_MAP, 0, psycho_ce); 531 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, 532 PSYCHO_PWRFAIL_INT_FLAGS, psycho_powerfail); 533 /* Psycho-specific initialization */ 534 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 535 /* 536 * Hummingbirds/Sabres do not have the following two 537 * interrupts. 538 */ 539 540 /* 541 * The spare hardware interrupt is used for the 542 * over-temperature interrupt. 543 */ 544 psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP, FAST, 545 psycho_overtemp); 546#ifdef PSYCHO_MAP_WAKEUP 547 /* 548 * psycho_wakeup() doesn't do anything useful right 549 * now. 550 */ 551 psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP, 0, 552 psycho_wakeup); 553#endif /* PSYCHO_MAP_WAKEUP */ 554 555 /* Initialize the counter-timer. */ 556 sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, 557 PSR_TC0); 558 } 559 560 /* 561 * Set up IOMMU and PCI configuration if we're the first 562 * of a pair of Psycho's to arrive here. 563 * 564 * We should calculate a TSB size based on amount of RAM 565 * and number of bus controllers and number and type of 566 * child devices. 567 * 568 * For the moment, 32KB should be more than enough. 569 */ 570 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 571 M_NOWAIT); 572 if (sc->sc_is == NULL) 573 panic("%s: malloc iommu_state failed", __func__); 574 sc->sc_is->is_sb[0] = 0; 575 sc->sc_is->is_sb[1] = 0; 576 if (OF_getproplen(node, "no-streaming-cache") < 0) 577 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 578 psycho_iommu_init(sc, 3, dvmabase); 579 } else { 580 /* Just copy IOMMU state, config tag and address. */ 581 sc->sc_is = osc->sc_is; 582 if (OF_getproplen(node, "no-streaming-cache") < 0) 583 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 584 iommu_reset(sc->sc_is); 585 } 586 587 /* Allocate our tags. */ 588 sc->sc_pci_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 589 sc->sc_pci_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 590 sc->sc_pci_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 591 if (bus_dma_tag_create(nexus_get_dmatag(dev), 8, 1, 0, 0x3ffffffff, 592 NULL, NULL, 0x3ffffffff, 0xff, 0xffffffff, 0, NULL, NULL, 593 &sc->sc_pci_dmat) != 0) 594 panic("%s: bus_dma_tag_create failed", __func__); 595 /* Customize the tag. */ 596 sc->sc_pci_dmat->dt_cookie = sc->sc_is; 597 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 598 /* XXX: register as root DMA tag (kludge). */ 599 sparc64_root_dma_tag = sc->sc_pci_dmat; 600 601#ifdef PSYCHO_DEBUG 602 /* 603 * Enable all interrupts and clear all interrupt states. 604 * This aids the debugging of interrupt routing problems. 605 */ 606 for (map = PSR_PCIA0_INT_MAP, clr = PSR_PCIA0_INT_CLR, n = 0; 607 map <= PSR_PCIB3_INT_MAP; map += 8, clr += 32, n++) { 608 mr = PSYCHO_READ8(sc, map); 609 device_printf(dev, "intr map (pci) %d: %#lx\n", n, (u_long)mr); 610 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 611 for (i = 0; i < 4; i++) 612 PCICTL_WRITE8(sc, clr + i * 8, 0); 613 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 614 } 615 for (map = PSR_SCSI_INT_MAP, clr = PSR_SCSI_INT_CLR, n = 0; 616 map <= PSR_SERIAL_INT_MAP; map += 8, clr += 8, n++) { 617 mr = PSYCHO_READ8(sc, map); 618 device_printf(dev, "intr map (obio) %d: %#lx, clr: %#lx\n", n, 619 (u_long)mr, (u_long)clr); 620 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 621 PSYCHO_WRITE8(sc, clr, 0); 622 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 623 } 624#endif /* PSYCHO_DEBUG */ 625 626 /* 627 * Get the bus range from the firmware; it is used solely for obtaining 628 * the inital bus number, and cannot be trusted on all machines. 629 */ 630 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br)); 631 if (n == -1) 632 panic("%s: could not get bus-range", __func__); 633 if (n != sizeof(psycho_br)) 634 panic("%s: broken bus-range (%d)", __func__, n); 635 636 /* Clear PCI status error bits. */ 637 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, 638 PCIR_STATUS, PCIM_STATUS_PERR | PCIM_STATUS_RMABORT | 639 PCIM_STATUS_RTABORT | PCIM_STATUS_STABORT | 640 PCIM_STATUS_PERRREPORT, 2); 641 642 /* 643 * Set the latency timer register as this isn't always done by the 644 * firmware. 645 */ 646 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, 647 PCIR_LATTIMER, 64, 1); 648 649 sc->sc_pci_secbus = sc->sc_pci_subbus = ofw_pci_alloc_busno(node); 650 /* 651 * Program the bus range registers. 652 * NOTE: for the Psycho, the second write changes the bus number the 653 * Psycho itself uses for it's configuration space, so these 654 * writes must be kept in this order! 655 * The Hummingbird/Sabre always uses bus 0, but there only can be one 656 * Hummingbird/Sabre per machine. 657 */ 658 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SUBBUS, 659 sc->sc_pci_subbus, 1); 660 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SECBUS, 661 sc->sc_pci_secbus, 1); 662 663 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 664 /* 665 * On E250 the interrupt map entry for the EBus bridge is wrong, 666 * causing incorrect interrupts to be assigned to some devices on 667 * the EBus. Work around it by changing our copy of the interrupt 668 * map mask to perform a full comparison of the INO. That way 669 * the interrupt map entry for the EBus bridge won't match at all 670 * and the INOs specified in the "interrupts" properties of the 671 * EBus devices will be used directly instead. 672 */ 673 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 && 674 sc->sc_pci_iinfo.opi_imapmsk != NULL) 675 *(ofw_pci_intr_t *)(&sc->sc_pci_iinfo.opi_imapmsk[ 676 sc->sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK; 677 678 device_add_child(dev, "pci", sc->sc_pci_secbus); 679 return (bus_generic_attach(dev)); 680} 681 682static void 683psycho_set_intr(struct psycho_softc *sc, int index, bus_addr_t map, int iflags, 684 driver_filter_t handler) 685{ 686 int rid, vec, res; 687 uint64_t mr; 688 689 res = EINVAL; 690 rid = index; 691 mr = PSYCHO_READ8(sc, map); 692 vec = INTVEC(mr); 693 sc->sc_irq_res[index] = bus_alloc_resource(sc->sc_dev, SYS_RES_IRQ, 694 &rid, vec, vec, 1, RF_ACTIVE); 695 if (sc->sc_irq_res[index] != NULL) { 696 if (iflags & FAST) { 697 iflags &= ~FAST; 698 res = bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 699 INTR_TYPE_MISC | iflags, handler, NULL, sc, 700 &sc->sc_ihand[index]); 701 } else 702 res = bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 703 INTR_TYPE_MISC | iflags, NULL, 704 (driver_intr_t *)handler, sc, 705 &sc->sc_ihand[index]); 706 } 707 if (res) 708 panic("%s: failed to set up interrupt", __func__); 709 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 710} 711 712static int 713psycho_find_intrmap(struct psycho_softc *sc, int ino, bus_addr_t *intrmapptr, 714 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 715{ 716 bus_addr_t intrmap, intrclr; 717 uint64_t im; 718 u_long diag; 719 int found; 720 721 found = 0; 722 /* Hunt thru OBIO first. */ 723 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 724 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 725 intrmap <= PSR_SERIAL_INT_MAP; intrmap += 8, intrclr += 8, 726 diag >>= 2) { 727 im = PSYCHO_READ8(sc, intrmap); 728 if (INTINO(im) == ino) { 729 diag &= 2; 730 found = 1; 731 break; 732 } 733 } 734 735 if (!found) { 736 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 737 /* Now do PCI interrupts. */ 738 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 739 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 740 diag >>= 8) { 741 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 742 (intrmap == PSR_PCIA2_INT_MAP || 743 intrmap == PSR_PCIA3_INT_MAP)) 744 continue; 745 im = PSYCHO_READ8(sc, intrmap); 746 if (((im ^ ino) & 0x3c) == 0) { 747 intrclr += 8 * (ino & 3); 748 diag = (diag >> ((ino & 3) * 2)) & 2; 749 found = 1; 750 break; 751 } 752 } 753 } 754 if (intrmapptr != NULL) 755 *intrmapptr = intrmap; 756 if (intrclrptr != NULL) 757 *intrclrptr = intrclr; 758 if (intrdiagptr != NULL) 759 *intrdiagptr = diag; 760 return (found); 761} 762 763/* 764 * Interrupt handlers 765 */ 766static int 767psycho_ue(void *arg) 768{ 769 struct psycho_softc *sc = arg; 770 uint64_t afar, afsr; 771 772 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 773 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 774 /* 775 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 776 * the AFAR to be set to the physical address of the TTE entry that 777 * was invalid/write protected. Call into the iommu code to have 778 * them decoded to virtual I/O addresses. 779 */ 780 if ((afsr & UEAFSR_P_DTE) != 0) 781 iommu_decode_fault(sc->sc_is, afar); 782 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx", 783 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 784 return (FILTER_HANDLED); 785} 786 787static int 788psycho_ce(void *arg) 789{ 790 struct psycho_softc *sc = arg; 791 uint64_t afar, afsr; 792 793 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 794 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 795 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx " 796 "AFSR %#lx\n", (u_long)afar, (u_long)afsr); 797 /* Clear the error bits that we caught. */ 798 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr & CEAFSR_ERRMASK); 799 PSYCHO_WRITE8(sc, PSR_CE_INT_CLR, 0); 800 return (FILTER_HANDLED); 801} 802 803static int 804psycho_pci_bus(void *arg) 805{ 806 struct psycho_softc *sc = arg; 807 uint64_t afar, afsr; 808 809 afar = PCICTL_READ8(sc, PCR_AFA); 810 afsr = PCICTL_READ8(sc, PCR_AFS); 811 panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx", 812 device_get_name(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar, 813 (u_long)afsr); 814 return (FILTER_HANDLED); 815} 816 817static int 818psycho_powerfail(void *arg) 819{ 820 821#ifdef DEBUGGER_ON_POWERFAIL 822 struct psycho_softc *sc = arg; 823 824 kdb_enter("powerfail"); 825 PSYCHO_WRITE8(sc, PSR_POWER_INT_CLR, 0); 826#else 827 printf("Power Failure Detected: Shutting down NOW.\n"); 828 shutdown_nice(0); 829#endif 830 return (FILTER_HANDLED); 831} 832 833static int 834psycho_overtemp(void *arg) 835{ 836 837 printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n"); 838 shutdown_nice(RB_POWEROFF); 839 return (FILTER_HANDLED); 840} 841 842#ifdef PSYCHO_MAP_WAKEUP 843static int 844psycho_wakeup(void *arg) 845{ 846 struct psycho_softc *sc = arg; 847 848 PSYCHO_WRITE8(sc, PSR_PWRMGT_INT_CLR, 0); 849 /* Gee, we don't really have a framework to deal with this properly. */ 850 device_printf(sc->sc_dev, "power management wakeup\n"); 851 return (FILTER_HANDLED); 852} 853#endif /* PSYCHO_MAP_WAKEUP */ 854 855static void 856psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase) 857{ 858 char *name; 859 struct iommu_state *is = sc->sc_is; 860 861 /* Punch in our copies. */ 862 is->is_bustag = sc->sc_bustag; 863 is->is_bushandle = sc->sc_bushandle; 864 is->is_iommu = PSR_IOMMU; 865 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 866 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 867 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 868 is->is_dva = PSR_IOMMU_SVADIAG; 869 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 870 871 /* Give us a nice name... */ 872 name = malloc(32, M_DEVBUF, M_NOWAIT); 873 if (name == NULL) 874 panic("%s: could not malloc iommu name", __func__); 875 snprintf(name, 32, "%s dvma", device_get_nameunit(sc->sc_dev)); 876 877 iommu_init(name, is, tsbsize, dvmabase, 0); 878} 879 880static int 881psycho_maxslots(device_t dev) 882{ 883 884 /* XXX: is this correct? */ 885 return (PCI_SLOTMAX); 886} 887 888static uint32_t 889psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 890 int width) 891{ 892 struct psycho_softc *sc; 893 bus_space_handle_t bh; 894 u_long offset = 0; 895 uint8_t byte; 896 uint16_t shrt; 897 uint32_t wrd; 898 uint32_t r; 899 int i; 900 901 sc = device_get_softc(dev); 902 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 903 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 904 switch (width) { 905 case 1: 906 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 907 r = byte; 908 break; 909 case 2: 910 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 911 r = shrt; 912 break; 913 case 4: 914 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 915 r = wrd; 916 break; 917 default: 918 panic("%s: bad width", __func__); 919 } 920 921 if (i) { 922#ifdef PSYCHO_DEBUG 923 printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 924 __func__, bus, slot, func, reg); 925#endif 926 r = -1; 927 } 928 return (r); 929} 930 931static void 932psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 933 uint32_t val, int width) 934{ 935 struct psycho_softc *sc; 936 bus_space_handle_t bh; 937 u_long offset = 0; 938 939 sc = device_get_softc(dev); 940 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 941 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 942 switch (width) { 943 case 1: 944 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 945 break; 946 case 2: 947 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 948 break; 949 case 4: 950 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 951 break; 952 default: 953 panic("%s: bad width", __func__); 954 } 955} 956 957static int 958psycho_route_interrupt(device_t bridge, device_t dev, int pin) 959{ 960 struct psycho_softc *sc; 961 struct ofw_pci_register reg; 962 bus_addr_t intrmap; 963 ofw_pci_intr_t pintr, mintr; 964 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 965 966 sc = device_get_softc(bridge); 967 pintr = pin; 968 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, 969 sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) 970 return (mintr); 971 /* 972 * If this is outside of the range for an intpin, it's likely a full 973 * INO, and no mapping is required at all; this happens on the U30, 974 * where there's no interrupt map at the Psycho node. Fortunately, 975 * there seem to be no INOs in the intpin range on this boxen, so 976 * this easy heuristics will do. 977 */ 978 if (pin > 4) 979 return (pin); 980 /* 981 * Guess the INO; we always assume that this is a non-OBIO 982 * device, and that pin is a "real" intpin number. Determine 983 * the mapping register to be used by the slot number. 984 * We only need to do this on E450s, it seems; here, the slot numbers 985 * for bus A are one-based, while those for bus B seemingly have an 986 * offset of 2 (hence the factor of 3 below). 987 */ 988 intrmap = PSR_PCIA0_INT_MAP + 989 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half); 990 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1; 991 device_printf(bridge, "guessing interrupt %d for device %d.%d pin %d\n", 992 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin); 993 return (mintr); 994} 995 996static int 997psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 998{ 999 struct psycho_softc *sc; 1000 1001 sc = device_get_softc(dev); 1002 switch (which) { 1003 case PCIB_IVAR_BUS: 1004 *result = sc->sc_pci_secbus; 1005 return (0); 1006 } 1007 return (ENOENT); 1008} 1009 1010/* Write to the correct clr register, and call the actual handler. */ 1011static int 1012psycho_intr_stub(void *arg) 1013{ 1014 struct psycho_clr *pc = arg; 1015 1016 if (pc->pci_ppb != NULL) { 1017 (void)PCIB_READ_CONFIG(pc->pci_ppb, pc->pci_bus, pc->pci_slot, 1018 pc->pci_func, PCIR_VENDOR, 2); 1019 (void)PSYCHO_READ8(pc->pci_sc, PSR_DMA_WRITE_SYNC); 1020 } 1021 pc->pci_handler(pc->pci_arg); 1022 PSYCHO_WRITE8(pc->pci_sc, pc->pci_clr, 0); 1023 return (FILTER_HANDLED); 1024} 1025 1026static int 1027psycho_setup_intr(device_t dev, device_t child, struct resource *ires, 1028 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1029 void **cookiep) 1030{ 1031 struct { 1032 int apb:1; 1033 int ppb:1; 1034 } found; 1035 devclass_t pci_devclass; 1036 device_t cdev, pdev, pcidev; 1037 struct psycho_softc *sc; 1038 struct psycho_clr *pc; 1039 bus_addr_t intrmapptr, intrclrptr; 1040 long vec; 1041 uint64_t mr; 1042 int error, ino; 1043 1044 if (filt != NULL && intr != NULL) 1045 return (EINVAL); 1046 1047 sc = device_get_softc(dev); 1048 pc = malloc(sizeof(*pc), M_DEVBUF, M_NOWAIT | M_ZERO); 1049 if (pc == NULL) 1050 return (ENOMEM); 1051 1052 /* 1053 * Hunt through all the interrupt mapping regs to look for our 1054 * interrupt vector. 1055 * 1056 * XXX We only compare INOs rather than IGNs since the firmware may 1057 * not provide the IGN and the IGN is constant for all devices on that 1058 * PCI controller. This could cause problems for the FFB/external 1059 * interrupt which has a full vector that can be set arbitrarily. 1060 */ 1061 vec = rman_get_start(ires); 1062 ino = INTINO(vec); 1063 if (!psycho_find_intrmap(sc, ino, &intrmapptr, &intrclrptr, NULL)) { 1064 device_printf(dev, "cannot find interrupt vector 0x%lx\n", vec); 1065 free(pc, M_DEVBUF); 1066 return (EINVAL); 1067 } 1068 1069#ifdef PSYCHO_DEBUG 1070 device_printf(dev, "%s: INO %d, map %#lx, clr %#lx\n", __func__, ino, 1071 (u_long)intrmapptr, (u_long)intrclrptr); 1072#endif 1073 1074 pc->pci_sc = sc; 1075 pc->pci_arg = arg; 1076 pc->pci_handler = (filt != NULL) ? filt : (driver_filter_t *)intr; 1077 pc->pci_clr = intrclrptr; 1078 1079 /* 1080 * The Sabre-APB-combination has a bug where it does not drain 1081 * DMA write data for devices behind additional PCI-PCI bridges 1082 * underneath the APB PCI-PCI bridge. The workaround is to do 1083 * a read on the farest PCI-PCI bridge followed by a read of the 1084 * PCI DMA write sync register of the Sabre. 1085 * XXX installing the workaround for an affected device and the 1086 * actual workaround in psycho_intr_stub() should be moved to 1087 * psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() 1088 * methods, respectively, once we make use of BUS_GET_DMA_TAG(), 1089 * so the workaround isn't only applied for interrupt handlers 1090 * but also for polling(4) callbacks. 1091 */ 1092 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 1093 pcidev = NULL; 1094 found.apb = found.ppb = 0; 1095 pci_devclass = devclass_find("pci"); 1096 for (cdev = child; cdev != dev; cdev = pdev) { 1097 pdev = device_get_parent(cdev); 1098 if (pcidev == NULL) { 1099 if (device_get_devclass(pdev) != pci_devclass) 1100 continue; 1101 pcidev = cdev; 1102 continue; 1103 } 1104 /* 1105 * NB: APB would also match as PCI-PCI bridges. 1106 */ 1107 if (pci_get_vendor(cdev) == 0x108e && 1108 pci_get_device(cdev) == 0x5000) { 1109 found.apb = 1; 1110 break; 1111 } 1112 if (pci_get_class(cdev) == PCIC_BRIDGE && 1113 pci_get_subclass(cdev) == PCIS_BRIDGE_PCI) 1114 found.ppb = 1; 1115 } 1116 if (found.apb && found.ppb && pcidev != NULL) { 1117 pc->pci_ppb = 1118 device_get_parent(device_get_parent(pcidev)); 1119 pc->pci_bus = pci_get_bus(pcidev); 1120 pc->pci_slot = pci_get_slot(pcidev); 1121 pc->pci_func = pci_get_function(pcidev); 1122 if (bootverbose) 1123 device_printf(dev, "installed DMA sync " 1124 "workaround for device %d.%d on bus %d\n", 1125 pc->pci_slot, pc->pci_func, pc->pci_bus); 1126 } 1127 } 1128 1129 /* Disable the interrupt while we fiddle with it. */ 1130 mr = PSYCHO_READ8(sc, intrmapptr); 1131 PSYCHO_WRITE8(sc, intrmapptr, mr & ~INTMAP_V); 1132 if (filt != NULL) 1133 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 1134 psycho_intr_stub, NULL, pc, cookiep); 1135 else 1136 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 1137 NULL, (driver_intr_t *)psycho_intr_stub, pc, cookiep); 1138 if (error != 0) { 1139 free(pc, M_DEVBUF); 1140 return (error); 1141 } 1142 pc->pci_cookie = *cookiep; 1143 *cookiep = pc; 1144 1145 /* 1146 * Clear the interrupt, it might have been triggered before it was 1147 * set up. 1148 */ 1149 PSYCHO_WRITE8(sc, intrclrptr, 0); 1150 /* 1151 * Enable the interrupt and program the target module now we have the 1152 * handler installed. 1153 */ 1154 PSYCHO_WRITE8(sc, intrmapptr, INTMAP_ENABLE(mr, PCPU_GET(mid))); 1155 return (error); 1156} 1157 1158static int 1159psycho_teardown_intr(device_t dev, device_t child, struct resource *vec, 1160 void *cookie) 1161{ 1162 struct psycho_clr *pc = cookie; 1163 int error; 1164 1165 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 1166 pc->pci_cookie); 1167 /* 1168 * Don't disable the interrupt for now, so that stray interupts get 1169 * detected... 1170 */ 1171 if (error != 0) 1172 free(pc, M_DEVBUF); 1173 return (error); 1174} 1175 1176static struct resource * 1177psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1178 u_long start, u_long end, u_long count, u_int flags) 1179{ 1180 struct psycho_softc *sc; 1181 struct resource *rv; 1182 struct rman *rm; 1183 bus_space_tag_t bt; 1184 bus_space_handle_t bh; 1185 int needactivate = flags & RF_ACTIVE; 1186 1187 flags &= ~RF_ACTIVE; 1188 1189 sc = device_get_softc(bus); 1190 if (type == SYS_RES_IRQ) { 1191 /* 1192 * XXX: Don't accept blank ranges for now, only single 1193 * interrupts. The other case should not happen with the 1194 * MI PCI code... 1195 * XXX: This may return a resource that is out of the 1196 * range that was specified. Is this correct...? 1197 */ 1198 if (start != end) 1199 panic("%s: XXX: interrupt range", __func__); 1200 start = end |= sc->sc_ign; 1201 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, 1202 rid, start, end, count, flags)); 1203 } 1204 switch (type) { 1205 case SYS_RES_MEMORY: 1206 rm = &sc->sc_pci_mem_rman; 1207 bt = sc->sc_pci_memt; 1208 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1209 break; 1210 case SYS_RES_IOPORT: 1211 rm = &sc->sc_pci_io_rman; 1212 bt = sc->sc_pci_iot; 1213 bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1214 break; 1215 default: 1216 return (NULL); 1217 } 1218 1219 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1220 if (rv == NULL) 1221 return (NULL); 1222 rman_set_rid(rv, *rid); 1223 bh += rman_get_start(rv); 1224 rman_set_bustag(rv, bt); 1225 rman_set_bushandle(rv, bh); 1226 1227 if (needactivate) { 1228 if (bus_activate_resource(child, type, *rid, rv)) { 1229 rman_release_resource(rv); 1230 return (NULL); 1231 } 1232 } 1233 1234 return (rv); 1235} 1236 1237static int 1238psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1239 struct resource *r) 1240{ 1241 void *p; 1242 int error; 1243 1244 if (type == SYS_RES_IRQ) 1245 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1246 type, rid, r)); 1247 if (type == SYS_RES_MEMORY) { 1248 /* 1249 * Need to memory-map the device space, as some drivers depend 1250 * on the virtual address being set and useable. 1251 */ 1252 error = sparc64_bus_mem_map(rman_get_bustag(r), 1253 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1254 if (error != 0) 1255 return (error); 1256 rman_set_virtual(r, p); 1257 } 1258 return (rman_activate_resource(r)); 1259} 1260 1261static int 1262psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1263 struct resource *r) 1264{ 1265 1266 if (type == SYS_RES_IRQ) 1267 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1268 type, rid, r)); 1269 if (type == SYS_RES_MEMORY) { 1270 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1271 rman_set_virtual(r, NULL); 1272 } 1273 return (rman_deactivate_resource(r)); 1274} 1275 1276static int 1277psycho_release_resource(device_t bus, device_t child, int type, int rid, 1278 struct resource *r) 1279{ 1280 int error; 1281 1282 if (type == SYS_RES_IRQ) 1283 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1284 type, rid, r)); 1285 if (rman_get_flags(r) & RF_ACTIVE) { 1286 error = bus_deactivate_resource(child, type, rid, r); 1287 if (error) 1288 return error; 1289 } 1290 return (rman_release_resource(r)); 1291} 1292 1293static int 1294psycho_intr_pending(device_t dev, ofw_pci_intr_t intr) 1295{ 1296 struct psycho_softc *sc; 1297 u_long diag; 1298 1299 sc = device_get_softc(dev); 1300 if (!psycho_find_intrmap(sc, intr, NULL, NULL, &diag)) { 1301 device_printf(dev, "%s: mapping not found for %d\n", __func__, 1302 intr); 1303 return (0); 1304 } 1305 return (diag != 0); 1306} 1307 1308static phandle_t 1309psycho_get_node(device_t bus, device_t dev) 1310{ 1311 struct psycho_softc *sc; 1312 1313 sc = device_get_softc(bus); 1314 /* We only have one child, the PCI bus, which needs our own node. */ 1315 return (sc->sc_node); 1316} 1317 1318static void 1319psycho_adjust_busrange(device_t dev, u_int subbus) 1320{ 1321 struct psycho_softc *sc; 1322 1323 sc = device_get_softc(dev); 1324 /* If necessary, adjust the subordinate bus number register. */ 1325 if (subbus > sc->sc_pci_subbus) { 1326#ifdef PSYCHO_DEBUG 1327 device_printf(dev, 1328 "adjusting secondary bus number from %d to %d\n", 1329 sc->sc_pci_subbus, subbus); 1330#endif 1331 sc->sc_pci_subbus = subbus; 1332 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, 1333 PCSR_SUBBUS, subbus, 1); 1334 } 1335} 1336 1337static bus_space_tag_t 1338psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1339{ 1340 bus_space_tag_t bt; 1341 1342 bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF, M_NOWAIT | M_ZERO); 1343 if (bt == NULL) 1344 panic("%s: out of memory", __func__); 1345 1346 bt->bst_cookie = sc; 1347 bt->bst_parent = sc->sc_bustag; 1348 bt->bst_type = type; 1349 return (bt); 1350} 1351