psycho.c revision 153061
1/*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: head/sys/sparc64/pci/psycho.c 153061 2005-12-03 19:52:20Z marius $"); 34 35/* 36 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+' 37 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges. 38 */ 39 40#include "opt_ofw_pci.h" 41#include "opt_psycho.h" 42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/bus.h> 46#include <sys/kdb.h> 47#include <sys/kernel.h> 48#include <sys/module.h> 49#include <sys/malloc.h> 50#include <sys/pcpu.h> 51#include <sys/reboot.h> 52 53#include <dev/ofw/ofw_bus.h> 54#include <dev/ofw/ofw_pci.h> 55#include <dev/ofw/openfirm.h> 56 57#include <machine/bus.h> 58#include <machine/bus_private.h> 59#include <machine/iommureg.h> 60#include <machine/bus_common.h> 61#include <machine/nexusvar.h> 62#include <machine/ofw_bus.h> 63#include <machine/ofw_upa.h> 64#include <machine/resource.h> 65#include <machine/ver.h> 66 67#include <sys/rman.h> 68 69#include <machine/iommuvar.h> 70 71#include <dev/pci/pcivar.h> 72 73#include <sparc64/pci/ofw_pci.h> 74#include <sparc64/pci/psychoreg.h> 75#include <sparc64/pci/psychovar.h> 76 77#include "pcib_if.h" 78 79static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *, 80 const char *); 81static const struct psycho_desc *psycho_get_desc(phandle_t, const char *); 82static void psycho_set_intr(struct psycho_softc *, int, device_t, bus_addr_t, 83 int, driver_intr_t); 84static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *, 85 bus_addr_t *, u_long *); 86static void psycho_intr_stub(void *); 87static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 88 89/* Interrupt handlers */ 90static void psycho_ue(void *); 91static void psycho_ce(void *); 92static void psycho_pci_bus(void *); 93static void psycho_powerfail(void *); 94static void psycho_overtemp(void *); 95#ifdef PSYCHO_MAP_WAKEUP 96static void psycho_wakeup(void *); 97#endif 98 99/* IOMMU support */ 100static void psycho_iommu_init(struct psycho_softc *, int, uint32_t); 101 102/* 103 * Methods 104 */ 105static device_probe_t psycho_probe; 106static device_attach_t psycho_attach; 107static bus_read_ivar_t psycho_read_ivar; 108static bus_setup_intr_t psycho_setup_intr; 109static bus_teardown_intr_t psycho_teardown_intr; 110static bus_alloc_resource_t psycho_alloc_resource; 111static bus_activate_resource_t psycho_activate_resource; 112static bus_deactivate_resource_t psycho_deactivate_resource; 113static bus_release_resource_t psycho_release_resource; 114static pcib_maxslots_t psycho_maxslots; 115static pcib_read_config_t psycho_read_config; 116static pcib_write_config_t psycho_write_config; 117static pcib_route_interrupt_t psycho_route_interrupt; 118static ofw_pci_intr_pending_t psycho_intr_pending; 119static ofw_pci_get_bus_handle_t psycho_get_bus_handle; 120static ofw_bus_get_node_t psycho_get_node; 121static ofw_pci_adjust_busrange_t psycho_adjust_busrange; 122 123static device_method_t psycho_methods[] = { 124 /* Device interface */ 125 DEVMETHOD(device_probe, psycho_probe), 126 DEVMETHOD(device_attach, psycho_attach), 127 128 /* Bus interface */ 129 DEVMETHOD(bus_print_child, bus_generic_print_child), 130 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 131 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 132 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 133 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 134 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 135 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 136 DEVMETHOD(bus_release_resource, psycho_release_resource), 137 138 /* pcib interface */ 139 DEVMETHOD(pcib_maxslots, psycho_maxslots), 140 DEVMETHOD(pcib_read_config, psycho_read_config), 141 DEVMETHOD(pcib_write_config, psycho_write_config), 142 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 143 144 /* ofw_bus interface */ 145 DEVMETHOD(ofw_bus_get_node, psycho_get_node), 146 147 /* ofw_pci interface */ 148 DEVMETHOD(ofw_pci_intr_pending, psycho_intr_pending), 149 DEVMETHOD(ofw_pci_get_bus_handle, psycho_get_bus_handle), 150 DEVMETHOD(ofw_pci_adjust_busrange, psycho_adjust_busrange), 151 152 { 0, 0 } 153}; 154 155static driver_t psycho_driver = { 156 "pcib", 157 psycho_methods, 158 sizeof(struct psycho_softc), 159}; 160 161static devclass_t psycho_devclass; 162 163DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 164 165SLIST_HEAD(, psycho_softc) psycho_softcs = 166 SLIST_HEAD_INITIALIZER(psycho_softcs); 167 168struct psycho_clr { 169 struct psycho_softc *pci_sc; 170 bus_addr_t pci_clr; /* clear register */ 171 driver_intr_t *pci_handler; /* handler to call */ 172 void *pci_arg; /* argument for the handler */ 173 void *pci_cookie; /* parent bus int. cookie */ 174}; 175 176#define PSYCHO_READ8(sc, off) \ 177 bus_space_read_8((sc)->sc_bustag, (sc)->sc_bushandle, (off)) 178#define PSYCHO_WRITE8(sc, off, v) \ 179 bus_space_write_8((sc)->sc_bustag, (sc)->sc_bushandle, (off), (v)) 180#define PCICTL_READ8(sc, off) \ 181 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 182#define PCICTL_WRITE8(sc, off, v) \ 183 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 184 185/* 186 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 187 * single PCI bus and does not have a streaming buffer. It often has an APB 188 * (advanced PCI bridge) connected to it, which was designed specifically for 189 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 190 * appears as two "Simba"'s underneath the Sabre. 191 * 192 * "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's 193 * basically the same as Sabre but without an APB underneath it. 194 * 195 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA bus 196 * and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while 197 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 198 * will usually find a "Psycho+" since I don't think the original "Psycho" 199 * ever shipped, and if it did it would be in the U30. 200 * 201 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are 202 * both part of the same IC, they only have a single register space. As such, 203 * they need to be configured together, even though the autoconfiguration will 204 * attach them separately. 205 * 206 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often 207 * as pci1 and pci2, although they have been implemented with other PCI bus 208 * numbers on some machines. 209 * 210 * On UltraII machines, there can be any number of "Psycho+" ICs, each 211 * providing two PCI buses. 212 */ 213#ifdef DEBUGGER_ON_POWERFAIL 214#define PSYCHO_PWRFAIL_INT_FLAGS INTR_FAST 215#else 216#define PSYCHO_PWRFAIL_INT_FLAGS 0 217#endif 218 219#define OFW_PCI_TYPE "pci" 220 221struct psycho_desc { 222 const char *pd_string; 223 int pd_mode; 224 const char *pd_name; 225}; 226 227static const struct psycho_desc psycho_compats[] = { 228 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 229 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" }, 230 { "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" }, 231 { NULL, 0, NULL } 232}; 233 234static const struct psycho_desc psycho_models[] = { 235 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 236 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 237 { NULL, 0, NULL } 238}; 239 240static const struct psycho_desc * 241psycho_find_desc(const struct psycho_desc *table, const char *string) 242{ 243 const struct psycho_desc *desc; 244 245 for (desc = table; desc->pd_string != NULL; desc++) { 246 if (strcmp(desc->pd_string, string) == 0) 247 return (desc); 248 } 249 return (NULL); 250} 251 252static const struct psycho_desc * 253psycho_get_desc(phandle_t node, const char *model) 254{ 255 const struct psycho_desc *rv; 256 char compat[32]; 257 258 rv = NULL; 259 if (model != NULL) 260 rv = psycho_find_desc(psycho_models, model); 261 if (rv == NULL && 262 OF_getprop(node, "compatible", compat, sizeof(compat)) != -1) 263 rv = psycho_find_desc(psycho_compats, compat); 264 return (rv); 265} 266 267static int 268psycho_probe(device_t dev) 269{ 270 const char *dtype; 271 272 dtype = nexus_get_device_type(dev); 273 if (nexus_get_reg(dev) != NULL && dtype != NULL && 274 strcmp(dtype, OFW_PCI_TYPE) == 0 && 275 psycho_get_desc(nexus_get_node(dev), 276 nexus_get_model(dev)) != NULL) { 277 device_set_desc(dev, "U2P UPA-PCI bridge"); 278 return (0); 279 } 280 281 return (ENXIO); 282} 283 284static int 285psycho_attach(device_t dev) 286{ 287 struct psycho_softc *sc; 288 struct psycho_softc *osc = NULL; 289 struct psycho_softc *asc; 290 struct ofw_pci_ranges *range; 291 struct upa_regs *reg; 292 const struct psycho_desc *desc; 293 phandle_t node; 294 uint64_t csr; 295 uint32_t dvmabase; 296 u_long mlen; 297 int psycho_br[2]; 298 int n, i, nrange, nreg, rid; 299#ifdef PSYCHO_DEBUG 300 bus_addr_t map, clr; 301 uint64_t mr; 302#endif 303 304 node = nexus_get_node(dev); 305 sc = device_get_softc(dev); 306 desc = psycho_get_desc(node, nexus_get_model(dev)); 307 308 sc->sc_node = node; 309 sc->sc_dev = dev; 310 sc->sc_mode = desc->pd_mode; 311 312 /* 313 * The Psycho gets three register banks: 314 * (0) per-PBM configuration and status registers 315 * (1) per-PBM PCI configuration space, containing only the 316 * PBM 256-byte PCI header 317 * (2) the shared Psycho configuration registers 318 */ 319 reg = nexus_get_reg(dev); 320 nreg = nexus_get_nreg(dev); 321 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 322 if (nreg <= 2) 323 panic("%s: %d not enough registers", __func__, nreg); 324 sc->sc_basepaddr = (vm_paddr_t)UPA_REG_PHYS(®[2]); 325 mlen = UPA_REG_SIZE(®[2]); 326 sc->sc_pcictl = UPA_REG_PHYS(®[0]) - sc->sc_basepaddr; 327 switch (sc->sc_pcictl) { 328 case PSR_PCICTL0: 329 sc->sc_half = 0; 330 break; 331 case PSR_PCICTL1: 332 sc->sc_half = 1; 333 break; 334 default: 335 panic("%s: bogus PCI control register location", 336 __func__); 337 } 338 } else { 339 if (nreg <= 0) 340 panic("%s: %d not enough registers", __func__, nreg); 341 sc->sc_basepaddr = (vm_paddr_t)UPA_REG_PHYS(®[0]); 342 mlen = UPA_REG_SIZE(reg); 343 sc->sc_pcictl = PSR_PCICTL0; 344 sc->sc_half = 0; 345 } 346 347 /* 348 * Match other Psycho's that are already configured against 349 * the base physical address. This will be the same for a 350 * pair of devices that share register space. 351 */ 352 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 353 if (asc->sc_basepaddr == sc->sc_basepaddr) { 354 /* Found partner. */ 355 osc = asc; 356 break; 357 } 358 } 359 360 if (osc == NULL) { 361 rid = 0; 362 sc->sc_mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 363 sc->sc_basepaddr, sc->sc_basepaddr + mlen - 1, mlen, 364 RF_ACTIVE); 365 if (sc->sc_mem_res == NULL || 366 rman_get_start(sc->sc_mem_res) != sc->sc_basepaddr) 367 panic("%s: could not allocate device memory", __func__); 368 sc->sc_bustag = rman_get_bustag(sc->sc_mem_res); 369 sc->sc_bushandle = rman_get_bushandle(sc->sc_mem_res); 370 } else { 371 /* 372 * There's another Psycho using the same register space. 373 * Copy the relevant stuff. 374 */ 375 sc->sc_mem_res = NULL; 376 sc->sc_bustag = osc->sc_bustag; 377 sc->sc_bushandle = osc->sc_bushandle; 378 } 379 csr = PSYCHO_READ8(sc, PSR_CS); 380 sc->sc_ign = 0x7c0; /* Hummingbird/Sabre IGN is always 0x1f. */ 381 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 382 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << INTMAP_IGN_SHIFT; 383 384 device_printf(dev, "%s, impl %d, version %d, ign %#x, bus %c\n", 385 desc->pd_name, (int)PSYCHO_GCSR_IMPL(csr), 386 (int)PSYCHO_GCSR_VERS(csr), sc->sc_ign, 'A' + sc->sc_half); 387 388 /* Setup the PCI control register. */ 389 csr = PCICTL_READ8(sc, PCR_CS); 390 csr |= PCICTL_MRLM | PCICTL_ARB_PARK | PCICTL_ERRINTEN | PCICTL_4ENABLE; 391 csr &= ~(PCICTL_SERR | PCICTL_CPU_PRIO | PCICTL_ARB_PRIO | 392 PCICTL_RTRYWAIT); 393 PCICTL_WRITE8(sc, PCR_CS, csr); 394 395 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 396 /* Use the PROM preset for now. */ 397 csr = PCICTL_READ8(sc, PCR_TAS); 398 if (csr == 0) 399 panic("%s: Hummingbird/Sabre TAS not initialized.", 400 __func__); 401 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT; 402 } else 403 dvmabase = -1; 404 405 /* Initialize memory and I/O rmans. */ 406 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 407 sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports"; 408 if (rman_init(&sc->sc_pci_io_rman) != 0 || 409 rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0) 410 panic("%s: failed to set up I/O rman", __func__); 411 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 412 sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory"; 413 if (rman_init(&sc->sc_pci_mem_rman) != 0 || 414 rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 415 panic("%s: failed to set up memory rman", __func__); 416 417 nrange = OF_getprop_alloc(node, "ranges", sizeof(*range), 418 (void **)&range); 419 /* 420 * Make sure that the expected ranges are present. The OFW_PCI_CS_MEM64 421 * one is not currently used though. 422 */ 423 if (nrange != PSYCHO_NRANGE) 424 panic("%s: unsupported number of ranges", __func__); 425 /* 426 * Find the addresses of the various bus spaces. 427 * There should not be multiple ones of one kind. 428 * The physical start addresses of the ranges are the configuration, 429 * memory and I/O handles. 430 */ 431 for (n = 0; n < PSYCHO_NRANGE; n++) { 432 i = OFW_PCI_RANGE_CS(&range[n]); 433 if (sc->sc_pci_bh[i] != 0) 434 panic("%s: duplicate range for space %d", __func__, i); 435 sc->sc_pci_bh[i] = OFW_PCI_RANGE_PHYS(&range[n]); 436 } 437 free(range, M_OFWPROP); 438 439 /* Register the softc, this is needed for paired Psychos. */ 440 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 441 442 /* 443 * Register a PCI bus error interrupt handler according to which 444 * half this is. Hummingbird/Sabre don't have a PCI bus B error 445 * interrupt but they are also only used for PCI bus A. 446 */ 447 psycho_set_intr(sc, 0, dev, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP : 448 PSR_PCIBERR_INT_MAP, INTR_FAST, psycho_pci_bus); 449 450 /* 451 * If we're a Hummingbird/Sabre or the first of a pair of Psycho's to 452 * arrive here, start up the IOMMU. 453 */ 454 if (osc == NULL) { 455 /* 456 * Establish handlers for interesting interrupts... 457 * 458 * XXX We need to remember these and remove this to support 459 * hotplug on the UPA/FHC bus. 460 * 461 * XXX Not all controllers have these, but installing them 462 * is better than trying to sort through this mess. 463 */ 464 psycho_set_intr(sc, 1, dev, PSR_UE_INT_MAP, INTR_FAST, 465 psycho_ue); 466 psycho_set_intr(sc, 2, dev, PSR_CE_INT_MAP, 0, psycho_ce); 467 psycho_set_intr(sc, 3, dev, PSR_POWER_INT_MAP, 468 PSYCHO_PWRFAIL_INT_FLAGS, psycho_powerfail); 469 /* Psycho-specific initialization */ 470 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 471 /* 472 * Hummingbirds/Sabres do not have the following two 473 * interrupts. 474 */ 475 476 /* 477 * The spare hardware interrupt is used for the 478 * over-temperature interrupt. 479 */ 480 psycho_set_intr(sc, 4, dev, PSR_SPARE_INT_MAP, 481 INTR_FAST, psycho_overtemp); 482#ifdef PSYCHO_MAP_WAKEUP 483 /* 484 * psycho_wakeup() doesn't do anything useful right 485 * now. 486 */ 487 psycho_set_intr(sc, 5, dev, PSR_PWRMGT_INT_MAP, 0, 488 psycho_wakeup); 489#endif /* PSYCHO_MAP_WAKEUP */ 490 491 /* Initialize the counter-timer. */ 492 sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, 493 PSR_TC0); 494 } 495 496 /* 497 * Setup IOMMU and PCI configuration if we're the first 498 * of a pair of Psycho's to arrive here. 499 * 500 * We should calculate a TSB size based on amount of RAM 501 * and number of bus controllers and number and type of 502 * child devices. 503 * 504 * For the moment, 32KB should be more than enough. 505 */ 506 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 507 M_NOWAIT); 508 if (sc->sc_is == NULL) 509 panic("%s: malloc iommu_state failed", __func__); 510 sc->sc_is->is_sb[0] = 0; 511 sc->sc_is->is_sb[1] = 0; 512 if (OF_getproplen(node, "no-streaming-cache") < 0) 513 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 514 psycho_iommu_init(sc, 3, dvmabase); 515 } else { 516 /* Just copy IOMMU state, config tag and address. */ 517 sc->sc_is = osc->sc_is; 518 if (OF_getproplen(node, "no-streaming-cache") < 0) 519 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 520 iommu_reset(sc->sc_is); 521 } 522 523 /* Allocate our tags. */ 524 sc->sc_pci_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 525 sc->sc_pci_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 526 sc->sc_pci_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 527 if (bus_dma_tag_create(nexus_get_dmatag(dev), 8, 1, 0, 0x3ffffffff, 528 NULL, NULL, 0x3ffffffff, 0xff, 0xffffffff, 0, NULL, NULL, 529 &sc->sc_pci_dmat) != 0) 530 panic("%s: bus_dma_tag_create failed", __func__); 531 /* Customize the tag. */ 532 sc->sc_pci_dmat->dt_cookie = sc->sc_is; 533 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 534 /* XXX: register as root DMA tag (kludge). */ 535 sparc64_root_dma_tag = sc->sc_pci_dmat; 536 537#ifdef PSYCHO_DEBUG 538 /* 539 * Enable all interrupts and clear all interrupt states. 540 * This aids the debugging of interrupt routing problems. 541 */ 542 for (map = PSR_PCIA0_INT_MAP, clr = PSR_PCIA0_INT_CLR, n = 0; 543 map <= PSR_PCIB3_INT_MAP; map += 8, clr += 32, n++) { 544 mr = PSYCHO_READ8(sc, map); 545 device_printf(dev, "intr map (pci) %d: %#lx\n", n, (u_long)mr); 546 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 547 for (i = 0; i < 4; i++) 548 PCICTL_WRITE8(sc, clr + i * 8, 0); 549 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 550 } 551 for (map = PSR_SCSI_INT_MAP, clr = PSR_SCSI_INT_CLR, n = 0; 552 map <= PSR_SERIAL_INT_MAP; map += 8, clr += 8, n++) { 553 mr = PSYCHO_READ8(sc, map); 554 device_printf(dev, "intr map (obio) %d: %#lx, clr: %#lx\n", n, 555 (u_long)mr, (u_long)clr); 556 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 557 PSYCHO_WRITE8(sc, clr, 0); 558 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 559 } 560#endif /* PSYCHO_DEBUG */ 561 562 /* 563 * Get the bus range from the firmware; it is used solely for obtaining 564 * the inital bus number, and cannot be trusted on all machines. 565 */ 566 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br)); 567 if (n == -1) 568 panic("%s: could not get Psycho bus-range", __func__); 569 if (n != sizeof(psycho_br)) 570 panic("%s: broken Psycho bus-range (%d)", __func__, n); 571 572 sc->sc_pci_secbus = sc->sc_pci_subbus = ofw_pci_alloc_busno(node); 573 /* 574 * Program the bus range registers. 575 * NOTE: for the Psycho, the second write changes the bus number the 576 * Psycho itself uses for it's configuration space, so these 577 * writes must be kept in this order! 578 * The Hummingbird/Sabre always uses bus 0, but there only can be one 579 * Hummingbird/Sabre per machine. 580 */ 581 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SUBBUS, 582 sc->sc_pci_subbus, 1); 583 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SECBUS, 584 sc->sc_pci_secbus, 1); 585 586 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 587 /* 588 * On E250 the interrupt map entry for the EBus bridge is wrong, 589 * causing incorrect interrupts to be assigned to some devices on 590 * the EBus. Work around it by changing our copy of the interrupt 591 * map mask to do perform a full comparison of the INO. That way 592 * the interrupt map entry for the EBus bridge won't match at all 593 * and the INOs specified in the "interrupts" properties of the 594 * EBus devices will be used directly instead. 595 */ 596 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 && 597 sc->sc_pci_iinfo.opi_imapmsk != NULL) 598 *(ofw_pci_intr_t *)(&sc->sc_pci_iinfo.opi_imapmsk[ 599 sc->sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK; 600 601 device_add_child(dev, "pci", sc->sc_pci_secbus); 602 return (bus_generic_attach(dev)); 603} 604 605static void 606psycho_set_intr(struct psycho_softc *sc, int index, device_t dev, 607 bus_addr_t map, int iflags, driver_intr_t handler) 608{ 609 int rid, vec; 610 uint64_t mr; 611 612 rid = index; 613 mr = PSYCHO_READ8(sc, map); 614 vec = INTVEC(mr); 615 sc->sc_irq_res[index] = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 616 vec, vec, 1, RF_ACTIVE); 617 if (sc->sc_irq_res[index] == NULL) 618 panic("%s: failed to get interrupt", __func__); 619 bus_setup_intr(dev, sc->sc_irq_res[index], INTR_TYPE_MISC | iflags, 620 handler, sc, &sc->sc_ihand[index]); 621 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 622} 623 624static int 625psycho_find_intrmap(struct psycho_softc *sc, int ino, bus_addr_t *intrmapptr, 626 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 627{ 628 bus_addr_t intrmap, intrclr; 629 uint64_t im; 630 u_long diag; 631 int found; 632 633 found = 0; 634 /* Hunt thru OBIO first. */ 635 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 636 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 637 intrmap <= PSR_SERIAL_INT_MAP; intrmap += 8, intrclr += 8, 638 diag >>= 2) { 639 im = PSYCHO_READ8(sc, intrmap); 640 if (INTINO(im) == ino) { 641 diag &= 2; 642 found = 1; 643 break; 644 } 645 } 646 647 if (!found) { 648 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 649 /* Now do PCI interrupts. */ 650 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 651 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 652 diag >>= 8) { 653 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 654 (intrmap == PSR_PCIA2_INT_MAP || 655 intrmap == PSR_PCIA3_INT_MAP)) 656 continue; 657 im = PSYCHO_READ8(sc, intrmap); 658 if (((im ^ ino) & 0x3c) == 0) { 659 intrclr += 8 * (ino & 3); 660 diag = (diag >> ((ino & 3) * 2)) & 2; 661 found = 1; 662 break; 663 } 664 } 665 } 666 if (intrmapptr != NULL) 667 *intrmapptr = intrmap; 668 if (intrclrptr != NULL) 669 *intrclrptr = intrclr; 670 if (intrdiagptr != NULL) 671 *intrdiagptr = diag; 672 return (found); 673} 674 675/* 676 * Interrupt handlers 677 */ 678static void 679psycho_ue(void *arg) 680{ 681 struct psycho_softc *sc = arg; 682 uint64_t afar, afsr; 683 684 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 685 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 686 /* 687 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 688 * the AFAR to be set to the physical address of the TTE entry that 689 * was invalid/write protected. Call into the iommu code to have 690 * them decoded to virtual IO addresses. 691 */ 692 if ((afsr & UEAFSR_P_DTE) != 0) 693 iommu_decode_fault(sc->sc_is, afar); 694 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx", 695 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 696} 697 698static void 699psycho_ce(void *arg) 700{ 701 struct psycho_softc *sc = arg; 702 uint64_t afar, afsr; 703 704 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 705 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 706 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx " 707 "AFSR %#lx\n", (u_long)afar, (u_long)afsr); 708 /* Clear the error bits that we caught. */ 709 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr & CEAFSR_ERRMASK); 710 PSYCHO_WRITE8(sc, PSR_CE_INT_CLR, 0); 711} 712 713static void 714psycho_pci_bus(void *arg) 715{ 716 struct psycho_softc *sc = arg; 717 uint64_t afar, afsr; 718 719 afar = PCICTL_READ8(sc, PCR_AFA); 720 afsr = PCICTL_READ8(sc, PCR_AFS); 721 panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx", 722 device_get_name(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar, 723 (u_long)afsr); 724} 725 726static void 727psycho_powerfail(void *arg) 728{ 729 730#ifdef DEBUGGER_ON_POWERFAIL 731 struct psycho_softc *sc = arg; 732 733 kdb_enter("powerfail"); 734 PSYCHO_WRITE8(sc, PSR_POWER_INT_CLR, 0); 735#else 736 printf("Power Failure Detected: Shutting down NOW.\n"); 737 shutdown_nice(0); 738#endif 739} 740 741static void 742psycho_overtemp(void *arg) 743{ 744 745 printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n"); 746 shutdown_nice(RB_POWEROFF); 747} 748 749#ifdef PSYCHO_MAP_WAKEUP 750static void 751psycho_wakeup(void *arg) 752{ 753 struct psycho_softc *sc = arg; 754 755 PSYCHO_WRITE8(sc, PSR_PWRMGT_INT_CLR, 0); 756 /* Gee, we don't really have a framework to deal with this properly. */ 757 device_printf(sc->sc_dev, "power management wakeup\n"); 758} 759#endif /* PSYCHO_MAP_WAKEUP */ 760 761static void 762psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase) 763{ 764 char *name; 765 struct iommu_state *is = sc->sc_is; 766 767 /* Punch in our copies. */ 768 is->is_bustag = sc->sc_bustag; 769 is->is_bushandle = sc->sc_bushandle; 770 is->is_iommu = PSR_IOMMU; 771 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 772 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 773 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 774 is->is_dva = PSR_IOMMU_SVADIAG; 775 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 776 777 /* Give us a nice name... */ 778 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 779 if (name == 0) 780 panic("%s: could not malloc iommu name", __func__); 781 snprintf(name, 32, "%s dvma", device_get_nameunit(sc->sc_dev)); 782 783 iommu_init(name, is, tsbsize, dvmabase, 0); 784} 785 786static int 787psycho_maxslots(device_t dev) 788{ 789 790 /* XXX: is this correct? */ 791 return (PCI_SLOTMAX); 792} 793 794static uint32_t 795psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 796 int width) 797{ 798 struct psycho_softc *sc; 799 bus_space_handle_t bh; 800 u_long offset = 0; 801 uint8_t byte; 802 uint16_t shrt; 803 uint32_t wrd; 804 uint32_t r; 805 int i; 806 807 sc = device_get_softc(dev); 808 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 809 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 810 switch (width) { 811 case 1: 812 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 813 r = byte; 814 break; 815 case 2: 816 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 817 r = shrt; 818 break; 819 case 4: 820 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 821 r = wrd; 822 break; 823 default: 824 panic("%s: bad width", __func__); 825 } 826 827 if (i) { 828#ifdef PSYCHO_DEBUG 829 printf("Psycho read data error reading: %d.%d.%d: 0x%x\n", 830 bus, slot, func, reg); 831#endif 832 r = -1; 833 } 834 return (r); 835} 836 837static void 838psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 839 uint32_t val, int width) 840{ 841 struct psycho_softc *sc; 842 bus_space_handle_t bh; 843 u_long offset = 0; 844 845 sc = device_get_softc(dev); 846 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 847 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 848 switch (width) { 849 case 1: 850 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 851 break; 852 case 2: 853 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 854 break; 855 case 4: 856 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 857 break; 858 default: 859 panic("%s: bad width", __func__); 860 } 861} 862 863static int 864psycho_route_interrupt(device_t bridge, device_t dev, int pin) 865{ 866 struct psycho_softc *sc; 867 struct ofw_pci_register reg; 868 bus_addr_t intrmap; 869 phandle_t node = ofw_bus_get_node(dev); 870 ofw_pci_intr_t pintr, mintr; 871 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 872 873 sc = device_get_softc(bridge); 874 pintr = pin; 875 if (ofw_bus_lookup_imap(node, &sc->sc_pci_iinfo, ®, sizeof(reg), 876 &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) 877 return (mintr); 878 /* 879 * If this is outside of the range for an intpin, it's likely a full 880 * INO, and no mapping is required at all; this happens on the U30, 881 * where there's no interrupt map at the Psycho node. Fortunately, 882 * there seem to be no INOs in the intpin range on this boxen, so 883 * this easy heuristics will do. 884 */ 885 if (pin > 4) 886 return (pin); 887 /* 888 * Guess the INO; we always assume that this is a non-OBIO 889 * device, and that pin is a "real" intpin number. Determine 890 * the mapping register to be used by the slot number. 891 * We only need to do this on E450s, it seems; here, the slot numbers 892 * for bus A are one-based, while those for bus B seemingly have an 893 * offset of 2 (hence the factor of 3 below). 894 */ 895 intrmap = PSR_PCIA0_INT_MAP + 896 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half); 897 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1; 898 device_printf(bridge, "guessing interrupt %d for device %d/%d pin %d\n", 899 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin); 900 return (mintr); 901} 902 903static int 904psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 905{ 906 struct psycho_softc *sc; 907 908 sc = device_get_softc(dev); 909 switch (which) { 910 case PCIB_IVAR_BUS: 911 *result = sc->sc_pci_secbus; 912 return (0); 913 } 914 return (ENOENT); 915} 916 917/* Write to the correct clr register, and call the actual handler. */ 918static void 919psycho_intr_stub(void *arg) 920{ 921 struct psycho_clr *pc = arg; 922 923 pc->pci_handler(pc->pci_arg); 924 PSYCHO_WRITE8(pc->pci_sc, pc->pci_clr, 0); 925} 926 927static int 928psycho_setup_intr(device_t dev, device_t child, struct resource *ires, 929 int flags, driver_intr_t *intr, void *arg, void **cookiep) 930{ 931 struct psycho_softc *sc; 932 struct psycho_clr *pc; 933 bus_addr_t intrmapptr, intrclrptr; 934 long vec = rman_get_start(ires); 935 uint64_t mr; 936 int ino, error; 937 938 sc = device_get_softc(dev); 939 pc = (struct psycho_clr *)malloc(sizeof(*pc), M_DEVBUF, M_NOWAIT); 940 if (pc == NULL) 941 return (0); 942 943 /* 944 * Hunt through all the interrupt mapping regs to look for our 945 * interrupt vector. 946 * 947 * XXX We only compare INOs rather than IGNs since the firmware may 948 * not provide the IGN and the IGN is constant for all devices on that 949 * PCI controller. This could cause problems for the FFB/external 950 * interrupt which has a full vector that can be set arbitrarily. 951 */ 952 ino = INTINO(vec); 953 954 if (!psycho_find_intrmap(sc, ino, &intrmapptr, &intrclrptr, NULL)) { 955 device_printf(dev, "Cannot find interrupt vector %lx\n", vec); 956 free(pc, M_DEVBUF); 957 return (0); 958 } 959 960#ifdef PSYCHO_DEBUG 961 device_printf(dev, "%s: INO %d, map %#lx, clr %#lx\n", __func__, ino, 962 (u_long)intrmapptr, (u_long)intrclrptr); 963#endif 964 pc->pci_sc = sc; 965 pc->pci_arg = arg; 966 pc->pci_handler = intr; 967 pc->pci_clr = intrclrptr; 968 /* Disable the interrupt while we fiddle with it */ 969 mr = PSYCHO_READ8(sc, intrmapptr); 970 PSYCHO_WRITE8(sc, intrmapptr, mr & ~INTMAP_V); 971 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 972 psycho_intr_stub, pc, cookiep); 973 if (error != 0) { 974 free(pc, M_DEVBUF); 975 return (error); 976 } 977 pc->pci_cookie = *cookiep; 978 *cookiep = pc; 979 980 /* 981 * Clear the interrupt, it might have been triggered before it was 982 * set up. 983 */ 984 PSYCHO_WRITE8(sc, intrclrptr, 0); 985 /* 986 * Enable the interrupt and program the target module now we have the 987 * handler installed. 988 */ 989 PSYCHO_WRITE8(sc, intrmapptr, INTMAP_ENABLE(mr, PCPU_GET(mid))); 990 return (error); 991} 992 993static int 994psycho_teardown_intr(device_t dev, device_t child, struct resource *vec, 995 void *cookie) 996{ 997 struct psycho_clr *pc = cookie; 998 int error; 999 1000 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 1001 pc->pci_cookie); 1002 /* 1003 * Don't disable the interrupt for now, so that stray interupts get 1004 * detected... 1005 */ 1006 if (error != 0) 1007 free(pc, M_DEVBUF); 1008 return (error); 1009} 1010 1011static struct resource * 1012psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1013 u_long start, u_long end, u_long count, u_int flags) 1014{ 1015 struct psycho_softc *sc; 1016 struct resource *rv; 1017 struct rman *rm; 1018 bus_space_tag_t bt; 1019 bus_space_handle_t bh; 1020 int needactivate = flags & RF_ACTIVE; 1021 1022 flags &= ~RF_ACTIVE; 1023 1024 sc = device_get_softc(bus); 1025 if (type == SYS_RES_IRQ) { 1026 /* 1027 * XXX: Don't accept blank ranges for now, only single 1028 * interrupts. The other case should not happen with the 1029 * MI PCI code... 1030 * XXX: This may return a resource that is out of the 1031 * range that was specified. Is this correct...? 1032 */ 1033 if (start != end) 1034 panic("%s: XXX: interrupt range", __func__); 1035 start = end |= sc->sc_ign; 1036 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, 1037 rid, start, end, count, flags)); 1038 } 1039 switch (type) { 1040 case SYS_RES_MEMORY: 1041 rm = &sc->sc_pci_mem_rman; 1042 bt = sc->sc_pci_memt; 1043 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1044 break; 1045 case SYS_RES_IOPORT: 1046 rm = &sc->sc_pci_io_rman; 1047 bt = sc->sc_pci_iot; 1048 bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1049 break; 1050 default: 1051 return (NULL); 1052 } 1053 1054 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1055 if (rv == NULL) 1056 return (NULL); 1057 1058 bh += rman_get_start(rv); 1059 rman_set_bustag(rv, bt); 1060 rman_set_bushandle(rv, bh); 1061 1062 if (needactivate) { 1063 if (bus_activate_resource(child, type, *rid, rv)) { 1064 rman_release_resource(rv); 1065 return (NULL); 1066 } 1067 } 1068 1069 return (rv); 1070} 1071 1072static int 1073psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1074 struct resource *r) 1075{ 1076 void *p; 1077 int error; 1078 1079 if (type == SYS_RES_IRQ) 1080 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1081 type, rid, r)); 1082 if (type == SYS_RES_MEMORY) { 1083 /* 1084 * Need to memory-map the device space, as some drivers depend 1085 * on the virtual address being set and useable. 1086 */ 1087 error = sparc64_bus_mem_map(rman_get_bustag(r), 1088 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1089 if (error != 0) 1090 return (error); 1091 rman_set_virtual(r, p); 1092 } 1093 return (rman_activate_resource(r)); 1094} 1095 1096static int 1097psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1098 struct resource *r) 1099{ 1100 1101 if (type == SYS_RES_IRQ) 1102 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1103 type, rid, r)); 1104 if (type == SYS_RES_MEMORY) { 1105 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1106 rman_set_virtual(r, NULL); 1107 } 1108 return (rman_deactivate_resource(r)); 1109} 1110 1111static int 1112psycho_release_resource(device_t bus, device_t child, int type, int rid, 1113 struct resource *r) 1114{ 1115 int error; 1116 1117 if (type == SYS_RES_IRQ) 1118 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1119 type, rid, r)); 1120 if (rman_get_flags(r) & RF_ACTIVE) { 1121 error = bus_deactivate_resource(child, type, rid, r); 1122 if (error) 1123 return error; 1124 } 1125 return (rman_release_resource(r)); 1126} 1127 1128static int 1129psycho_intr_pending(device_t dev, ofw_pci_intr_t intr) 1130{ 1131 struct psycho_softc *sc; 1132 u_long diag; 1133 1134 sc = device_get_softc(dev); 1135 if (!psycho_find_intrmap(sc, intr, NULL, NULL, &diag)) { 1136 device_printf(dev, "%s: mapping not found for %d\n", __func__, 1137 intr); 1138 return (0); 1139 } 1140 return (diag != 0); 1141} 1142 1143static bus_space_handle_t 1144psycho_get_bus_handle(device_t dev, int type, bus_space_handle_t childhdl, 1145 bus_space_tag_t *tag) 1146{ 1147 struct psycho_softc *sc; 1148 1149 sc = device_get_softc(dev); 1150 switch (type) { 1151 case SYS_RES_IOPORT: 1152 *tag = sc->sc_pci_iot; 1153 return (sc->sc_pci_bh[OFW_PCI_CS_IO] + childhdl); 1154 case SYS_RES_MEMORY: 1155 *tag = sc->sc_pci_memt; 1156 return (sc->sc_pci_bh[OFW_PCI_CS_MEM32] + childhdl); 1157 default: 1158 panic("%s: illegal space (%d)\n", __func__, type); 1159 } 1160} 1161 1162static phandle_t 1163psycho_get_node(device_t bus, device_t dev) 1164{ 1165 struct psycho_softc *sc; 1166 1167 sc = device_get_softc(bus); 1168 /* We only have one child, the PCI bus, which needs our own node. */ 1169 return (sc->sc_node); 1170} 1171 1172static void 1173psycho_adjust_busrange(device_t dev, u_int subbus) 1174{ 1175 struct psycho_softc *sc; 1176 1177 sc = device_get_softc(dev); 1178 /* If necessary, adjust the subordinate bus number register. */ 1179 if (subbus > sc->sc_pci_subbus) { 1180#ifdef PSYCHO_DEBUG 1181 device_printf(dev, 1182 "adjusting secondary bus number from %d to %d\n", 1183 sc->sc_pci_subbus, subbus); 1184#endif 1185 sc->sc_pci_subbus = subbus; 1186 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, 1187 PCSR_SUBBUS, subbus, 1); 1188 } 1189} 1190 1191static bus_space_tag_t 1192psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1193{ 1194 bus_space_tag_t bt; 1195 1196 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1197 M_NOWAIT | M_ZERO); 1198 if (bt == NULL) 1199 panic("%s: out of memory", __func__); 1200 1201 bt->bst_cookie = sc; 1202 bt->bst_parent = sc->sc_bustag; 1203 bt->bst_type = type; 1204 return (bt); 1205} 1206