psycho.c revision 152698
1/*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: head/sys/sparc64/pci/psycho.c 152698 2005-11-22 22:32:50Z marius $"); 34 35/* 36 * Support for `Psycho' and `Psycho+' UPA to PCI bridge and 37 * UltraSPARC IIi and IIe `Sabre' PCI controllers 38 */ 39 40#include "opt_ofw_pci.h" 41#include "opt_psycho.h" 42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/bus.h> 46#include <sys/kdb.h> 47#include <sys/kernel.h> 48#include <sys/module.h> 49#include <sys/malloc.h> 50#include <sys/pcpu.h> 51 52#include <dev/ofw/ofw_bus.h> 53#include <dev/ofw/ofw_pci.h> 54#include <dev/ofw/openfirm.h> 55 56#include <machine/bus.h> 57#include <machine/bus_private.h> 58#include <machine/iommureg.h> 59#include <machine/bus_common.h> 60#include <machine/nexusvar.h> 61#include <machine/ofw_bus.h> 62#include <machine/ofw_upa.h> 63#include <machine/resource.h> 64#include <machine/ver.h> 65 66#include <sys/rman.h> 67 68#include <machine/iommuvar.h> 69 70#include <dev/pci/pcivar.h> 71 72#include <sparc64/pci/ofw_pci.h> 73#include <sparc64/pci/psychoreg.h> 74#include <sparc64/pci/psychovar.h> 75 76#include "pcib_if.h" 77 78static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *, 79 const char *); 80static const struct psycho_desc *psycho_get_desc(phandle_t, const char *); 81static void psycho_set_intr(struct psycho_softc *, int, device_t, bus_addr_t, 82 int, driver_intr_t); 83static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *, 84 bus_addr_t *, u_long *); 85static void psycho_intr_stub(void *); 86static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 87 88/* Interrupt handlers */ 89static void psycho_ue(void *); 90static void psycho_ce(void *); 91static void psycho_bus_a(void *); 92static void psycho_bus_b(void *); 93static void psycho_powerfail(void *); 94#ifdef PSYCHO_MAP_WAKEUP 95static void psycho_wakeup(void *); 96#endif 97 98/* IOMMU support */ 99static void psycho_iommu_init(struct psycho_softc *, int, uint32_t); 100 101/* 102 * Methods 103 */ 104static device_probe_t psycho_probe; 105static device_attach_t psycho_attach; 106static bus_read_ivar_t psycho_read_ivar; 107static bus_setup_intr_t psycho_setup_intr; 108static bus_teardown_intr_t psycho_teardown_intr; 109static bus_alloc_resource_t psycho_alloc_resource; 110static bus_activate_resource_t psycho_activate_resource; 111static bus_deactivate_resource_t psycho_deactivate_resource; 112static bus_release_resource_t psycho_release_resource; 113static pcib_maxslots_t psycho_maxslots; 114static pcib_read_config_t psycho_read_config; 115static pcib_write_config_t psycho_write_config; 116static pcib_route_interrupt_t psycho_route_interrupt; 117static ofw_pci_intr_pending_t psycho_intr_pending; 118static ofw_pci_get_bus_handle_t psycho_get_bus_handle; 119static ofw_bus_get_node_t psycho_get_node; 120static ofw_pci_adjust_busrange_t psycho_adjust_busrange; 121 122static device_method_t psycho_methods[] = { 123 /* Device interface */ 124 DEVMETHOD(device_probe, psycho_probe), 125 DEVMETHOD(device_attach, psycho_attach), 126 127 /* Bus interface */ 128 DEVMETHOD(bus_print_child, bus_generic_print_child), 129 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 130 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 131 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 132 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 133 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 134 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 135 DEVMETHOD(bus_release_resource, psycho_release_resource), 136 137 /* pcib interface */ 138 DEVMETHOD(pcib_maxslots, psycho_maxslots), 139 DEVMETHOD(pcib_read_config, psycho_read_config), 140 DEVMETHOD(pcib_write_config, psycho_write_config), 141 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 142 143 /* ofw_bus interface */ 144 DEVMETHOD(ofw_bus_get_node, psycho_get_node), 145 146 /* ofw_pci interface */ 147 DEVMETHOD(ofw_pci_intr_pending, psycho_intr_pending), 148 DEVMETHOD(ofw_pci_get_bus_handle, psycho_get_bus_handle), 149 DEVMETHOD(ofw_pci_adjust_busrange, psycho_adjust_busrange), 150 151 { 0, 0 } 152}; 153 154static driver_t psycho_driver = { 155 "pcib", 156 psycho_methods, 157 sizeof(struct psycho_softc), 158}; 159 160static devclass_t psycho_devclass; 161 162DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 163 164SLIST_HEAD(, psycho_softc) psycho_softcs = 165 SLIST_HEAD_INITIALIZER(psycho_softcs); 166 167struct psycho_clr { 168 struct psycho_softc *pci_sc; 169 bus_addr_t pci_clr; /* clear register */ 170 driver_intr_t *pci_handler; /* handler to call */ 171 void *pci_arg; /* argument for the handler */ 172 void *pci_cookie; /* parent bus int. cookie */ 173}; 174 175#define PSYCHO_READ8(sc, off) \ 176 bus_space_read_8((sc)->sc_bustag, (sc)->sc_bushandle, (off)) 177#define PSYCHO_WRITE8(sc, off, v) \ 178 bus_space_write_8((sc)->sc_bustag, (sc)->sc_bushandle, (off), (v)) 179#define PCICTL_READ8(sc, off) \ 180 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 181#define PCICTL_WRITE8(sc, off, v) \ 182 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 183 184/* 185 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 186 * single PCI bus and does not have a streaming buffer. It often has an APB 187 * (advanced PCI bridge) connected to it, which was designed specifically for 188 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 189 * appears as two "Simba"'s underneath the Sabre. 190 * 191 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA bus 192 * and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while 193 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 194 * will usually find a "Psycho+" since I don't think the original "Psycho" 195 * ever shipped, and if it did it would be in the U30. 196 * 197 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are 198 * both part of the same IC, they only have a single register space. As such, 199 * they need to be configured together, even though the autoconfiguration will 200 * attach them separately. 201 * 202 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often 203 * as pci1 and pci2, although they have been implemented with other PCI bus 204 * numbers on some machines. 205 * 206 * On UltraII machines, there can be any number of "Psycho+" ICs, each 207 * providing two PCI buses. 208 */ 209#ifdef DEBUGGER_ON_POWERFAIL 210#define PSYCHO_PWRFAIL_INT_FLAGS INTR_FAST 211#else 212#define PSYCHO_PWRFAIL_INT_FLAGS 0 213#endif 214 215#define OFW_PCI_TYPE "pci" 216 217struct psycho_desc { 218 const char *pd_string; 219 int pd_mode; 220 const char *pd_name; 221}; 222 223static const struct psycho_desc psycho_compats[] = { 224 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 225 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre (US-IIi) compatible" }, 226 { "pci108e,a001", PSYCHO_MODE_SABRE, "Sabre (US-IIe) compatible" }, 227 { NULL, 0, NULL } 228}; 229 230static const struct psycho_desc psycho_models[] = { 231 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 232 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 233 { NULL, 0, NULL } 234}; 235 236static const struct psycho_desc * 237psycho_find_desc(const struct psycho_desc *table, const char *string) 238{ 239 const struct psycho_desc *desc; 240 241 for (desc = table; desc->pd_string != NULL; desc++) { 242 if (strcmp(desc->pd_string, string) == 0) 243 return (desc); 244 } 245 return (NULL); 246} 247 248static const struct psycho_desc * 249psycho_get_desc(phandle_t node, const char *model) 250{ 251 const struct psycho_desc *rv; 252 char compat[32]; 253 254 rv = NULL; 255 if (model != NULL) 256 rv = psycho_find_desc(psycho_models, model); 257 if (rv == NULL && 258 OF_getprop(node, "compatible", compat, sizeof(compat)) != -1) 259 rv = psycho_find_desc(psycho_compats, compat); 260 return (rv); 261} 262 263static int 264psycho_probe(device_t dev) 265{ 266 const char *dtype; 267 268 dtype = nexus_get_device_type(dev); 269 if (nexus_get_reg(dev) != NULL && dtype != NULL && 270 strcmp(dtype, OFW_PCI_TYPE) == 0 && 271 psycho_get_desc(nexus_get_node(dev), 272 nexus_get_model(dev)) != NULL) { 273 device_set_desc(dev, "U2P UPA-PCI bridge"); 274 return (0); 275 } 276 277 return (ENXIO); 278} 279 280static int 281psycho_attach(device_t dev) 282{ 283 struct psycho_softc *sc; 284 struct psycho_softc *osc = NULL; 285 struct psycho_softc *asc; 286 struct upa_ranges *range; 287 struct upa_regs *reg; 288 const struct psycho_desc *desc; 289 phandle_t node; 290 uint64_t csr; 291 uint32_t dvmabase; 292 u_long mlen; 293 int psycho_br[2]; 294 int n, i, nrange, nreg, rid; 295#ifdef PSYCHO_DEBUG 296 bus_addr_t map, clr; 297 uint64_t mr; 298#endif 299 300 node = nexus_get_node(dev); 301 sc = device_get_softc(dev); 302 desc = psycho_get_desc(node, nexus_get_model(dev)); 303 304 sc->sc_node = node; 305 sc->sc_dev = dev; 306 sc->sc_mode = desc->pd_mode; 307 308 /* 309 * The Psycho gets three register banks: 310 * (0) per-PBM configuration and status registers 311 * (1) per-PBM PCI configuration space, containing only the 312 * PBM 256-byte PCI header 313 * (2) the shared Psycho configuration registers 314 */ 315 reg = nexus_get_reg(dev); 316 nreg = nexus_get_nreg(dev); 317 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 318 if (nreg <= 2) 319 panic("%s: %d not enough registers", __func__, nreg); 320 sc->sc_basepaddr = (vm_paddr_t)UPA_REG_PHYS(®[2]); 321 mlen = UPA_REG_SIZE(®[2]); 322 sc->sc_pcictl = UPA_REG_PHYS(®[0]) - sc->sc_basepaddr; 323 switch (sc->sc_pcictl) { 324 case PSR_PCICTL0: 325 sc->sc_half = 0; 326 break; 327 case PSR_PCICTL1: 328 sc->sc_half = 1; 329 break; 330 default: 331 panic("%s: bogus PCI control register location", 332 __func__); 333 } 334 } else { 335 if (nreg <= 0) 336 panic("%s: %d not enough registers", __func__, nreg); 337 sc->sc_basepaddr = (vm_paddr_t)UPA_REG_PHYS(®[0]); 338 mlen = UPA_REG_SIZE(reg); 339 sc->sc_pcictl = PSR_PCICTL0; 340 sc->sc_half = 0; 341 } 342 343 /* 344 * Match other Psycho's that are already configured against 345 * the base physical address. This will be the same for a 346 * pair of devices that share register space. 347 */ 348 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 349 if (asc->sc_basepaddr == sc->sc_basepaddr) { 350 /* Found partner. */ 351 osc = asc; 352 break; 353 } 354 } 355 356 if (osc == NULL) { 357 rid = 0; 358 sc->sc_mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 359 sc->sc_basepaddr, sc->sc_basepaddr + mlen - 1, mlen, 360 RF_ACTIVE); 361 if (sc->sc_mem_res == NULL || 362 rman_get_start(sc->sc_mem_res) != sc->sc_basepaddr) 363 panic("%s: could not allocate device memory", __func__); 364 sc->sc_bustag = rman_get_bustag(sc->sc_mem_res); 365 sc->sc_bushandle = rman_get_bushandle(sc->sc_mem_res); 366 } else { 367 /* 368 * There's another Psycho using the same register space. 369 * Copy the relevant stuff. 370 */ 371 sc->sc_mem_res = NULL; 372 sc->sc_bustag = osc->sc_bustag; 373 sc->sc_bushandle = osc->sc_bushandle; 374 } 375 csr = PSYCHO_READ8(sc, PSR_CS); 376 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 377 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 378 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << INTMAP_IGN_SHIFT; 379 380 device_printf(dev, "%s, impl %d, version %d, ign %#x, bus %c\n", 381 desc->pd_name, (int)PSYCHO_GCSR_IMPL(csr), 382 (int)PSYCHO_GCSR_VERS(csr), sc->sc_ign, 'A' + sc->sc_half); 383 384 /* Setup the PCI control register. */ 385 csr = PCICTL_READ8(sc, PCR_CS); 386 csr |= PCICTL_MRLM | PCICTL_ARB_PARK | PCICTL_ERRINTEN | PCICTL_4ENABLE; 387 csr &= ~(PCICTL_SERR | PCICTL_CPU_PRIO | PCICTL_ARB_PRIO | 388 PCICTL_RTRYWAIT); 389 PCICTL_WRITE8(sc, PCR_CS, csr); 390 391 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 392 /* Use the PROM preset for now. */ 393 csr = PCICTL_READ8(sc, PCR_TAS); 394 if (csr == 0) 395 panic("%s: Sabre TAS not initialized.", __func__); 396 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT; 397 } else 398 dvmabase = -1; 399 400 /* Initialize memory and I/O rmans. */ 401 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 402 sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports"; 403 if (rman_init(&sc->sc_pci_io_rman) != 0 || 404 rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0) 405 panic("%s: failed to set up I/O rman", __func__); 406 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 407 sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory"; 408 if (rman_init(&sc->sc_pci_mem_rman) != 0 || 409 rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 410 panic("%s: failed to set up memory rman", __func__); 411 412 nrange = OF_getprop_alloc(node, "ranges", sizeof(*range), 413 (void **)&range); 414 /* 415 * Make sure that the expected ranges are present. The PCI_CS_MEM64 416 * one is not currently used though. 417 */ 418 if (nrange != PSYCHO_NRANGE) 419 panic("%s: unsupported number of ranges", __func__); 420 /* 421 * Find the addresses of the various bus spaces. 422 * There should not be multiple ones of one kind. 423 * The physical start addresses of the ranges are the configuration, 424 * memory and I/O handles. 425 */ 426 for (n = 0; n < PSYCHO_NRANGE; n++) { 427 i = UPA_RANGE_CS(&range[n]); 428 if (sc->sc_pci_bh[i] != 0) 429 panic("%s: duplicate range for space %d", __func__, i); 430 sc->sc_pci_bh[i] = UPA_RANGE_PHYS(&range[n]); 431 } 432 free(range, M_OFWPROP); 433 434 /* Register the softc, this is needed for paired Psychos. */ 435 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 436 437 /* 438 * If we're a Sabre or the first of a pair of Psycho's to arrive here, 439 * start up the IOMMU. 440 */ 441 if (osc == NULL) { 442 /* 443 * Establish handlers for interesting interrupts... 444 * 445 * XXX We need to remember these and remove this to support 446 * hotplug on the UPA/FHC bus. 447 * 448 * XXX Not all controllers have these, but installing them 449 * is better than trying to sort through this mess. 450 */ 451 psycho_set_intr(sc, 0, dev, PSR_UE_INT_MAP, INTR_FAST, 452 psycho_ue); 453 psycho_set_intr(sc, 1, dev, PSR_CE_INT_MAP, 0, psycho_ce); 454 psycho_set_intr(sc, 2, dev, PSR_PCIAERR_INT_MAP, INTR_FAST, 455 psycho_bus_a); 456 psycho_set_intr(sc, 4, dev, PSR_POWER_INT_MAP, 457 PSYCHO_PWRFAIL_INT_FLAGS, psycho_powerfail); 458 /* Psycho-specific initialization */ 459 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 460 /* 461 * Sabres do not have the following two interrupts. 462 */ 463 psycho_set_intr(sc, 3, dev, PSR_PCIBERR_INT_MAP, 464 INTR_FAST, psycho_bus_b); 465#ifdef PSYCHO_MAP_WAKEUP 466 /* 467 * psycho_wakeup() doesn't do anything useful right 468 * now. 469 */ 470 psycho_set_intr(sc, 5, dev, PSR_PWRMGT_INT_MAP, 0, 471 psycho_wakeup); 472#endif /* PSYCHO_MAP_WAKEUP */ 473 474 /* Initialize the counter-timer. */ 475 sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, 476 PSR_TC0); 477 } 478 479 /* 480 * Setup IOMMU and PCI configuration if we're the first 481 * of a pair of Psycho's to arrive here. 482 * 483 * We should calculate a TSB size based on amount of RAM 484 * and number of bus controllers and number and type of 485 * child devices. 486 * 487 * For the moment, 32KB should be more than enough. 488 */ 489 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 490 M_NOWAIT); 491 if (sc->sc_is == NULL) 492 panic("%s: malloc iommu_state failed", __func__); 493 sc->sc_is->is_sb[0] = 0; 494 sc->sc_is->is_sb[1] = 0; 495 if (OF_getproplen(node, "no-streaming-cache") < 0) 496 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 497 psycho_iommu_init(sc, 3, dvmabase); 498 } else { 499 /* Just copy IOMMU state, config tag and address */ 500 sc->sc_is = osc->sc_is; 501 if (OF_getproplen(node, "no-streaming-cache") < 0) 502 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 503 iommu_reset(sc->sc_is); 504 } 505 506 /* Allocate our tags. */ 507 sc->sc_pci_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 508 sc->sc_pci_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 509 sc->sc_pci_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 510 if (bus_dma_tag_create(nexus_get_dmatag(dev), 8, 1, 0, 0x3ffffffff, 511 NULL, NULL, 0x3ffffffff, 0xff, 0xffffffff, 0, NULL, NULL, 512 &sc->sc_pci_dmat) != 0) 513 panic("%s: bus_dma_tag_create failed", __func__); 514 /* Customize the tag. */ 515 sc->sc_pci_dmat->dt_cookie = sc->sc_is; 516 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 517 /* XXX: register as root DMA tag (kludge). */ 518 sparc64_root_dma_tag = sc->sc_pci_dmat; 519 520#ifdef PSYCHO_DEBUG 521 /* 522 * Enable all interrupts and clear all interrupt states. 523 * This aids the debugging of interrupt routing problems. 524 */ 525 for (map = PSR_PCIA0_INT_MAP, clr = PSR_PCIA0_INT_CLR, n = 0; 526 map <= PSR_PCIB3_INT_MAP; map += 8, clr += 32, n++) { 527 mr = PSYCHO_READ8(sc, map); 528 device_printf(dev, "intr map (pci) %d: %#lx\n", n, (u_long)mr); 529 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 530 for (i = 0; i < 4; i++) 531 PCICTL_WRITE8(sc, clr + i * 8, 0); 532 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 533 } 534 for (map = PSR_SCSI_INT_MAP, clr = PSR_SCSI_INT_CLR, n = 0; 535 map <= PSR_SERIAL_INT_MAP; map += 8, clr += 8, n++) { 536 mr = PSYCHO_READ8(sc, map); 537 device_printf(dev, "intr map (obio) %d: %#lx, clr: %#lx\n", n, 538 (u_long)mr, (u_long)clr); 539 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 540 PSYCHO_WRITE8(sc, clr, 0); 541 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 542 } 543#endif /* PSYCHO_DEBUG */ 544 545 /* 546 * Get the bus range from the firmware; it is used solely for obtaining 547 * the inital bus number, and cannot be trusted on all machines. 548 */ 549 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br)); 550 if (n == -1) 551 panic("%s: could not get Psycho bus-range", __func__); 552 if (n != sizeof(psycho_br)) 553 panic("%s: broken Psycho bus-range (%d)", __func__, n); 554 555 sc->sc_pci_secbus = sc->sc_pci_subbus = ofw_pci_alloc_busno(node); 556 /* 557 * Program the bus range registers. 558 * NOTE: for the Psycho, the second write changes the bus number the 559 * Psycho itself uses for it's configuration space, so these 560 * writes must be kept in this order! 561 * The Sabre always uses bus 0, but there only can be one Sabre per 562 * machine. 563 */ 564 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SUBBUS, 565 sc->sc_pci_subbus, 1); 566 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SECBUS, 567 sc->sc_pci_secbus, 1); 568 569 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 570 /* 571 * Workaround for incorrect interrupt map entries on E250. 572 */ 573 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 && 574 sc->sc_pci_iinfo.opi_imapmsk != NULL) 575 *(ofw_pci_intr_t *)(&sc->sc_pci_iinfo.opi_imapmsk[ 576 sc->sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK; 577 578 device_add_child(dev, "pci", sc->sc_pci_secbus); 579 return (bus_generic_attach(dev)); 580} 581 582static void 583psycho_set_intr(struct psycho_softc *sc, int index, device_t dev, 584 bus_addr_t map, int iflags, driver_intr_t handler) 585{ 586 int rid, vec; 587 uint64_t mr; 588 589 mr = PSYCHO_READ8(sc, map); 590 vec = INTVEC(mr); 591 sc->sc_irq_res[index] = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 592 vec, vec, 1, RF_ACTIVE); 593 if (sc->sc_irq_res[index] == NULL) 594 panic("%s: failed to get interrupt", __func__); 595 bus_setup_intr(dev, sc->sc_irq_res[index], INTR_TYPE_MISC | iflags, 596 handler, sc, &sc->sc_ihand[index]); 597 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 598} 599 600static int 601psycho_find_intrmap(struct psycho_softc *sc, int ino, bus_addr_t *intrmapptr, 602 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 603{ 604 bus_addr_t intrmap, intrclr; 605 uint64_t im; 606 u_long diag; 607 int found; 608 609 found = 0; 610 /* Hunt thru obio first */ 611 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 612 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 613 intrmap <= PSR_SERIAL_INT_MAP; intrmap += 8, intrclr += 8, 614 diag >>= 2) { 615 im = PSYCHO_READ8(sc, intrmap); 616 if (INTINO(im) == ino) { 617 diag &= 2; 618 found = 1; 619 break; 620 } 621 } 622 623 if (!found) { 624 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 625 /* Now do PCI interrupts */ 626 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 627 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 628 diag >>= 8) { 629 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 630 (intrmap == PSR_PCIA2_INT_MAP || 631 intrmap == PSR_PCIA3_INT_MAP)) 632 continue; 633 im = PSYCHO_READ8(sc, intrmap); 634 if (((im ^ ino) & 0x3c) == 0) { 635 intrclr += 8 * (ino & 3); 636 diag = (diag >> ((ino & 3) * 2)) & 2; 637 found = 1; 638 break; 639 } 640 } 641 } 642 if (intrmapptr != NULL) 643 *intrmapptr = intrmap; 644 if (intrclrptr != NULL) 645 *intrclrptr = intrclr; 646 if (intrdiagptr != NULL) 647 *intrdiagptr = diag; 648 return (found); 649} 650 651/* 652 * Interrupt handlers 653 */ 654static void 655psycho_ue(void *arg) 656{ 657 struct psycho_softc *sc = arg; 658 uint64_t afar, afsr; 659 660 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 661 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 662 /* 663 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 664 * the AFAR to be set to the physical address of the TTE entry that 665 * was invalid/write protected. Call into the iommu code to have 666 * them decoded to virtual IO addresses. 667 */ 668 if ((afsr & UEAFSR_P_DTE) != 0) 669 iommu_decode_fault(sc->sc_is, afar); 670 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx", 671 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 672} 673 674static void 675psycho_ce(void *arg) 676{ 677 struct psycho_softc *sc = arg; 678 uint64_t afar, afsr; 679 680 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 681 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 682 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx " 683 "AFSR %#lx\n", (u_long)afar, (u_long)afsr); 684 /* Clear the error bits that we caught. */ 685 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr & CEAFSR_ERRMASK); 686 PSYCHO_WRITE8(sc, PSR_CE_INT_CLR, 0); 687} 688 689static void 690psycho_bus_a(void *arg) 691{ 692 struct psycho_softc *sc = arg; 693 uint64_t afar, afsr; 694 695 afar = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFA); 696 afsr = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFS); 697 panic("%s: PCI bus A error AFAR %#lx AFSR %#lx", 698 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 699} 700 701static void 702psycho_bus_b(void *arg) 703{ 704 struct psycho_softc *sc = arg; 705 uint64_t afar, afsr; 706 707 afar = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFA); 708 afsr = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFS); 709 panic("%s: PCI bus B error AFAR %#lx AFSR %#lx", 710 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 711} 712 713static void 714psycho_powerfail(void *arg) 715{ 716 717#ifdef DEBUGGER_ON_POWERFAIL 718 struct psycho_softc *sc = arg; 719 720 kdb_enter("powerfail"); 721 PSYCHO_WRITE8(sc, PSR_POWER_INT_CLR, 0); 722#else 723 printf("Power Failure Detected: Shutting down NOW.\n"); 724 shutdown_nice(0); 725#endif 726} 727 728#ifdef PSYCHO_MAP_WAKEUP 729static void 730psycho_wakeup(void *arg) 731{ 732 struct psycho_softc *sc = arg; 733 734 PSYCHO_WRITE8(sc, PSR_PWRMGT_INT_CLR, 0); 735 /* Gee, we don't really have a framework to deal with this properly. */ 736 device_printf(sc->sc_dev, "power management wakeup\n"); 737} 738#endif /* PSYCHO_MAP_WAKEUP */ 739 740static void 741psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase) 742{ 743 char *name; 744 struct iommu_state *is = sc->sc_is; 745 746 /* Punch in our copies. */ 747 is->is_bustag = sc->sc_bustag; 748 is->is_bushandle = sc->sc_bushandle; 749 is->is_iommu = PSR_IOMMU; 750 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 751 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 752 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 753 is->is_dva = PSR_IOMMU_SVADIAG; 754 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 755 756 /* Give us a nice name... */ 757 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 758 if (name == 0) 759 panic("%s: could not malloc iommu name", __func__); 760 snprintf(name, 32, "%s dvma", device_get_nameunit(sc->sc_dev)); 761 762 iommu_init(name, is, tsbsize, dvmabase, 0); 763} 764 765static int 766psycho_maxslots(device_t dev) 767{ 768 769 /* XXX: is this correct? */ 770 return (PCI_SLOTMAX); 771} 772 773static uint32_t 774psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 775 int width) 776{ 777 struct psycho_softc *sc; 778 bus_space_handle_t bh; 779 u_long offset = 0; 780 uint8_t byte; 781 uint16_t shrt; 782 uint32_t wrd; 783 uint32_t r; 784 int i; 785 786 sc = device_get_softc(dev); 787 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 788 bh = sc->sc_pci_bh[PCI_CS_CONFIG]; 789 switch (width) { 790 case 1: 791 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 792 r = byte; 793 break; 794 case 2: 795 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 796 r = shrt; 797 break; 798 case 4: 799 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 800 r = wrd; 801 break; 802 default: 803 panic("%s: bad width", __func__); 804 } 805 806 if (i) { 807#ifdef PSYCHO_DEBUG 808 printf("Psycho read data error reading: %d.%d.%d: 0x%x\n", 809 bus, slot, func, reg); 810#endif 811 r = -1; 812 } 813 return (r); 814} 815 816static void 817psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 818 uint32_t val, int width) 819{ 820 struct psycho_softc *sc; 821 bus_space_handle_t bh; 822 u_long offset = 0; 823 824 sc = device_get_softc(dev); 825 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 826 bh = sc->sc_pci_bh[PCI_CS_CONFIG]; 827 switch (width) { 828 case 1: 829 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 830 break; 831 case 2: 832 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 833 break; 834 case 4: 835 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 836 break; 837 default: 838 panic("%s: bad width", __func__); 839 } 840} 841 842static int 843psycho_route_interrupt(device_t bridge, device_t dev, int pin) 844{ 845 struct psycho_softc *sc; 846 struct ofw_pci_register reg; 847 bus_addr_t intrmap; 848 phandle_t node = ofw_bus_get_node(dev); 849 ofw_pci_intr_t pintr, mintr; 850 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 851 852 sc = device_get_softc(bridge); 853 pintr = pin; 854 if (ofw_bus_lookup_imap(node, &sc->sc_pci_iinfo, ®, sizeof(reg), 855 &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) 856 return (mintr); 857 /* 858 * If this is outside of the range for an intpin, it's likely a full 859 * INO, and no mapping is required at all; this happens on the U30, 860 * where there's no interrupt map at the Psycho node. Fortunately, 861 * there seem to be no INOs in the intpin range on this boxen, so 862 * this easy heuristics will do. 863 */ 864 if (pin > 4) 865 return (pin); 866 /* 867 * Guess the INO; we always assume that this is a non-OBIO 868 * device, and that pin is a "real" intpin number. Determine 869 * the mapping register to be used by the slot number. 870 * We only need to do this on E450s, it seems; here, the slot numbers 871 * for bus A are one-based, while those for bus B seemingly have an 872 * offset of 2 (hence the factor of 3 below). 873 */ 874 intrmap = PSR_PCIA0_INT_MAP + 875 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half); 876 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1; 877 device_printf(bridge, "guessing interrupt %d for device %d/%d pin %d\n", 878 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin); 879 return (mintr); 880} 881 882static int 883psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 884{ 885 struct psycho_softc *sc; 886 887 sc = device_get_softc(dev); 888 switch (which) { 889 case PCIB_IVAR_BUS: 890 *result = sc->sc_pci_secbus; 891 return (0); 892 } 893 return (ENOENT); 894} 895 896/* Write to the correct clr register, and call the actual handler. */ 897static void 898psycho_intr_stub(void *arg) 899{ 900 struct psycho_clr *pc = arg; 901 902 pc->pci_handler(pc->pci_arg); 903 PSYCHO_WRITE8(pc->pci_sc, pc->pci_clr, 0); 904} 905 906static int 907psycho_setup_intr(device_t dev, device_t child, struct resource *ires, 908 int flags, driver_intr_t *intr, void *arg, void **cookiep) 909{ 910 struct psycho_softc *sc; 911 struct psycho_clr *pc; 912 bus_addr_t intrmapptr, intrclrptr; 913 long vec = rman_get_start(ires); 914 uint64_t mr; 915 int ino, error; 916 917 sc = device_get_softc(dev); 918 pc = (struct psycho_clr *)malloc(sizeof(*pc), M_DEVBUF, M_NOWAIT); 919 if (pc == NULL) 920 return (0); 921 922 /* 923 * Hunt through all the interrupt mapping regs to look for our 924 * interrupt vector. 925 * 926 * XXX We only compare INOs rather than IGNs since the firmware may 927 * not provide the IGN and the IGN is constant for all devices on that 928 * PCI controller. This could cause problems for the FFB/external 929 * interrupt which has a full vector that can be set arbitrarily. 930 */ 931 ino = INTINO(vec); 932 933 if (!psycho_find_intrmap(sc, ino, &intrmapptr, &intrclrptr, NULL)) { 934 device_printf(dev, "Cannot find interrupt vector %lx\n", vec); 935 free(pc, M_DEVBUF); 936 return (0); 937 } 938 939#ifdef PSYCHO_DEBUG 940 device_printf(dev, "%s: INO %d, map %#lx, clr %#lx\n", __func__, ino, 941 (u_long)intrmapptr, (u_long)intrclrptr); 942#endif 943 pc->pci_sc = sc; 944 pc->pci_arg = arg; 945 pc->pci_handler = intr; 946 pc->pci_clr = intrclrptr; 947 /* Disable the interrupt while we fiddle with it */ 948 mr = PSYCHO_READ8(sc, intrmapptr); 949 PSYCHO_WRITE8(sc, intrmapptr, mr & ~INTMAP_V); 950 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 951 psycho_intr_stub, pc, cookiep); 952 if (error != 0) { 953 free(pc, M_DEVBUF); 954 return (error); 955 } 956 pc->pci_cookie = *cookiep; 957 *cookiep = pc; 958 959 /* 960 * Clear the interrupt, it might have been triggered before it was 961 * set up. 962 */ 963 PSYCHO_WRITE8(sc, intrclrptr, 0); 964 /* 965 * Enable the interrupt and program the target module now we have the 966 * handler installed. 967 */ 968 PSYCHO_WRITE8(sc, intrmapptr, INTMAP_ENABLE(mr, PCPU_GET(mid))); 969 return (error); 970} 971 972static int 973psycho_teardown_intr(device_t dev, device_t child, struct resource *vec, 974 void *cookie) 975{ 976 struct psycho_clr *pc = cookie; 977 int error; 978 979 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 980 pc->pci_cookie); 981 /* 982 * Don't disable the interrupt for now, so that stray interupts get 983 * detected... 984 */ 985 if (error != 0) 986 free(pc, M_DEVBUF); 987 return (error); 988} 989 990static struct resource * 991psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 992 u_long start, u_long end, u_long count, u_int flags) 993{ 994 struct psycho_softc *sc; 995 struct resource *rv; 996 struct rman *rm; 997 bus_space_tag_t bt; 998 bus_space_handle_t bh; 999 int needactivate = flags & RF_ACTIVE; 1000 1001 flags &= ~RF_ACTIVE; 1002 1003 sc = device_get_softc(bus); 1004 if (type == SYS_RES_IRQ) { 1005 /* 1006 * XXX: Don't accept blank ranges for now, only single 1007 * interrupts. The other case should not happen with the 1008 * MI PCI code... 1009 * XXX: This may return a resource that is out of the 1010 * range that was specified. Is this correct...? 1011 */ 1012 if (start != end) 1013 panic("%s: XXX: interrupt range", __func__); 1014 start = end |= sc->sc_ign; 1015 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, 1016 rid, start, end, count, flags)); 1017 } 1018 switch (type) { 1019 case SYS_RES_MEMORY: 1020 rm = &sc->sc_pci_mem_rman; 1021 bt = sc->sc_pci_memt; 1022 bh = sc->sc_pci_bh[PCI_CS_MEM32]; 1023 break; 1024 case SYS_RES_IOPORT: 1025 rm = &sc->sc_pci_io_rman; 1026 bt = sc->sc_pci_iot; 1027 bh = sc->sc_pci_bh[PCI_CS_IO]; 1028 break; 1029 default: 1030 return (NULL); 1031 } 1032 1033 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1034 if (rv == NULL) 1035 return (NULL); 1036 1037 bh += rman_get_start(rv); 1038 rman_set_bustag(rv, bt); 1039 rman_set_bushandle(rv, bh); 1040 1041 if (needactivate) { 1042 if (bus_activate_resource(child, type, *rid, rv)) { 1043 rman_release_resource(rv); 1044 return (NULL); 1045 } 1046 } 1047 1048 return (rv); 1049} 1050 1051static int 1052psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1053 struct resource *r) 1054{ 1055 void *p; 1056 int error; 1057 1058 if (type == SYS_RES_IRQ) 1059 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1060 type, rid, r)); 1061 if (type == SYS_RES_MEMORY) { 1062 /* 1063 * Need to memory-map the device space, as some drivers depend 1064 * on the virtual address being set and useable. 1065 */ 1066 error = sparc64_bus_mem_map(rman_get_bustag(r), 1067 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1068 if (error != 0) 1069 return (error); 1070 rman_set_virtual(r, p); 1071 } 1072 return (rman_activate_resource(r)); 1073} 1074 1075static int 1076psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1077 struct resource *r) 1078{ 1079 1080 if (type == SYS_RES_IRQ) 1081 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1082 type, rid, r)); 1083 if (type == SYS_RES_MEMORY) { 1084 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1085 rman_set_virtual(r, NULL); 1086 } 1087 return (rman_deactivate_resource(r)); 1088} 1089 1090static int 1091psycho_release_resource(device_t bus, device_t child, int type, int rid, 1092 struct resource *r) 1093{ 1094 int error; 1095 1096 if (type == SYS_RES_IRQ) 1097 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1098 type, rid, r)); 1099 if (rman_get_flags(r) & RF_ACTIVE) { 1100 error = bus_deactivate_resource(child, type, rid, r); 1101 if (error) 1102 return error; 1103 } 1104 return (rman_release_resource(r)); 1105} 1106 1107static int 1108psycho_intr_pending(device_t dev, ofw_pci_intr_t intr) 1109{ 1110 struct psycho_softc *sc; 1111 u_long diag; 1112 1113 sc = device_get_softc(dev); 1114 if (!psycho_find_intrmap(sc, intr, NULL, NULL, &diag)) { 1115 device_printf(dev, "%s: mapping not found for %d\n", __func__, 1116 intr); 1117 return (0); 1118 } 1119 return (diag != 0); 1120} 1121 1122static bus_space_handle_t 1123psycho_get_bus_handle(device_t dev, int type, bus_space_handle_t childhdl, 1124 bus_space_tag_t *tag) 1125{ 1126 struct psycho_softc *sc; 1127 1128 sc = device_get_softc(dev); 1129 switch (type) { 1130 case SYS_RES_IOPORT: 1131 *tag = sc->sc_pci_iot; 1132 return (sc->sc_pci_bh[PCI_CS_IO] + childhdl); 1133 case SYS_RES_MEMORY: 1134 *tag = sc->sc_pci_memt; 1135 return (sc->sc_pci_bh[PCI_CS_MEM32] + childhdl); 1136 default: 1137 panic("%s: illegal space (%d)\n", __func__, type); 1138 } 1139} 1140 1141static phandle_t 1142psycho_get_node(device_t bus, device_t dev) 1143{ 1144 struct psycho_softc *sc; 1145 1146 sc = device_get_softc(bus); 1147 /* We only have one child, the PCI bus, which needs our own node. */ 1148 return (sc->sc_node); 1149} 1150 1151static void 1152psycho_adjust_busrange(device_t dev, u_int subbus) 1153{ 1154 struct psycho_softc *sc; 1155 1156 sc = device_get_softc(dev); 1157 /* If necessary, adjust the subordinate bus number register. */ 1158 if (subbus > sc->sc_pci_subbus) { 1159#ifdef PSYCHO_DEBUG 1160 device_printf(dev, 1161 "adjusting secondary bus number from %d to %d\n", 1162 sc->sc_pci_subbus, subbus); 1163#endif 1164 sc->sc_pci_subbus = subbus; 1165 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, 1166 PCSR_SUBBUS, subbus, 1); 1167 } 1168} 1169 1170static bus_space_tag_t 1171psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1172{ 1173 bus_space_tag_t bt; 1174 1175 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1176 M_NOWAIT | M_ZERO); 1177 if (bt == NULL) 1178 panic("%s: out of memory", __func__); 1179 1180 bt->bst_cookie = sc; 1181 bt->bst_parent = sc->sc_bustag; 1182 bt->bst_type = type; 1183 return (bt); 1184} 1185