psycho.c revision 152696
1/*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: head/sys/sparc64/pci/psycho.c 152696 2005-11-22 21:34:26Z marius $"); 34 35/* 36 * Support for `Psycho' and `Psycho+' UPA to PCI bridge and 37 * UltraSPARC IIi and IIe `Sabre' PCI controllers 38 */ 39 40#include "opt_ofw_pci.h" 41#include "opt_psycho.h" 42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/bus.h> 46#include <sys/kdb.h> 47#include <sys/kernel.h> 48#include <sys/module.h> 49#include <sys/malloc.h> 50#include <sys/pcpu.h> 51 52#include <dev/ofw/ofw_bus.h> 53#include <dev/ofw/ofw_pci.h> 54#include <dev/ofw/openfirm.h> 55 56#include <machine/bus.h> 57#include <machine/bus_private.h> 58#include <machine/iommureg.h> 59#include <machine/bus_common.h> 60#include <machine/nexusvar.h> 61#include <machine/ofw_bus.h> 62#include <machine/ofw_upa.h> 63#include <machine/resource.h> 64 65#include <sys/rman.h> 66 67#include <machine/iommuvar.h> 68 69#include <dev/pci/pcivar.h> 70 71#include <sparc64/pci/ofw_pci.h> 72#include <sparc64/pci/psychoreg.h> 73#include <sparc64/pci/psychovar.h> 74 75#include "pcib_if.h" 76 77static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *, 78 const char *); 79static const struct psycho_desc *psycho_get_desc(phandle_t, const char *); 80static void psycho_set_intr(struct psycho_softc *, int, device_t, bus_addr_t, 81 int, driver_intr_t); 82static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *, 83 bus_addr_t *, u_long *); 84static void psycho_intr_stub(void *); 85static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 86 87/* Interrupt handlers */ 88static void psycho_ue(void *); 89static void psycho_ce(void *); 90static void psycho_bus_a(void *); 91static void psycho_bus_b(void *); 92static void psycho_powerfail(void *); 93#ifdef PSYCHO_MAP_WAKEUP 94static void psycho_wakeup(void *); 95#endif 96 97/* IOMMU support */ 98static void psycho_iommu_init(struct psycho_softc *, int); 99 100/* 101 * Methods 102 */ 103static device_probe_t psycho_probe; 104static device_attach_t psycho_attach; 105static bus_read_ivar_t psycho_read_ivar; 106static bus_setup_intr_t psycho_setup_intr; 107static bus_teardown_intr_t psycho_teardown_intr; 108static bus_alloc_resource_t psycho_alloc_resource; 109static bus_activate_resource_t psycho_activate_resource; 110static bus_deactivate_resource_t psycho_deactivate_resource; 111static bus_release_resource_t psycho_release_resource; 112static pcib_maxslots_t psycho_maxslots; 113static pcib_read_config_t psycho_read_config; 114static pcib_write_config_t psycho_write_config; 115static pcib_route_interrupt_t psycho_route_interrupt; 116static ofw_pci_intr_pending_t psycho_intr_pending; 117static ofw_pci_get_bus_handle_t psycho_get_bus_handle; 118static ofw_bus_get_node_t psycho_get_node; 119static ofw_pci_adjust_busrange_t psycho_adjust_busrange; 120 121static device_method_t psycho_methods[] = { 122 /* Device interface */ 123 DEVMETHOD(device_probe, psycho_probe), 124 DEVMETHOD(device_attach, psycho_attach), 125 126 /* Bus interface */ 127 DEVMETHOD(bus_print_child, bus_generic_print_child), 128 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 129 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 130 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 131 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 132 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 133 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 134 DEVMETHOD(bus_release_resource, psycho_release_resource), 135 136 /* pcib interface */ 137 DEVMETHOD(pcib_maxslots, psycho_maxslots), 138 DEVMETHOD(pcib_read_config, psycho_read_config), 139 DEVMETHOD(pcib_write_config, psycho_write_config), 140 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 141 142 /* ofw_bus interface */ 143 DEVMETHOD(ofw_bus_get_node, psycho_get_node), 144 145 /* ofw_pci interface */ 146 DEVMETHOD(ofw_pci_intr_pending, psycho_intr_pending), 147 DEVMETHOD(ofw_pci_get_bus_handle, psycho_get_bus_handle), 148 DEVMETHOD(ofw_pci_adjust_busrange, psycho_adjust_busrange), 149 150 { 0, 0 } 151}; 152 153static driver_t psycho_driver = { 154 "pcib", 155 psycho_methods, 156 sizeof(struct psycho_softc), 157}; 158 159static devclass_t psycho_devclass; 160 161DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 162 163SLIST_HEAD(, psycho_softc) psycho_softcs = 164 SLIST_HEAD_INITIALIZER(psycho_softcs); 165 166struct psycho_clr { 167 struct psycho_softc *pci_sc; 168 bus_addr_t pci_clr; /* clear register */ 169 driver_intr_t *pci_handler; /* handler to call */ 170 void *pci_arg; /* argument for the handler */ 171 void *pci_cookie; /* parent bus int. cookie */ 172}; 173 174#define PSYCHO_READ8(sc, off) \ 175 bus_space_read_8((sc)->sc_bustag, (sc)->sc_bushandle, (off)) 176#define PSYCHO_WRITE8(sc, off, v) \ 177 bus_space_write_8((sc)->sc_bustag, (sc)->sc_bushandle, (off), (v)) 178#define PCICTL_READ8(sc, off) \ 179 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 180#define PCICTL_WRITE8(sc, off, v) \ 181 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 182 183/* 184 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 185 * single PCI bus and does not have a streaming buffer. It often has an APB 186 * (advanced PCI bridge) connected to it, which was designed specifically for 187 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 188 * appears as two "Simba"'s underneath the Sabre. 189 * 190 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA bus 191 * and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while 192 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 193 * will usually find a "Psycho+" since I don't think the original "Psycho" 194 * ever shipped, and if it did it would be in the U30. 195 * 196 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are 197 * both part of the same IC, they only have a single register space. As such, 198 * they need to be configured together, even though the autoconfiguration will 199 * attach them separately. 200 * 201 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often 202 * as pci1 and pci2, although they have been implemented with other PCI bus 203 * numbers on some machines. 204 * 205 * On UltraII machines, there can be any number of "Psycho+" ICs, each 206 * providing two PCI buses. 207 */ 208#ifdef DEBUGGER_ON_POWERFAIL 209#define PSYCHO_PWRFAIL_INT_FLAGS INTR_FAST 210#else 211#define PSYCHO_PWRFAIL_INT_FLAGS 0 212#endif 213 214#define OFW_PCI_TYPE "pci" 215 216struct psycho_desc { 217 const char *pd_string; 218 int pd_mode; 219 const char *pd_name; 220}; 221 222static const struct psycho_desc psycho_compats[] = { 223 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 224 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre (US-IIi) compatible" }, 225 { "pci108e,a001", PSYCHO_MODE_SABRE, "Sabre (US-IIe) compatible" }, 226 { NULL, 0, NULL } 227}; 228 229static const struct psycho_desc psycho_models[] = { 230 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 231 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 232 { NULL, 0, NULL } 233}; 234 235static const struct psycho_desc * 236psycho_find_desc(const struct psycho_desc *table, const char *string) 237{ 238 const struct psycho_desc *desc; 239 240 for (desc = table; desc->pd_string != NULL; desc++) { 241 if (strcmp(desc->pd_string, string) == 0) 242 return (desc); 243 } 244 return (NULL); 245} 246 247static const struct psycho_desc * 248psycho_get_desc(phandle_t node, const char *model) 249{ 250 const struct psycho_desc *rv; 251 char compat[32]; 252 253 rv = NULL; 254 if (model != NULL) 255 rv = psycho_find_desc(psycho_models, model); 256 if (rv == NULL && 257 OF_getprop(node, "compatible", compat, sizeof(compat)) != -1) 258 rv = psycho_find_desc(psycho_compats, compat); 259 return (rv); 260} 261 262static int 263psycho_probe(device_t dev) 264{ 265 const char *dtype; 266 267 dtype = nexus_get_device_type(dev); 268 if (nexus_get_reg(dev) != NULL && dtype != NULL && 269 strcmp(dtype, OFW_PCI_TYPE) == 0 && 270 psycho_get_desc(nexus_get_node(dev), 271 nexus_get_model(dev)) != NULL) { 272 device_set_desc(dev, "U2P UPA-PCI bridge"); 273 return (0); 274 } 275 276 return (ENXIO); 277} 278 279static int 280psycho_attach(device_t dev) 281{ 282 struct psycho_softc *sc; 283 struct psycho_softc *osc = NULL; 284 struct psycho_softc *asc; 285 struct upa_regs *reg; 286 const struct psycho_desc *desc; 287 phandle_t node; 288 uint64_t csr; 289 u_long mlen; 290 int psycho_br[2]; 291 int n, i, nreg, rid; 292#ifdef PSYCHO_DEBUG 293 bus_addr_t map, clr; 294 uint64_t mr; 295#endif 296 297 node = nexus_get_node(dev); 298 sc = device_get_softc(dev); 299 desc = psycho_get_desc(node, nexus_get_model(dev)); 300 301 sc->sc_node = node; 302 sc->sc_dev = dev; 303 sc->sc_dmatag = nexus_get_dmatag(dev); 304 sc->sc_mode = desc->pd_mode; 305 306 /* 307 * The Psycho gets three register banks: 308 * (0) per-PBM configuration and status registers 309 * (1) per-PBM PCI configuration space, containing only the 310 * PBM 256-byte PCI header 311 * (2) the shared Psycho configuration registers 312 */ 313 reg = nexus_get_reg(dev); 314 nreg = nexus_get_nreg(dev); 315 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 316 if (nreg <= 2) 317 panic("%s: %d not enough registers", __func__, nreg); 318 sc->sc_basepaddr = (vm_paddr_t)UPA_REG_PHYS(®[2]); 319 mlen = UPA_REG_SIZE(®[2]); 320 sc->sc_pcictl = UPA_REG_PHYS(®[0]) - sc->sc_basepaddr; 321 switch (sc->sc_pcictl) { 322 case PSR_PCICTL0: 323 sc->sc_half = 0; 324 break; 325 case PSR_PCICTL1: 326 sc->sc_half = 1; 327 break; 328 default: 329 panic("%s: bogus PCI control register location", 330 __func__); 331 } 332 } else { 333 if (nreg <= 0) 334 panic("%s: %d not enough registers", __func__, nreg); 335 sc->sc_basepaddr = (vm_paddr_t)UPA_REG_PHYS(®[0]); 336 mlen = UPA_REG_SIZE(reg); 337 sc->sc_pcictl = PSR_PCICTL0; 338 sc->sc_half = 0; 339 } 340 341 /* 342 * Match other Psycho's that are already configured against 343 * the base physical address. This will be the same for a 344 * pair of devices that share register space. 345 */ 346 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 347 if (asc->sc_basepaddr == sc->sc_basepaddr) { 348 /* Found partner. */ 349 osc = asc; 350 break; 351 } 352 } 353 354 if (osc == NULL) { 355 rid = 0; 356 sc->sc_mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 357 sc->sc_basepaddr, sc->sc_basepaddr + mlen - 1, mlen, 358 RF_ACTIVE); 359 if (sc->sc_mem_res == NULL || 360 rman_get_start(sc->sc_mem_res) != sc->sc_basepaddr) 361 panic("%s: could not allocate device memory", __func__); 362 sc->sc_bustag = rman_get_bustag(sc->sc_mem_res); 363 sc->sc_bushandle = rman_get_bushandle(sc->sc_mem_res); 364 } else { 365 /* 366 * There's another Psycho using the same register space. 367 * Copy the relevant stuff. 368 */ 369 sc->sc_mem_res = NULL; 370 sc->sc_bustag = osc->sc_bustag; 371 sc->sc_bushandle = osc->sc_bushandle; 372 } 373 csr = PSYCHO_READ8(sc, PSR_CS); 374 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 375 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 376 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << INTMAP_IGN_SHIFT; 377 378 device_printf(dev, "%s, impl %d, version %d, ign %#x, bus %c\n", 379 desc->pd_name, (int)PSYCHO_GCSR_IMPL(csr), 380 (int)PSYCHO_GCSR_VERS(csr), sc->sc_ign, 'A' + sc->sc_half); 381 382 /* Setup the PCI control register. */ 383 csr = PCICTL_READ8(sc, PCR_CS); 384 csr |= PCICTL_MRLM | PCICTL_ARB_PARK | PCICTL_ERRINTEN | PCICTL_4ENABLE; 385 csr &= ~(PCICTL_SERR | PCICTL_CPU_PRIO | PCICTL_ARB_PRIO | 386 PCICTL_RTRYWAIT); 387 PCICTL_WRITE8(sc, PCR_CS, csr); 388 389 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 390 /* Use the PROM preset for now. */ 391 csr = PCICTL_READ8(sc, PCR_TAS); 392 if (csr == 0) 393 panic("%s: Sabre TAS not initialized.", __func__); 394 sc->sc_dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT; 395 } else 396 sc->sc_dvmabase = -1; 397 398 /* Initialize memory and I/O rmans. */ 399 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 400 sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports"; 401 if (rman_init(&sc->sc_pci_io_rman) != 0 || 402 rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0) 403 panic("%s: failed to set up I/O rman", __func__); 404 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 405 sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory"; 406 if (rman_init(&sc->sc_pci_mem_rman) != 0 || 407 rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 408 panic("%s: failed to set up memory rman", __func__); 409 410 sc->sc_nrange = OF_getprop_alloc(node, "ranges", sizeof(*sc->sc_range), 411 (void **)&sc->sc_range); 412 if (sc->sc_nrange == -1) 413 panic("%s: could not get Psycho ranges", __func__); 414 /* 415 * Find the addresses of the various bus spaces. 416 * There should not be multiple ones of one kind. 417 * The physical start addresses of the ranges are the configuration, 418 * memory and I/O handles. 419 */ 420 for (n = 0; n < sc->sc_nrange; n++) { 421 i = UPA_RANGE_CS(&sc->sc_range[n]); 422 if (sc->sc_pci_bh[i] != 0) 423 panic("%s: duplicate range for space %d", __func__, i); 424 sc->sc_pci_bh[i] = UPA_RANGE_PHYS(&sc->sc_range[n]); 425 } 426 /* 427 * Check that all needed handles are present. The PCI_CS_MEM64 one is 428 * not currently used. 429 */ 430 for (n = 0; n < 3; n++) { 431 if (sc->sc_pci_bh[n] == 0) 432 panic("%s: range %d missing", __func__, n); 433 } 434 435 /* Register the softc, this is needed for paired Psychos. */ 436 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 437 438 /* 439 * If we're a Sabre or the first of a pair of Psycho's to arrive here, 440 * start up the IOMMU. 441 */ 442 if (osc == NULL) { 443 /* 444 * Establish handlers for interesting interrupts... 445 * 446 * XXX We need to remember these and remove this to support 447 * hotplug on the UPA/FHC bus. 448 * 449 * XXX Not all controllers have these, but installing them 450 * is better than trying to sort through this mess. 451 */ 452 psycho_set_intr(sc, 0, dev, PSR_UE_INT_MAP, INTR_FAST, 453 psycho_ue); 454 psycho_set_intr(sc, 1, dev, PSR_CE_INT_MAP, 0, psycho_ce); 455 psycho_set_intr(sc, 2, dev, PSR_PCIAERR_INT_MAP, INTR_FAST, 456 psycho_bus_a); 457 psycho_set_intr(sc, 4, dev, PSR_POWER_INT_MAP, 458 PSYCHO_PWRFAIL_INT_FLAGS, psycho_powerfail); 459 /* Psycho-specific initialization */ 460 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 461 /* 462 * Sabres do not have the following two interrupts. 463 */ 464 psycho_set_intr(sc, 3, dev, PSR_PCIBERR_INT_MAP, 465 INTR_FAST, psycho_bus_b); 466#ifdef PSYCHO_MAP_WAKEUP 467 /* 468 * psycho_wakeup() doesn't do anything useful right 469 * now. 470 */ 471 psycho_set_intr(sc, 5, dev, PSR_PWRMGT_INT_MAP, 0, 472 psycho_wakeup); 473#endif /* PSYCHO_MAP_WAKEUP */ 474 475 /* Initialize the counter-timer. */ 476 sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, 477 PSR_TC0); 478 } 479 480 /* 481 * Setup IOMMU and PCI configuration if we're the first 482 * of a pair of Psycho's to arrive here. 483 * 484 * We should calculate a TSB size based on amount of RAM 485 * and number of bus controllers and number and type of 486 * child devices. 487 * 488 * For the moment, 32KB should be more than enough. 489 */ 490 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 491 M_NOWAIT); 492 if (sc->sc_is == NULL) 493 panic("%s: malloc iommu_state failed", __func__); 494 sc->sc_is->is_sb[0] = 0; 495 sc->sc_is->is_sb[1] = 0; 496 if (OF_getproplen(node, "no-streaming-cache") < 0) 497 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 498 psycho_iommu_init(sc, 3); 499 } else { 500 /* Just copy IOMMU state, config tag and address */ 501 sc->sc_is = osc->sc_is; 502 if (OF_getproplen(node, "no-streaming-cache") < 0) 503 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 504 iommu_reset(sc->sc_is); 505 } 506 507 /* Allocate our tags. */ 508 sc->sc_pci_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 509 sc->sc_pci_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 510 sc->sc_pci_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 511 if (bus_dma_tag_create(sc->sc_dmatag, 8, 1, 0, 0x3ffffffff, 512 NULL, NULL, 0x3ffffffff, 0xff, 0xffffffff, 0, NULL, NULL, 513 &sc->sc_pci_dmat) != 0) 514 panic("%s: bus_dma_tag_create failed", __func__); 515 /* Customize the tag. */ 516 sc->sc_pci_dmat->dt_cookie = sc->sc_is; 517 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 518 /* XXX: register as root DMA tag (kludge). */ 519 sparc64_root_dma_tag = sc->sc_pci_dmat; 520 521#ifdef PSYCHO_DEBUG 522 /* 523 * Enable all interrupts and clear all interrupt states. 524 * This aids the debugging of interrupt routing problems. 525 */ 526 for (map = PSR_PCIA0_INT_MAP, clr = PSR_PCIA0_INT_CLR, n = 0; 527 map <= PSR_PCIB3_INT_MAP; map += 8, clr += 32, n++) { 528 mr = PSYCHO_READ8(sc, map); 529 device_printf(dev, "intr map (pci) %d: %#lx\n", n, (u_long)mr); 530 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 531 for (i = 0; i < 4; i++) 532 PCICTL_WRITE8(sc, clr + i * 8, 0); 533 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 534 } 535 for (map = PSR_SCSI_INT_MAP, clr = PSR_SCSI_INT_CLR, n = 0; 536 map <= PSR_SERIAL_INT_MAP; map += 8, clr += 8, n++) { 537 mr = PSYCHO_READ8(sc, map); 538 device_printf(dev, "intr map (obio) %d: %#lx, clr: %#lx\n", n, 539 (u_long)mr, (u_long)clr); 540 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 541 PSYCHO_WRITE8(sc, clr, 0); 542 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 543 } 544#endif /* PSYCHO_DEBUG */ 545 546 /* 547 * Get the bus range from the firmware; it is used solely for obtaining 548 * the inital bus number, and cannot be trusted on all machines. 549 */ 550 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br)); 551 if (n == -1) 552 panic("%s: could not get Psycho bus-range", __func__); 553 if (n != sizeof(psycho_br)) 554 panic("%s: broken Psycho bus-range (%d)", __func__, n); 555 556 sc->sc_pci_secbus = sc->sc_pci_subbus = ofw_pci_alloc_busno(node); 557 /* 558 * Program the bus range registers. 559 * NOTE: for the Psycho, the second write changes the bus number the 560 * Psycho itself uses for it's configuration space, so these 561 * writes must be kept in this order! 562 * The Sabre always uses bus 0, but there only can be one Sabre per 563 * machine. 564 */ 565 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SUBBUS, 566 sc->sc_pci_subbus, 1); 567 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SECBUS, 568 sc->sc_pci_secbus, 1); 569 570 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 571 572 device_add_child(dev, "pci", sc->sc_pci_secbus); 573 return (bus_generic_attach(dev)); 574} 575 576static void 577psycho_set_intr(struct psycho_softc *sc, int index, device_t dev, 578 bus_addr_t map, int iflags, driver_intr_t handler) 579{ 580 int rid, vec; 581 uint64_t mr; 582 583 mr = PSYCHO_READ8(sc, map); 584 vec = INTVEC(mr); 585 sc->sc_irq_res[index] = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 586 vec, vec, 1, RF_ACTIVE); 587 if (sc->sc_irq_res[index] == NULL) 588 panic("%s: failed to get interrupt", __func__); 589 bus_setup_intr(dev, sc->sc_irq_res[index], INTR_TYPE_MISC | iflags, 590 handler, sc, &sc->sc_ihand[index]); 591 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 592} 593 594static int 595psycho_find_intrmap(struct psycho_softc *sc, int ino, bus_addr_t *intrmapptr, 596 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 597{ 598 bus_addr_t intrmap, intrclr; 599 uint64_t im; 600 u_long diag; 601 int found; 602 603 found = 0; 604 /* Hunt thru obio first */ 605 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 606 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 607 intrmap <= PSR_SERIAL_INT_MAP; intrmap += 8, intrclr += 8, 608 diag >>= 2) { 609 im = PSYCHO_READ8(sc, intrmap); 610 if (INTINO(im) == ino) { 611 diag &= 2; 612 found = 1; 613 break; 614 } 615 } 616 617 if (!found) { 618 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 619 /* Now do PCI interrupts */ 620 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 621 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 622 diag >>= 8) { 623 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 624 (intrmap == PSR_PCIA2_INT_MAP || 625 intrmap == PSR_PCIA3_INT_MAP)) 626 continue; 627 im = PSYCHO_READ8(sc, intrmap); 628 if (((im ^ ino) & 0x3c) == 0) { 629 intrclr += 8 * (ino & 3); 630 diag = (diag >> ((ino & 3) * 2)) & 2; 631 found = 1; 632 break; 633 } 634 } 635 } 636 if (intrmapptr != NULL) 637 *intrmapptr = intrmap; 638 if (intrclrptr != NULL) 639 *intrclrptr = intrclr; 640 if (intrdiagptr != NULL) 641 *intrdiagptr = diag; 642 return (found); 643} 644 645/* 646 * Interrupt handlers 647 */ 648static void 649psycho_ue(void *arg) 650{ 651 struct psycho_softc *sc = arg; 652 uint64_t afar, afsr; 653 654 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 655 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 656 /* 657 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 658 * the AFAR to be set to the physical address of the TTE entry that 659 * was invalid/write protected. Call into the iommu code to have 660 * them decoded to virtual IO addresses. 661 */ 662 if ((afsr & UEAFSR_P_DTE) != 0) 663 iommu_decode_fault(sc->sc_is, afar); 664 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx", 665 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 666} 667 668static void 669psycho_ce(void *arg) 670{ 671 struct psycho_softc *sc = arg; 672 uint64_t afar, afsr; 673 674 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 675 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 676 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx " 677 "AFSR %#lx\n", (u_long)afar, (u_long)afsr); 678 /* Clear the error bits that we caught. */ 679 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr & CEAFSR_ERRMASK); 680 PSYCHO_WRITE8(sc, PSR_CE_INT_CLR, 0); 681} 682 683static void 684psycho_bus_a(void *arg) 685{ 686 struct psycho_softc *sc = arg; 687 uint64_t afar, afsr; 688 689 afar = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFA); 690 afsr = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFS); 691 panic("%s: PCI bus A error AFAR %#lx AFSR %#lx", 692 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 693} 694 695static void 696psycho_bus_b(void *arg) 697{ 698 struct psycho_softc *sc = arg; 699 uint64_t afar, afsr; 700 701 afar = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFA); 702 afsr = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFS); 703 panic("%s: PCI bus B error AFAR %#lx AFSR %#lx", 704 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 705} 706 707static void 708psycho_powerfail(void *arg) 709{ 710 711#ifdef DEBUGGER_ON_POWERFAIL 712 struct psycho_softc *sc = arg; 713 714 kdb_enter("powerfail"); 715 PSYCHO_WRITE8(sc, PSR_POWER_INT_CLR, 0); 716#else 717 printf("Power Failure Detected: Shutting down NOW.\n"); 718 shutdown_nice(0); 719#endif 720} 721 722#ifdef PSYCHO_MAP_WAKEUP 723static void 724psycho_wakeup(void *arg) 725{ 726 struct psycho_softc *sc = arg; 727 728 PSYCHO_WRITE8(sc, PSR_PWRMGT_INT_CLR, 0); 729 /* Gee, we don't really have a framework to deal with this properly. */ 730 device_printf(sc->sc_dev, "power management wakeup\n"); 731} 732#endif /* PSYCHO_MAP_WAKEUP */ 733 734static void 735psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 736{ 737 char *name; 738 struct iommu_state *is = sc->sc_is; 739 740 /* Punch in our copies. */ 741 is->is_bustag = sc->sc_bustag; 742 is->is_bushandle = sc->sc_bushandle; 743 is->is_iommu = PSR_IOMMU; 744 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 745 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 746 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 747 is->is_dva = PSR_IOMMU_SVADIAG; 748 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 749 750 /* Give us a nice name... */ 751 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 752 if (name == 0) 753 panic("%s: could not malloc iommu name", __func__); 754 snprintf(name, 32, "%s dvma", device_get_nameunit(sc->sc_dev)); 755 756 iommu_init(name, is, tsbsize, sc->sc_dvmabase, 0); 757} 758 759static int 760psycho_maxslots(device_t dev) 761{ 762 763 /* XXX: is this correct? */ 764 return (PCI_SLOTMAX); 765} 766 767static uint32_t 768psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 769 int width) 770{ 771 struct psycho_softc *sc; 772 bus_space_handle_t bh; 773 u_long offset = 0; 774 uint8_t byte; 775 uint16_t shrt; 776 uint32_t wrd; 777 uint32_t r; 778 int i; 779 780 sc = device_get_softc(dev); 781 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 782 bh = sc->sc_pci_bh[PCI_CS_CONFIG]; 783 switch (width) { 784 case 1: 785 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 786 r = byte; 787 break; 788 case 2: 789 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 790 r = shrt; 791 break; 792 case 4: 793 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 794 r = wrd; 795 break; 796 default: 797 panic("%s: bad width", __func__); 798 } 799 800 if (i) { 801#ifdef PSYCHO_DEBUG 802 printf("Psycho read data error reading: %d.%d.%d: 0x%x\n", 803 bus, slot, func, reg); 804#endif 805 r = -1; 806 } 807 return (r); 808} 809 810static void 811psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 812 uint32_t val, int width) 813{ 814 struct psycho_softc *sc; 815 bus_space_handle_t bh; 816 u_long offset = 0; 817 818 sc = device_get_softc(dev); 819 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 820 bh = sc->sc_pci_bh[PCI_CS_CONFIG]; 821 switch (width) { 822 case 1: 823 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 824 break; 825 case 2: 826 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 827 break; 828 case 4: 829 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 830 break; 831 default: 832 panic("%s: bad width", __func__); 833 } 834} 835 836static int 837psycho_route_interrupt(device_t bridge, device_t dev, int pin) 838{ 839 struct psycho_softc *sc; 840 struct ofw_pci_register reg; 841 bus_addr_t intrmap; 842 phandle_t node = ofw_bus_get_node(dev); 843 ofw_pci_intr_t pintr, mintr; 844 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 845 846 sc = device_get_softc(bridge); 847 pintr = pin; 848 if (ofw_bus_lookup_imap(node, &sc->sc_pci_iinfo, ®, sizeof(reg), 849 &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) 850 return (mintr); 851 /* 852 * If this is outside of the range for an intpin, it's likely a full 853 * INO, and no mapping is required at all; this happens on the U30, 854 * where there's no interrupt map at the Psycho node. Fortunately, 855 * there seem to be no INOs in the intpin range on this boxen, so 856 * this easy heuristics will do. 857 */ 858 if (pin > 4) 859 return (pin); 860 /* 861 * Guess the INO; we always assume that this is a non-OBIO 862 * device, and that pin is a "real" intpin number. Determine 863 * the mapping register to be used by the slot number. 864 * We only need to do this on E450s, it seems; here, the slot numbers 865 * for bus A are one-based, while those for bus B seemingly have an 866 * offset of 2 (hence the factor of 3 below). 867 */ 868 intrmap = PSR_PCIA0_INT_MAP + 869 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half); 870 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1; 871 device_printf(bridge, "guessing interrupt %d for device %d/%d pin %d\n", 872 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin); 873 return (mintr); 874} 875 876static int 877psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 878{ 879 struct psycho_softc *sc; 880 881 sc = device_get_softc(dev); 882 switch (which) { 883 case PCIB_IVAR_BUS: 884 *result = sc->sc_pci_secbus; 885 return (0); 886 } 887 return (ENOENT); 888} 889 890/* Write to the correct clr register, and call the actual handler. */ 891static void 892psycho_intr_stub(void *arg) 893{ 894 struct psycho_clr *pc = arg; 895 896 pc->pci_handler(pc->pci_arg); 897 PSYCHO_WRITE8(pc->pci_sc, pc->pci_clr, 0); 898} 899 900static int 901psycho_setup_intr(device_t dev, device_t child, struct resource *ires, 902 int flags, driver_intr_t *intr, void *arg, void **cookiep) 903{ 904 struct psycho_softc *sc; 905 struct psycho_clr *pc; 906 bus_addr_t intrmapptr, intrclrptr; 907 long vec = rman_get_start(ires); 908 uint64_t mr; 909 int ino, error; 910 911 sc = device_get_softc(dev); 912 pc = (struct psycho_clr *)malloc(sizeof(*pc), M_DEVBUF, M_NOWAIT); 913 if (pc == NULL) 914 return (0); 915 916 /* 917 * Hunt through all the interrupt mapping regs to look for our 918 * interrupt vector. 919 * 920 * XXX We only compare INOs rather than IGNs since the firmware may 921 * not provide the IGN and the IGN is constant for all devices on that 922 * PCI controller. This could cause problems for the FFB/external 923 * interrupt which has a full vector that can be set arbitrarily. 924 */ 925 ino = INTINO(vec); 926 927 if (!psycho_find_intrmap(sc, ino, &intrmapptr, &intrclrptr, NULL)) { 928 device_printf(dev, "Cannot find interrupt vector %lx\n", vec); 929 free(pc, M_DEVBUF); 930 return (0); 931 } 932 933#ifdef PSYCHO_DEBUG 934 device_printf(dev, "%s: INO %d, map %#lx, clr %#lx\n", __func__, ino, 935 (u_long)intrmapptr, (u_long)intrclrptr); 936#endif 937 pc->pci_sc = sc; 938 pc->pci_arg = arg; 939 pc->pci_handler = intr; 940 pc->pci_clr = intrclrptr; 941 /* Disable the interrupt while we fiddle with it */ 942 mr = PSYCHO_READ8(sc, intrmapptr); 943 PSYCHO_WRITE8(sc, intrmapptr, mr & ~INTMAP_V); 944 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 945 psycho_intr_stub, pc, cookiep); 946 if (error != 0) { 947 free(pc, M_DEVBUF); 948 return (error); 949 } 950 pc->pci_cookie = *cookiep; 951 *cookiep = pc; 952 953 /* 954 * Clear the interrupt, it might have been triggered before it was 955 * set up. 956 */ 957 PSYCHO_WRITE8(sc, intrclrptr, 0); 958 /* 959 * Enable the interrupt and program the target module now we have the 960 * handler installed. 961 */ 962 PSYCHO_WRITE8(sc, intrmapptr, INTMAP_ENABLE(mr, PCPU_GET(mid))); 963 return (error); 964} 965 966static int 967psycho_teardown_intr(device_t dev, device_t child, struct resource *vec, 968 void *cookie) 969{ 970 struct psycho_clr *pc = cookie; 971 int error; 972 973 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 974 pc->pci_cookie); 975 /* 976 * Don't disable the interrupt for now, so that stray interupts get 977 * detected... 978 */ 979 if (error != 0) 980 free(pc, M_DEVBUF); 981 return (error); 982} 983 984static struct resource * 985psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 986 u_long start, u_long end, u_long count, u_int flags) 987{ 988 struct psycho_softc *sc; 989 struct resource *rv; 990 struct rman *rm; 991 bus_space_tag_t bt; 992 bus_space_handle_t bh; 993 int needactivate = flags & RF_ACTIVE; 994 995 flags &= ~RF_ACTIVE; 996 997 sc = device_get_softc(bus); 998 if (type == SYS_RES_IRQ) { 999 /* 1000 * XXX: Don't accept blank ranges for now, only single 1001 * interrupts. The other case should not happen with the 1002 * MI PCI code... 1003 * XXX: This may return a resource that is out of the 1004 * range that was specified. Is this correct...? 1005 */ 1006 if (start != end) 1007 panic("%s: XXX: interrupt range", __func__); 1008 start = end |= sc->sc_ign; 1009 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, 1010 rid, start, end, count, flags)); 1011 } 1012 switch (type) { 1013 case SYS_RES_MEMORY: 1014 rm = &sc->sc_pci_mem_rman; 1015 bt = sc->sc_pci_memt; 1016 bh = sc->sc_pci_bh[PCI_CS_MEM32]; 1017 break; 1018 case SYS_RES_IOPORT: 1019 rm = &sc->sc_pci_io_rman; 1020 bt = sc->sc_pci_iot; 1021 bh = sc->sc_pci_bh[PCI_CS_IO]; 1022 break; 1023 default: 1024 return (NULL); 1025 } 1026 1027 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1028 if (rv == NULL) 1029 return (NULL); 1030 1031 bh += rman_get_start(rv); 1032 rman_set_bustag(rv, bt); 1033 rman_set_bushandle(rv, bh); 1034 1035 if (needactivate) { 1036 if (bus_activate_resource(child, type, *rid, rv)) { 1037 rman_release_resource(rv); 1038 return (NULL); 1039 } 1040 } 1041 1042 return (rv); 1043} 1044 1045static int 1046psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1047 struct resource *r) 1048{ 1049 void *p; 1050 int error; 1051 1052 if (type == SYS_RES_IRQ) 1053 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1054 type, rid, r)); 1055 if (type == SYS_RES_MEMORY) { 1056 /* 1057 * Need to memory-map the device space, as some drivers depend 1058 * on the virtual address being set and useable. 1059 */ 1060 error = sparc64_bus_mem_map(rman_get_bustag(r), 1061 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1062 if (error != 0) 1063 return (error); 1064 rman_set_virtual(r, p); 1065 } 1066 return (rman_activate_resource(r)); 1067} 1068 1069static int 1070psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1071 struct resource *r) 1072{ 1073 1074 if (type == SYS_RES_IRQ) 1075 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1076 type, rid, r)); 1077 if (type == SYS_RES_MEMORY) { 1078 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1079 rman_set_virtual(r, NULL); 1080 } 1081 return (rman_deactivate_resource(r)); 1082} 1083 1084static int 1085psycho_release_resource(device_t bus, device_t child, int type, int rid, 1086 struct resource *r) 1087{ 1088 int error; 1089 1090 if (type == SYS_RES_IRQ) 1091 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1092 type, rid, r)); 1093 if (rman_get_flags(r) & RF_ACTIVE) { 1094 error = bus_deactivate_resource(child, type, rid, r); 1095 if (error) 1096 return error; 1097 } 1098 return (rman_release_resource(r)); 1099} 1100 1101static int 1102psycho_intr_pending(device_t dev, ofw_pci_intr_t intr) 1103{ 1104 struct psycho_softc *sc; 1105 u_long diag; 1106 1107 sc = device_get_softc(dev); 1108 if (!psycho_find_intrmap(sc, intr, NULL, NULL, &diag)) { 1109 device_printf(dev, "%s: mapping not found for %d\n", __func__, 1110 intr); 1111 return (0); 1112 } 1113 return (diag != 0); 1114} 1115 1116static bus_space_handle_t 1117psycho_get_bus_handle(device_t dev, int type, bus_space_handle_t childhdl, 1118 bus_space_tag_t *tag) 1119{ 1120 struct psycho_softc *sc; 1121 1122 sc = device_get_softc(dev); 1123 switch (type) { 1124 case SYS_RES_IOPORT: 1125 *tag = sc->sc_pci_iot; 1126 return (sc->sc_pci_bh[PCI_CS_IO] + childhdl); 1127 case SYS_RES_MEMORY: 1128 *tag = sc->sc_pci_memt; 1129 return (sc->sc_pci_bh[PCI_CS_MEM32] + childhdl); 1130 default: 1131 panic("%s: illegal space (%d)\n", __func__, type); 1132 } 1133} 1134 1135static phandle_t 1136psycho_get_node(device_t bus, device_t dev) 1137{ 1138 struct psycho_softc *sc; 1139 1140 sc = device_get_softc(bus); 1141 /* We only have one child, the PCI bus, which needs our own node. */ 1142 return (sc->sc_node); 1143} 1144 1145static void 1146psycho_adjust_busrange(device_t dev, u_int subbus) 1147{ 1148 struct psycho_softc *sc; 1149 1150 sc = device_get_softc(dev); 1151 /* If necessary, adjust the subordinate bus number register. */ 1152 if (subbus > sc->sc_pci_subbus) { 1153#ifdef PSYCHO_DEBUG 1154 device_printf(dev, 1155 "adjusting secondary bus number from %d to %d\n", 1156 sc->sc_pci_subbus, subbus); 1157#endif 1158 sc->sc_pci_subbus = subbus; 1159 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, 1160 PCSR_SUBBUS, subbus, 1); 1161 } 1162} 1163 1164static bus_space_tag_t 1165psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1166{ 1167 bus_space_tag_t bt; 1168 1169 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1170 M_NOWAIT | M_ZERO); 1171 if (bt == NULL) 1172 panic("%s: out of memory", __func__); 1173 1174 bt->bst_cookie = sc; 1175 bt->bst_parent = sc->sc_bustag; 1176 bt->bst_type = type; 1177 return (bt); 1178} 1179