psycho.c revision 131537
1/* 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 30 * 31 * $FreeBSD: head/sys/sparc64/pci/psycho.c 131537 2004-07-03 20:56:16Z imp $ 32 */ 33 34/* 35 * Support for `psycho' and `psycho+' UPA to PCI bridge and 36 * UltraSPARC IIi and IIe `sabre' PCI controllers. 37 */ 38 39#include "opt_ofw_pci.h" 40#include "opt_psycho.h" 41 42#include <sys/param.h> 43#include <sys/systm.h> 44#include <sys/bus.h> 45#include <sys/kernel.h> 46#include <sys/module.h> 47#include <sys/malloc.h> 48#include <sys/pcpu.h> 49 50#include <dev/ofw/openfirm.h> 51#include <dev/ofw/ofw_pci.h> 52 53#include <machine/bus.h> 54#include <machine/bus_private.h> 55#include <machine/iommureg.h> 56#include <machine/bus_common.h> 57#include <machine/frame.h> 58#include <machine/intr_machdep.h> 59#include <machine/nexusvar.h> 60#include <machine/ofw_bus.h> 61#include <machine/ofw_upa.h> 62#include <machine/resource.h> 63 64#include <sys/rman.h> 65 66#include <machine/iommuvar.h> 67 68#include <dev/pci/pcivar.h> 69#include <dev/pci/pcireg.h> 70 71#include <sparc64/pci/ofw_pci.h> 72#include <sparc64/pci/psychoreg.h> 73#include <sparc64/pci/psychovar.h> 74 75#include "pcib_if.h" 76 77static void psycho_set_intr(struct psycho_softc *, int, device_t, bus_addr_t, 78 int, driver_intr_t); 79static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *, 80 bus_addr_t *, u_long *); 81static void psycho_intr_stub(void *); 82static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 83 84/* Interrupt handlers */ 85static void psycho_ue(void *); 86static void psycho_ce(void *); 87static void psycho_bus_a(void *); 88static void psycho_bus_b(void *); 89static void psycho_powerfail(void *); 90#ifdef PSYCHO_MAP_WAKEUP 91static void psycho_wakeup(void *); 92#endif 93 94/* IOMMU support */ 95static void psycho_iommu_init(struct psycho_softc *, int); 96 97/* 98 * Methods. 99 */ 100static device_probe_t psycho_probe; 101static device_attach_t psycho_attach; 102static bus_read_ivar_t psycho_read_ivar; 103static bus_setup_intr_t psycho_setup_intr; 104static bus_teardown_intr_t psycho_teardown_intr; 105static bus_alloc_resource_t psycho_alloc_resource; 106static bus_activate_resource_t psycho_activate_resource; 107static bus_deactivate_resource_t psycho_deactivate_resource; 108static bus_release_resource_t psycho_release_resource; 109static pcib_maxslots_t psycho_maxslots; 110static pcib_read_config_t psycho_read_config; 111static pcib_write_config_t psycho_write_config; 112static pcib_route_interrupt_t psycho_route_interrupt; 113static ofw_pci_intr_pending_t psycho_intr_pending; 114static ofw_pci_get_bus_handle_t psycho_get_bus_handle; 115static ofw_pci_get_node_t psycho_get_node; 116static ofw_pci_adjust_busrange_t psycho_adjust_busrange; 117 118static device_method_t psycho_methods[] = { 119 /* Device interface */ 120 DEVMETHOD(device_probe, psycho_probe), 121 DEVMETHOD(device_attach, psycho_attach), 122 123 /* Bus interface */ 124 DEVMETHOD(bus_print_child, bus_generic_print_child), 125 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 126 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 127 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 128 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 129 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 130 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 131 DEVMETHOD(bus_release_resource, psycho_release_resource), 132 133 /* pcib interface */ 134 DEVMETHOD(pcib_maxslots, psycho_maxslots), 135 DEVMETHOD(pcib_read_config, psycho_read_config), 136 DEVMETHOD(pcib_write_config, psycho_write_config), 137 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 138 139 /* ofw_pci interface */ 140 DEVMETHOD(ofw_pci_intr_pending, psycho_intr_pending), 141 DEVMETHOD(ofw_pci_get_bus_handle, psycho_get_bus_handle), 142 DEVMETHOD(ofw_pci_get_node, psycho_get_node), 143 DEVMETHOD(ofw_pci_adjust_busrange, psycho_adjust_busrange), 144 145 { 0, 0 } 146}; 147 148static driver_t psycho_driver = { 149 "pcib", 150 psycho_methods, 151 sizeof(struct psycho_softc), 152}; 153 154static devclass_t psycho_devclass; 155 156DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 157 158SLIST_HEAD(, psycho_softc) psycho_softcs = 159 SLIST_HEAD_INITIALIZER(psycho_softcs); 160 161struct psycho_clr { 162 struct psycho_softc *pci_sc; 163 bus_addr_t pci_clr; /* clear register */ 164 driver_intr_t *pci_handler; /* handler to call */ 165 void *pci_arg; /* argument for the handler */ 166 void *pci_cookie; /* interrupt cookie of parent bus */ 167}; 168 169struct psycho_strayclr { 170 struct psycho_softc *psc_sc; 171 bus_addr_t psc_clr; /* clear register */ 172}; 173 174#define PSYCHO_READ8(sc, off) \ 175 bus_space_read_8((sc)->sc_bustag, (sc)->sc_bushandle, (off)) 176#define PSYCHO_WRITE8(sc, off, v) \ 177 bus_space_write_8((sc)->sc_bustag, (sc)->sc_bushandle, (off), (v)) 178#define PCICTL_READ8(sc, off) \ 179 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 180#define PCICTL_WRITE8(sc, off, v) \ 181 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 182 183/* 184 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 185 * single PCI bus and does not have a streaming buffer. It often has an APB 186 * (advanced PCI bridge) connected to it, which was designed specifically for 187 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 188 * appears as two "simba"'s underneath the sabre. 189 * 190 * "psycho" and "psycho+" are dual UPA to PCI bridges. They sit on the UPA bus 191 * and manage two PCI buses. "psycho" has two 64-bit 33MHz buses, while 192 * "psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 193 * will usually find a "psycho+" since I don't think the original "psycho" 194 * ever shipped, and if it did it would be in the U30. 195 * 196 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 197 * both part of the same IC, they only have a single register space. As such, 198 * they need to be configured together, even though the autoconfiguration will 199 * attach them separately. 200 * 201 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 202 * as pci1 and pci2, although they have been implemented with other PCI bus 203 * numbers on some machines. 204 * 205 * On UltraII machines, there can be any number of "psycho+" ICs, each 206 * providing two PCI buses. 207 */ 208#ifdef DEBUGGER_ON_POWERFAIL 209#define PSYCHO_PWRFAIL_INT_FLAGS INTR_FAST 210#else 211#define PSYCHO_PWRFAIL_INT_FLAGS 0 212#endif 213 214#define OFW_PCI_TYPE "pci" 215 216struct psycho_desc { 217 char *pd_string; 218 int pd_mode; 219 char *pd_name; 220}; 221 222static struct psycho_desc psycho_compats[] = { 223 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 224 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre (US-IIi) compatible" }, 225 { "pci108e,a001", PSYCHO_MODE_SABRE, "Sabre (US-IIe) compatible" }, 226 { NULL, 0, NULL } 227}; 228 229static struct psycho_desc psycho_models[] = { 230 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 231 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 232 { NULL, 0, NULL } 233}; 234 235static struct psycho_desc * 236psycho_find_desc(struct psycho_desc *table, char *string) 237{ 238 struct psycho_desc *desc; 239 240 for (desc = table; desc->pd_string != NULL; desc++) { 241 if (strcmp(desc->pd_string, string) == 0) 242 return (desc); 243 } 244 return (NULL); 245} 246 247static struct psycho_desc * 248psycho_get_desc(phandle_t node, char *model) 249{ 250 struct psycho_desc *rv; 251 char compat[32]; 252 253 rv = NULL; 254 if (model != NULL) 255 rv = psycho_find_desc(psycho_models, model); 256 if (rv == NULL && 257 OF_getprop(node, "compatible", compat, sizeof(compat)) != -1) 258 rv = psycho_find_desc(psycho_compats, compat); 259 return (rv); 260} 261 262static int 263psycho_probe(device_t dev) 264{ 265 phandle_t node; 266 char *dtype; 267 268 node = nexus_get_node(dev); 269 dtype = nexus_get_device_type(dev); 270 if (nexus_get_reg(dev) != NULL && dtype != NULL && 271 strcmp(dtype, OFW_PCI_TYPE) == 0 && 272 psycho_get_desc(node, nexus_get_model(dev)) != NULL) { 273 device_set_desc(dev, "U2P UPA-PCI bridge"); 274 return (0); 275 } 276 277 return (ENXIO); 278} 279 280static int 281psycho_attach(device_t dev) 282{ 283 struct psycho_softc *sc; 284 struct psycho_softc *osc = NULL; 285 struct psycho_softc *asc; 286 struct upa_regs *reg; 287 struct psycho_desc *desc; 288 phandle_t node; 289 u_int64_t csr; 290 u_long mlen; 291 int psycho_br[2]; 292 int n, i, nreg, rid; 293#ifdef PSYCHO_DEBUG 294 bus_addr_t map, clr; 295 u_int64_t mr; 296#endif 297 298 node = nexus_get_node(dev); 299 sc = device_get_softc(dev); 300 desc = psycho_get_desc(node, nexus_get_model(dev)); 301 302 sc->sc_node = node; 303 sc->sc_dev = dev; 304 sc->sc_dmatag = nexus_get_dmatag(dev); 305 sc->sc_mode = desc->pd_mode; 306 307 /* 308 * The psycho gets three register banks: 309 * (0) per-PBM configuration and status registers 310 * (1) per-PBM PCI configuration space, containing only the 311 * PBM 256-byte PCI header 312 * (2) the shared psycho configuration registers 313 */ 314 reg = nexus_get_reg(dev); 315 nreg = nexus_get_nreg(dev); 316 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 317 if (nreg <= 2) 318 panic("psycho_attach: %d not enough registers", nreg); 319 sc->sc_basepaddr = (vm_paddr_t)UPA_REG_PHYS(®[2]); 320 mlen = UPA_REG_SIZE(®[2]); 321 sc->sc_pcictl = UPA_REG_PHYS(®[0]) - sc->sc_basepaddr; 322 switch (sc->sc_pcictl) { 323 case PSR_PCICTL0: 324 sc->sc_half = 0; 325 break; 326 case PSR_PCICTL1: 327 sc->sc_half = 1; 328 break; 329 default: 330 panic("psycho_attach: bogus pci control register " 331 "location"); 332 } 333 } else { 334 if (nreg <= 0) 335 panic("psycho_attach: %d not enough registers", nreg); 336 sc->sc_basepaddr = (vm_paddr_t)UPA_REG_PHYS(®[0]); 337 mlen = UPA_REG_SIZE(reg); 338 sc->sc_pcictl = PSR_PCICTL0; 339 sc->sc_half = 0; 340 } 341 342 /* 343 * Match other psycho's that are already configured against 344 * the base physical address. This will be the same for a 345 * pair of devices that share register space. 346 */ 347 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 348 if (asc->sc_basepaddr == sc->sc_basepaddr) { 349 /* Found partner */ 350 osc = asc; 351 break; 352 } 353 } 354 355 if (osc == NULL) { 356 rid = 0; 357 sc->sc_mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 358 sc->sc_basepaddr, sc->sc_basepaddr + mlen - 1, mlen, 359 RF_ACTIVE); 360 if (sc->sc_mem_res == NULL || 361 rman_get_start(sc->sc_mem_res) != sc->sc_basepaddr) 362 panic("psycho_attach: can't allocate device memory"); 363 sc->sc_bustag = rman_get_bustag(sc->sc_mem_res); 364 sc->sc_bushandle = rman_get_bushandle(sc->sc_mem_res); 365 } else { 366 /* 367 * There's another psycho using the same register space. Copy the 368 * relevant stuff. 369 */ 370 sc->sc_mem_res = NULL; 371 sc->sc_bustag = osc->sc_bustag; 372 sc->sc_bushandle = osc->sc_bushandle; 373 } 374 csr = PSYCHO_READ8(sc, PSR_CS); 375 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 376 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 377 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 378 379 device_printf(dev, "%s, impl %d, version %d, ign %#x, bus %c\n", 380 desc->pd_name, (int)PSYCHO_GCSR_IMPL(csr), 381 (int)PSYCHO_GCSR_VERS(csr), sc->sc_ign, 'A' + sc->sc_half); 382 383 /* Setup the PCI control register. */ 384 csr = PCICTL_READ8(sc, PCR_CS); 385 csr |= PCICTL_MRLM | PCICTL_ARB_PARK | PCICTL_ERRINTEN | PCICTL_4ENABLE; 386 csr &= ~(PCICTL_SERR | PCICTL_CPU_PRIO | PCICTL_ARB_PRIO | 387 PCICTL_RTRYWAIT); 388 PCICTL_WRITE8(sc, PCR_CS, csr); 389 390 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 391 /* Use the PROM preset for now. */ 392 csr = PCICTL_READ8(sc, PCR_TAS); 393 if (csr == 0) 394 panic("psycho_attach: sabre TAS not initialized."); 395 sc->sc_dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT; 396 } else 397 sc->sc_dvmabase = -1; 398 399 /* Initialize memory and i/o rmans */ 400 sc->sc_io_rman.rm_type = RMAN_ARRAY; 401 sc->sc_io_rman.rm_descr = "Psycho PCI I/O Ports"; 402 if (rman_init(&sc->sc_io_rman) != 0 || 403 rman_manage_region(&sc->sc_io_rman, 0, PSYCHO_IO_SIZE) != 0) 404 panic("psycho_probe: failed to set up i/o rman"); 405 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 406 sc->sc_mem_rman.rm_descr = "Psycho PCI Memory"; 407 if (rman_init(&sc->sc_mem_rman) != 0 || 408 rman_manage_region(&sc->sc_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 409 panic("psycho_probe: failed to set up memory rman"); 410 411 sc->sc_nrange = OF_getprop_alloc(sc->sc_node, "ranges", 412 sizeof(*sc->sc_range), (void **)&sc->sc_range); 413 if (sc->sc_nrange == -1) 414 panic("could not get psycho ranges"); 415 /* 416 * Find the addresses of the various bus spaces. 417 * There should not be multiple ones of one kind. 418 * The physical start addresses of the ranges are the configuration, 419 * memory and IO handles. 420 */ 421 for (n = 0; n < sc->sc_nrange; n++) { 422 i = UPA_RANGE_CS(&sc->sc_range[n]); 423 if (sc->sc_bh[i] != 0) 424 panic("psycho_attach: duplicate range for space %d", i); 425 sc->sc_bh[i] = UPA_RANGE_PHYS(&sc->sc_range[n]); 426 } 427 /* 428 * Check that all needed handles are present. The PCI_CS_MEM64 one is 429 * not currently used. 430 */ 431 for (n = 0; n < 3; n++) { 432 if (sc->sc_bh[n] == 0) 433 panic("psycho_attach: range %d missing", n); 434 } 435 436 /* Register the softc, this is needed for paired psychos. */ 437 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 438 439 /* 440 * If we're a sabre or the first of a pair of psycho's to arrive here, 441 * start up the IOMMU. 442 */ 443 if (osc == NULL) { 444 /* 445 * Establish handlers for interesting interrupts.... 446 * 447 * XXX We need to remember these and remove this to support 448 * hotplug on the UPA/FHC bus. 449 * 450 * XXX Not all controllers have these, but installing them 451 * is better than trying to sort through this mess. 452 */ 453 psycho_set_intr(sc, 0, dev, PSR_UE_INT_MAP, INTR_FAST, 454 psycho_ue); 455 psycho_set_intr(sc, 1, dev, PSR_CE_INT_MAP, 0, psycho_ce); 456 psycho_set_intr(sc, 2, dev, PSR_PCIAERR_INT_MAP, INTR_FAST, 457 psycho_bus_a); 458 psycho_set_intr(sc, 4, dev, PSR_POWER_INT_MAP, 459 PSYCHO_PWRFAIL_INT_FLAGS, psycho_powerfail); 460 /* Psycho-specific initialization. */ 461 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 462 /* 463 * Sabres do not have the following two interrupts. 464 */ 465 psycho_set_intr(sc, 3, dev, PSR_PCIBERR_INT_MAP, 466 INTR_FAST, psycho_bus_b); 467#ifdef PSYCHO_MAP_WAKEUP 468 /* 469 * psycho_wakeup() doesn't do anything useful right 470 * now. 471 */ 472 psycho_set_intr(sc, 5, dev, PSR_PWRMGT_INT_MAP, 0, 473 psycho_wakeup); 474#endif /* PSYCHO_MAP_WAKEUP */ 475 476 /* Initialize the counter-timer. */ 477 sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, 478 PSR_TC0); 479 } 480 481 /* 482 * Setup IOMMU and PCI configuration if we're the first 483 * of a pair of psycho's to arrive here. 484 * 485 * We should calculate a TSB size based on amount of RAM 486 * and number of bus controllers and number and type of 487 * child devices. 488 * 489 * For the moment, 32KB should be more than enough. 490 */ 491 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 492 M_NOWAIT); 493 if (sc->sc_is == NULL) 494 panic("psycho_attach: malloc iommu_state failed"); 495 sc->sc_is->is_sb[0] = 0; 496 sc->sc_is->is_sb[1] = 0; 497 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 498 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 499 psycho_iommu_init(sc, 3); 500 } else { 501 /* Just copy IOMMU state, config tag and address */ 502 sc->sc_is = osc->sc_is; 503 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 504 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 505 iommu_reset(sc->sc_is); 506 } 507 508 /* Allocate our tags. */ 509 sc->sc_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 510 sc->sc_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 511 sc->sc_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 512 if (bus_dma_tag_create(sc->sc_dmatag, 8, 1, 0, 0x3ffffffff, NULL, NULL, 513 0x3ffffffff, 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_dmat) != 0) 514 panic("psycho_attach: bus_dma_tag_create failed"); 515 /* Customize the tag. */ 516 sc->sc_dmat->dt_cookie = sc->sc_is; 517 sc->sc_dmat->dt_mt = &iommu_dma_methods; 518 /* XXX: register as root dma tag (kludge). */ 519 sparc64_root_dma_tag = sc->sc_dmat; 520 521#ifdef PSYCHO_DEBUG 522 /* 523 * Enable all interrupts and clear all interrupt states. 524 * This aids the debugging of interrupt routing problems. 525 */ 526 for (map = PSR_PCIA0_INT_MAP, clr = PSR_PCIA0_INT_CLR, n = 0; 527 map <= PSR_PCIB3_INT_MAP; map += 8, clr += 32, n++) { 528 mr = PSYCHO_READ8(sc, map); 529 device_printf(dev, "intr map (pci) %d: %#lx\n", n, (u_long)mr); 530 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 531 for (i = 0; i < 4; i++) 532 PCICTL_WRITE8(sc, clr + i * 8, 0); 533 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 534 } 535 for (map = PSR_SCSI_INT_MAP, clr = PSR_SCSI_INT_CLR, n = 0; 536 map <= PSR_SERIAL_INT_MAP; map += 8, clr += 8, n++) { 537 mr = PSYCHO_READ8(sc, map); 538 device_printf(dev, "intr map (obio) %d: %#lx, clr: %#lx\n", n, 539 (u_long)mr, (u_long)clr); 540 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 541 PSYCHO_WRITE8(sc, clr, 0); 542 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 543 } 544#endif /* PSYCHO_DEBUG */ 545 546 /* 547 * Get the bus range from the firmware; it is used solely for obtaining 548 * the inital bus number, and cannot be trusted on all machines. 549 */ 550 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br)); 551 if (n == -1) 552 panic("could not get psycho bus-range"); 553 if (n != sizeof(psycho_br)) 554 panic("broken psycho bus-range (%d)", n); 555 556 sc->sc_secbus = sc->sc_subbus = ofw_pci_alloc_busno(sc->sc_node); 557 /* 558 * Program the bus range registers. 559 * NOTE: for the psycho, the second write changes the bus number the 560 * psycho itself uses for it's configuration space, so these 561 * writes must be kept in this order! 562 * The sabre always uses bus 0, but there only can be one sabre per 563 * machine. 564 */ 565 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SUBBUS, 566 sc->sc_subbus, 1); 567 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SECBUS, 568 sc->sc_secbus, 1); 569 570 ofw_bus_setup_iinfo(node, &sc->sc_iinfo, sizeof(ofw_pci_intr_t)); 571 572 device_add_child(dev, "pci", sc->sc_secbus); 573 return (bus_generic_attach(dev)); 574} 575 576static void 577psycho_set_intr(struct psycho_softc *sc, int index, 578 device_t dev, bus_addr_t map, int iflags, driver_intr_t handler) 579{ 580 int rid, vec; 581 u_int64_t mr; 582 583 mr = PSYCHO_READ8(sc, map); 584 vec = INTVEC(mr); 585 sc->sc_irq_res[index] = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 586 vec, vec, 1, RF_ACTIVE); 587 if (sc->sc_irq_res[index] == NULL) 588 panic("psycho_set_intr: failed to get interrupt"); 589 bus_setup_intr(dev, sc->sc_irq_res[index], INTR_TYPE_MISC | iflags, 590 handler, sc, &sc->sc_ihand[index]); 591 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 592} 593 594static int 595psycho_find_intrmap(struct psycho_softc *sc, int ino, bus_addr_t *intrmapptr, 596 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 597{ 598 bus_addr_t intrmap, intrclr; 599 u_int64_t im; 600 u_long diag; 601 int found; 602 603 found = 0; 604 /* Hunt thru obio first */ 605 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 606 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 607 intrmap <= PSR_SERIAL_INT_MAP; intrmap += 8, intrclr += 8, 608 diag >>= 2) { 609 im = PSYCHO_READ8(sc, intrmap); 610 if (INTINO(im) == ino) { 611 diag &= 2; 612 found = 1; 613 break; 614 } 615 } 616 617 if (!found) { 618 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 619 /* Now do PCI interrupts */ 620 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 621 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 622 diag >>= 8) { 623 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 624 (intrmap == PSR_PCIA2_INT_MAP || 625 intrmap == PSR_PCIA3_INT_MAP)) 626 continue; 627 im = PSYCHO_READ8(sc, intrmap); 628 if (((im ^ ino) & 0x3c) == 0) { 629 intrclr += 8 * (ino & 3); 630 diag = (diag >> ((ino & 3) * 2)) & 2; 631 found = 1; 632 break; 633 } 634 } 635 } 636 if (intrmapptr != NULL) 637 *intrmapptr = intrmap; 638 if (intrclrptr != NULL) 639 *intrclrptr = intrclr; 640 if (intrdiagptr != NULL) 641 *intrdiagptr = diag; 642 return (found); 643} 644 645/* 646 * Interrupt handlers. 647 */ 648static void 649psycho_ue(void *arg) 650{ 651 struct psycho_softc *sc = (struct psycho_softc *)arg; 652 u_int64_t afar, afsr; 653 654 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 655 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 656 /* 657 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 658 * the AFAR to be set to the physical address of the TTE entry that 659 * was invalid/write protected. Call into the iommu code to have 660 * them decoded to virtual IO addresses. 661 */ 662 if ((afsr & UEAFSR_P_DTE) != 0) 663 iommu_decode_fault(sc->sc_is, afar); 664 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx", 665 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 666} 667 668static void 669psycho_ce(void *arg) 670{ 671 struct psycho_softc *sc = (struct psycho_softc *)arg; 672 u_int64_t afar, afsr; 673 674 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 675 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 676 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx " 677 "AFSR %#lx\n", (u_long)afar, (u_long)afsr); 678 /* Clear the error bits that we caught. */ 679 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr & CEAFSR_ERRMASK); 680 PSYCHO_WRITE8(sc, PSR_CE_INT_CLR, 0); 681} 682 683static void 684psycho_bus_a(void *arg) 685{ 686 struct psycho_softc *sc = (struct psycho_softc *)arg; 687 u_int64_t afar, afsr; 688 689 afar = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFA); 690 afsr = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFS); 691 panic("%s: PCI bus A error AFAR %#lx AFSR %#lx", 692 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 693} 694 695static void 696psycho_bus_b(void *arg) 697{ 698 struct psycho_softc *sc = (struct psycho_softc *)arg; 699 u_int64_t afar, afsr; 700 701 afar = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFA); 702 afsr = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFS); 703 panic("%s: PCI bus B error AFAR %#lx AFSR %#lx", 704 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 705} 706 707static void 708psycho_powerfail(void *arg) 709{ 710 711#ifdef DEBUGGER_ON_POWERFAIL 712 struct psycho_softc *sc = (struct psycho_softc *)arg; 713 714 Debugger("powerfail"); 715 PSYCHO_WRITE8(sc, PSR_POWER_INT_CLR, 0); 716#else 717 printf("Power Failure Detected: Shutting down NOW.\n"); 718 shutdown_nice(0); 719#endif 720} 721 722#ifdef PSYCHO_MAP_WAKEUP 723static void 724psycho_wakeup(void *arg) 725{ 726 struct psycho_softc *sc = (struct psycho_softc *)arg; 727 728 PSYCHO_WRITE8(sc, PSR_PWRMGT_INT_CLR, 0); 729 /* Gee, we don't really have a framework to deal with this properly. */ 730 device_printf(sc->sc_dev, "power management wakeup\n"); 731} 732#endif /* PSYCHO_MAP_WAKEUP */ 733 734void 735psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 736{ 737 char *name; 738 struct iommu_state *is = sc->sc_is; 739 740 /* punch in our copies */ 741 is->is_bustag = sc->sc_bustag; 742 is->is_bushandle = sc->sc_bushandle; 743 is->is_iommu = PSR_IOMMU; 744 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 745 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 746 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 747 is->is_dva = PSR_IOMMU_SVADIAG; 748 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 749 750 /* give us a nice name.. */ 751 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 752 if (name == 0) 753 panic("couldn't malloc iommu name"); 754 snprintf(name, 32, "%s dvma", device_get_nameunit(sc->sc_dev)); 755 756 iommu_init(name, is, tsbsize, sc->sc_dvmabase, 0); 757} 758 759static int 760psycho_maxslots(device_t dev) 761{ 762 763 /* XXX: is this correct? */ 764 return (PCI_SLOTMAX); 765} 766 767static u_int32_t 768psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 769 int width) 770{ 771 struct psycho_softc *sc; 772 bus_space_handle_t bh; 773 u_long offset = 0; 774 u_int8_t byte; 775 u_int16_t shrt; 776 u_int32_t wrd; 777 u_int32_t r; 778 int i; 779 780 sc = (struct psycho_softc *)device_get_softc(dev); 781 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 782 bh = sc->sc_bh[PCI_CS_CONFIG]; 783 switch (width) { 784 case 1: 785 i = bus_space_peek_1(sc->sc_cfgt, bh, offset, &byte); 786 r = byte; 787 break; 788 case 2: 789 i = bus_space_peek_2(sc->sc_cfgt, bh, offset, &shrt); 790 r = shrt; 791 break; 792 case 4: 793 i = bus_space_peek_4(sc->sc_cfgt, bh, offset, &wrd); 794 r = wrd; 795 break; 796 default: 797 panic("psycho_read_config: bad width"); 798 } 799 800 if (i) { 801#ifdef PSYCHO_DEBUG 802 printf("psycho read data error reading: %d.%d.%d: 0x%x\n", 803 bus, slot, func, reg); 804#endif 805 r = -1; 806 } 807 return (r); 808} 809 810static void 811psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, 812 u_int reg, u_int32_t val, int width) 813{ 814 struct psycho_softc *sc; 815 bus_space_handle_t bh; 816 u_long offset = 0; 817 818 sc = (struct psycho_softc *)device_get_softc(dev); 819 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 820 bh = sc->sc_bh[PCI_CS_CONFIG]; 821 switch (width) { 822 case 1: 823 bus_space_write_1(sc->sc_cfgt, bh, offset, val); 824 break; 825 case 2: 826 bus_space_write_2(sc->sc_cfgt, bh, offset, val); 827 break; 828 case 4: 829 bus_space_write_4(sc->sc_cfgt, bh, offset, val); 830 break; 831 default: 832 panic("psycho_write_config: bad width"); 833 } 834} 835 836static int 837psycho_route_interrupt(device_t bridge, device_t dev, int pin) 838{ 839 struct psycho_softc *sc = device_get_softc(bridge); 840 struct ofw_pci_register reg; 841 bus_addr_t intrmap; 842 phandle_t node = ofw_pci_get_node(dev); 843 ofw_pci_intr_t pintr, mintr; 844 u_int8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 845 846 pintr = pin; 847 if (ofw_bus_lookup_imap(node, &sc->sc_iinfo, ®, sizeof(reg), 848 &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) 849 return (mintr); 850 /* 851 * If this is outside of the range for an intpin, it's likely a full 852 * INO, and no mapping is required at all; this happens on the u30, 853 * where there's no interrupt map at the psycho node. Fortunately, 854 * there seem to be no INOs in the intpin range on this boxen, so 855 * this easy heuristics will do. 856 */ 857 if (pin > 4) 858 return (pin); 859 /* 860 * Guess the INO; we always assume that this is a non-OBIO 861 * device, and that pin is a "real" intpin number. Determine 862 * the mapping register to be used by the slot number. 863 * We only need to do this on e450s, it seems; here, the slot numbers 864 * for bus A are one-based, while those for bus B seemingly have an 865 * offset of 2 (hence the factor of 3 below). 866 */ 867 intrmap = PSR_PCIA0_INT_MAP + 868 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half); 869 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1; 870 device_printf(bridge, "guessing interrupt %d for device %d/%d pin %d\n", 871 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin); 872 return (mintr); 873} 874 875static int 876psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 877{ 878 struct psycho_softc *sc; 879 880 sc = (struct psycho_softc *)device_get_softc(dev); 881 switch (which) { 882 case PCIB_IVAR_BUS: 883 *result = sc->sc_secbus; 884 return (0); 885 } 886 return (ENOENT); 887} 888 889/* Write to the correct clr register, and call the actual handler. */ 890static void 891psycho_intr_stub(void *arg) 892{ 893 struct psycho_clr *pc; 894 895 pc = (struct psycho_clr *)arg; 896 pc->pci_handler(pc->pci_arg); 897 PSYCHO_WRITE8(pc->pci_sc, pc->pci_clr, 0); 898} 899 900static int 901psycho_setup_intr(device_t dev, device_t child, 902 struct resource *ires, int flags, driver_intr_t *intr, void *arg, 903 void **cookiep) 904{ 905 struct psycho_softc *sc; 906 struct psycho_clr *pc; 907 bus_addr_t intrmapptr, intrclrptr; 908 long vec = rman_get_start(ires); 909 u_int64_t mr; 910 int ino, error; 911 912 sc = (struct psycho_softc *)device_get_softc(dev); 913 pc = (struct psycho_clr *)malloc(sizeof(*pc), M_DEVBUF, M_NOWAIT); 914 if (pc == NULL) 915 return (0); 916 917 /* 918 * Hunt through all the interrupt mapping regs to look for our 919 * interrupt vector. 920 * 921 * XXX We only compare INOs rather than IGNs since the firmware may 922 * not provide the IGN and the IGN is constant for all devices on that 923 * PCI controller. This could cause problems for the FFB/external 924 * interrupt which has a full vector that can be set arbitrarily. 925 */ 926 ino = INTINO(vec); 927 928 if (!psycho_find_intrmap(sc, ino, &intrmapptr, &intrclrptr, NULL)) { 929 device_printf(dev, "Cannot find interrupt vector %lx\n", vec); 930 free(pc, M_DEVBUF); 931 return (0); 932 } 933 934#ifdef PSYCHO_DEBUG 935 device_printf(dev, "psycho_setup_intr: INO %d, map %#lx, clr %#lx\n", 936 ino, (u_long)intrmapptr, (u_long)intrclrptr); 937#endif 938 pc->pci_sc = sc; 939 pc->pci_arg = arg; 940 pc->pci_handler = intr; 941 pc->pci_clr = intrclrptr; 942 /* Disable the interrupt while we fiddle with it */ 943 mr = PSYCHO_READ8(sc, intrmapptr); 944 PSYCHO_WRITE8(sc, intrmapptr, mr & ~INTMAP_V); 945 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 946 psycho_intr_stub, pc, cookiep); 947 if (error != 0) { 948 free(pc, M_DEVBUF); 949 return (error); 950 } 951 pc->pci_cookie = *cookiep; 952 *cookiep = pc; 953 954 /* 955 * Clear the interrupt, it might have been triggered before it was 956 * set up. 957 */ 958 PSYCHO_WRITE8(sc, intrclrptr, 0); 959 /* 960 * Enable the interrupt and program the target module now we have the 961 * handler installed. 962 */ 963 PSYCHO_WRITE8(sc, intrmapptr, INTMAP_ENABLE(mr, PCPU_GET(mid))); 964 return (error); 965} 966 967static int 968psycho_teardown_intr(device_t dev, device_t child, 969 struct resource *vec, void *cookie) 970{ 971 struct psycho_clr *pc; 972 int error; 973 974 pc = (struct psycho_clr *)cookie; 975 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 976 pc->pci_cookie); 977 /* 978 * Don't disable the interrupt for now, so that stray interupts get 979 * detected... 980 */ 981 if (error != 0) 982 free(pc, M_DEVBUF); 983 return (error); 984} 985 986static struct resource * 987psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 988 u_long start, u_long end, u_long count, u_int flags) 989{ 990 struct psycho_softc *sc; 991 struct resource *rv; 992 struct rman *rm; 993 bus_space_tag_t bt; 994 bus_space_handle_t bh; 995 int needactivate = flags & RF_ACTIVE; 996 997 flags &= ~RF_ACTIVE; 998 999 sc = (struct psycho_softc *)device_get_softc(bus); 1000 if (type == SYS_RES_IRQ) { 1001 /* 1002 * XXX: Don't accept blank ranges for now, only single 1003 * interrupts. The other case should not happen with the MI pci 1004 * code... 1005 * XXX: This may return a resource that is out of the range 1006 * that was specified. Is this correct...? 1007 */ 1008 if (start != end) 1009 panic("psycho_alloc_resource: XXX: interrupt range"); 1010 start = end |= sc->sc_ign; 1011 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, 1012 rid, start, end, count, flags)); 1013 } 1014 switch (type) { 1015 case SYS_RES_MEMORY: 1016 rm = &sc->sc_mem_rman; 1017 bt = sc->sc_memt; 1018 bh = sc->sc_bh[PCI_CS_MEM32]; 1019 break; 1020 case SYS_RES_IOPORT: 1021 rm = &sc->sc_io_rman; 1022 bt = sc->sc_iot; 1023 bh = sc->sc_bh[PCI_CS_IO]; 1024 break; 1025 default: 1026 return (NULL); 1027 } 1028 1029 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1030 if (rv == NULL) 1031 return (NULL); 1032 1033 bh += rman_get_start(rv); 1034 rman_set_bustag(rv, bt); 1035 rman_set_bushandle(rv, bh); 1036 1037 if (needactivate) { 1038 if (bus_activate_resource(child, type, *rid, rv)) { 1039 rman_release_resource(rv); 1040 return (NULL); 1041 } 1042 } 1043 1044 return (rv); 1045} 1046 1047static int 1048psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1049 struct resource *r) 1050{ 1051 void *p; 1052 int error; 1053 1054 if (type == SYS_RES_IRQ) 1055 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1056 type, rid, r)); 1057 if (type == SYS_RES_MEMORY) { 1058 /* 1059 * Need to memory-map the device space, as some drivers depend 1060 * on the virtual address being set and useable. 1061 */ 1062 error = sparc64_bus_mem_map(rman_get_bustag(r), 1063 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1064 if (error != 0) 1065 return (error); 1066 rman_set_virtual(r, p); 1067 } 1068 return (rman_activate_resource(r)); 1069} 1070 1071static int 1072psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1073 struct resource *r) 1074{ 1075 1076 if (type == SYS_RES_IRQ) 1077 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1078 type, rid, r)); 1079 if (type == SYS_RES_MEMORY) { 1080 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1081 rman_set_virtual(r, NULL); 1082 } 1083 return (rman_deactivate_resource(r)); 1084} 1085 1086static int 1087psycho_release_resource(device_t bus, device_t child, int type, int rid, 1088 struct resource *r) 1089{ 1090 int error; 1091 1092 if (type == SYS_RES_IRQ) 1093 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1094 type, rid, r)); 1095 if (rman_get_flags(r) & RF_ACTIVE) { 1096 error = bus_deactivate_resource(child, type, rid, r); 1097 if (error) 1098 return error; 1099 } 1100 return (rman_release_resource(r)); 1101} 1102 1103static int 1104psycho_intr_pending(device_t dev, ofw_pci_intr_t intr) 1105{ 1106 struct psycho_softc *sc; 1107 u_long diag; 1108 1109 sc = (struct psycho_softc *)device_get_softc(dev); 1110 if (!psycho_find_intrmap(sc, intr, NULL, NULL, &diag)) { 1111 device_printf(dev, "psycho_intr_pending: mapping not found for" 1112 " %d\n", intr); 1113 return (0); 1114 } 1115 return (diag != 0); 1116} 1117 1118static bus_space_handle_t 1119psycho_get_bus_handle(device_t dev, int type, bus_space_handle_t childhdl, 1120 bus_space_tag_t *tag) 1121{ 1122 struct psycho_softc *sc; 1123 1124 sc = (struct psycho_softc *)device_get_softc(dev); 1125 switch (type) { 1126 case SYS_RES_IOPORT: 1127 *tag = sc->sc_iot; 1128 return (sc->sc_bh[PCI_CS_IO] + childhdl); 1129 case SYS_RES_MEMORY: 1130 *tag = sc->sc_memt; 1131 return (sc->sc_bh[PCI_CS_MEM32] + childhdl); 1132 default: 1133 panic("psycho_get_bus_handle: illegal space\n"); 1134 } 1135} 1136 1137static phandle_t 1138psycho_get_node(device_t bus, device_t dev) 1139{ 1140 struct psycho_softc *sc = device_get_softc(bus); 1141 1142 /* We only have one child, the PCI bus, which needs our own node. */ 1143 return (sc->sc_node); 1144} 1145 1146static void 1147psycho_adjust_busrange(device_t dev, u_int subbus) 1148{ 1149 struct psycho_softc *sc = device_get_softc(dev); 1150 1151 /* If necessary, adjust the subordinate bus number register. */ 1152 if (subbus > sc->sc_subbus) { 1153#ifdef PSYCHO_DEBUG 1154 device_printf(dev, 1155 "adjusting secondary bus number from %d to %d\n", 1156 sc->sc_subbus, subbus); 1157#endif 1158 sc->sc_subbus = subbus; 1159 PCIB_WRITE_CONFIG(dev, sc->sc_secbus, PCS_DEVICE, PCS_FUNC, 1160 PCSR_SUBBUS, subbus, 1); 1161 } 1162} 1163 1164static bus_space_tag_t 1165psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1166{ 1167 bus_space_tag_t bt; 1168 1169 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1170 M_NOWAIT | M_ZERO); 1171 if (bt == NULL) 1172 panic("psycho_alloc_bus_tag: out of memory"); 1173 1174 bzero(bt, sizeof *bt); 1175 bt->bst_cookie = sc; 1176 bt->bst_parent = sc->sc_bustag; 1177 bt->bst_type = type; 1178 return (bt); 1179} 1180