psycho.c revision 128625
1/* 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 30 * 31 * $FreeBSD: head/sys/sparc64/pci/psycho.c 128625 2004-04-25 00:30:28Z tmm $ 32 */ 33 34/* 35 * Support for `psycho' and `psycho+' UPA to PCI bridge and 36 * UltraSPARC IIi and IIe `sabre' PCI controllers. 37 */ 38 39#include "opt_ofw_pci.h" 40#include "opt_psycho.h" 41 42#include <sys/param.h> 43#include <sys/systm.h> 44#include <sys/bus.h> 45#include <sys/kernel.h> 46#include <sys/malloc.h> 47#include <sys/pcpu.h> 48 49#include <dev/ofw/openfirm.h> 50#include <dev/ofw/ofw_pci.h> 51 52#include <machine/bus.h> 53#include <machine/bus_private.h> 54#include <machine/iommureg.h> 55#include <machine/bus_common.h> 56#include <machine/frame.h> 57#include <machine/intr_machdep.h> 58#include <machine/nexusvar.h> 59#include <machine/ofw_bus.h> 60#include <machine/ofw_upa.h> 61#include <machine/resource.h> 62#include <machine/cpu.h> 63 64#include <sys/rman.h> 65 66#include <machine/iommuvar.h> 67 68#include <dev/pci/pcivar.h> 69#include <dev/pci/pcireg.h> 70 71#include <sparc64/pci/ofw_pci.h> 72#include <sparc64/pci/psychoreg.h> 73#include <sparc64/pci/psychovar.h> 74 75#include "pcib_if.h" 76 77static void psycho_set_intr(struct psycho_softc *, int, device_t, bus_addr_t, 78 int, driver_intr_t); 79static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *, 80 bus_addr_t *, u_long *); 81static void psycho_intr_stub(void *); 82static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 83#ifndef OFW_NEWPCI 84static ofw_pci_binit_t psycho_binit; 85#endif 86 87/* Interrupt handlers */ 88static void psycho_ue(void *); 89static void psycho_ce(void *); 90static void psycho_bus_a(void *); 91static void psycho_bus_b(void *); 92static void psycho_powerfail(void *); 93#ifdef PSYCHO_MAP_WAKEUP 94static void psycho_wakeup(void *); 95#endif 96 97/* IOMMU support */ 98static void psycho_iommu_init(struct psycho_softc *, int); 99 100/* 101 * Methods. 102 */ 103static device_probe_t psycho_probe; 104static device_attach_t psycho_attach; 105static bus_read_ivar_t psycho_read_ivar; 106static bus_setup_intr_t psycho_setup_intr; 107static bus_teardown_intr_t psycho_teardown_intr; 108static bus_alloc_resource_t psycho_alloc_resource; 109static bus_activate_resource_t psycho_activate_resource; 110static bus_deactivate_resource_t psycho_deactivate_resource; 111static bus_release_resource_t psycho_release_resource; 112static pcib_maxslots_t psycho_maxslots; 113static pcib_read_config_t psycho_read_config; 114static pcib_write_config_t psycho_write_config; 115static pcib_route_interrupt_t psycho_route_interrupt; 116static ofw_pci_intr_pending_t psycho_intr_pending; 117#ifndef OFW_NEWPCI 118static ofw_pci_guess_ino_t psycho_guess_ino; 119#endif 120static ofw_pci_get_bus_handle_t psycho_get_bus_handle; 121#ifdef OFW_NEWPCI 122static ofw_pci_get_node_t psycho_get_node; 123static ofw_pci_adjust_busrange_t psycho_adjust_busrange; 124#endif 125 126static device_method_t psycho_methods[] = { 127 /* Device interface */ 128 DEVMETHOD(device_probe, psycho_probe), 129 DEVMETHOD(device_attach, psycho_attach), 130 131 /* Bus interface */ 132 DEVMETHOD(bus_print_child, bus_generic_print_child), 133 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 134 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 135 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 136 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 137 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 138 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 139 DEVMETHOD(bus_release_resource, psycho_release_resource), 140 141 /* pcib interface */ 142 DEVMETHOD(pcib_maxslots, psycho_maxslots), 143 DEVMETHOD(pcib_read_config, psycho_read_config), 144 DEVMETHOD(pcib_write_config, psycho_write_config), 145 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 146 147 /* ofw_pci interface */ 148 DEVMETHOD(ofw_pci_intr_pending, psycho_intr_pending), 149#ifndef OFW_NEWPCI 150 DEVMETHOD(ofw_pci_guess_ino, psycho_guess_ino), 151#endif 152 DEVMETHOD(ofw_pci_get_bus_handle, psycho_get_bus_handle), 153#ifdef OFW_NEWPCI 154 DEVMETHOD(ofw_pci_get_node, psycho_get_node), 155 DEVMETHOD(ofw_pci_adjust_busrange, psycho_adjust_busrange), 156#endif 157 158 { 0, 0 } 159}; 160 161static driver_t psycho_driver = { 162 "pcib", 163 psycho_methods, 164 sizeof(struct psycho_softc), 165}; 166 167static devclass_t psycho_devclass; 168 169DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 170 171SLIST_HEAD(, psycho_softc) psycho_softcs = 172 SLIST_HEAD_INITIALIZER(psycho_softcs); 173 174struct psycho_clr { 175 struct psycho_softc *pci_sc; 176 bus_addr_t pci_clr; /* clear register */ 177 driver_intr_t *pci_handler; /* handler to call */ 178 void *pci_arg; /* argument for the handler */ 179 void *pci_cookie; /* interrupt cookie of parent bus */ 180}; 181 182struct psycho_strayclr { 183 struct psycho_softc *psc_sc; 184 bus_addr_t psc_clr; /* clear register */ 185}; 186 187#define PSYCHO_READ8(sc, off) \ 188 bus_space_read_8((sc)->sc_bustag, (sc)->sc_bushandle, (off)) 189#define PSYCHO_WRITE8(sc, off, v) \ 190 bus_space_write_8((sc)->sc_bustag, (sc)->sc_bushandle, (off), (v)) 191#define PCICTL_READ8(sc, off) \ 192 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 193#define PCICTL_WRITE8(sc, off, v) \ 194 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 195 196/* 197 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 198 * single PCI bus and does not have a streaming buffer. It often has an APB 199 * (advanced PCI bridge) connected to it, which was designed specifically for 200 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 201 * appears as two "simba"'s underneath the sabre. 202 * 203 * "psycho" and "psycho+" are dual UPA to PCI bridges. They sit on the UPA bus 204 * and manage two PCI buses. "psycho" has two 64-bit 33MHz buses, while 205 * "psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 206 * will usually find a "psycho+" since I don't think the original "psycho" 207 * ever shipped, and if it did it would be in the U30. 208 * 209 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 210 * both part of the same IC, they only have a single register space. As such, 211 * they need to be configured together, even though the autoconfiguration will 212 * attach them separately. 213 * 214 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 215 * as pci1 and pci2, although they have been implemented with other PCI bus 216 * numbers on some machines. 217 * 218 * On UltraII machines, there can be any number of "psycho+" ICs, each 219 * providing two PCI buses. 220 */ 221#ifdef DEBUGGER_ON_POWERFAIL 222#define PSYCHO_PWRFAIL_INT_FLAGS INTR_FAST 223#else 224#define PSYCHO_PWRFAIL_INT_FLAGS 0 225#endif 226 227#define OFW_PCI_TYPE "pci" 228 229struct psycho_desc { 230 char *pd_string; 231 int pd_mode; 232 char *pd_name; 233}; 234 235static struct psycho_desc psycho_compats[] = { 236 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 237 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre (US-IIi) compatible" }, 238 { "pci108e,a001", PSYCHO_MODE_SABRE, "Sabre (US-IIe) compatible" }, 239 { NULL, 0, NULL } 240}; 241 242static struct psycho_desc psycho_models[] = { 243 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 244 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 245 { NULL, 0, NULL } 246}; 247 248static struct psycho_desc * 249psycho_find_desc(struct psycho_desc *table, char *string) 250{ 251 struct psycho_desc *desc; 252 253 for (desc = table; desc->pd_string != NULL; desc++) { 254 if (strcmp(desc->pd_string, string) == 0) 255 return (desc); 256 } 257 return (NULL); 258} 259 260static struct psycho_desc * 261psycho_get_desc(phandle_t node, char *model) 262{ 263 struct psycho_desc *rv; 264 char compat[32]; 265 266 rv = NULL; 267 if (model != NULL) 268 rv = psycho_find_desc(psycho_models, model); 269 if (rv == NULL && 270 OF_getprop(node, "compatible", compat, sizeof(compat)) != -1) 271 rv = psycho_find_desc(psycho_compats, compat); 272 return (rv); 273} 274 275static int 276psycho_probe(device_t dev) 277{ 278 phandle_t node; 279 char *dtype; 280 281 node = nexus_get_node(dev); 282 dtype = nexus_get_device_type(dev); 283 if (nexus_get_reg(dev) != NULL && dtype != NULL && 284 strcmp(dtype, OFW_PCI_TYPE) == 0 && 285 psycho_get_desc(node, nexus_get_model(dev)) != NULL) { 286 device_set_desc(dev, "U2P UPA-PCI bridge"); 287 return (0); 288 } 289 290 return (ENXIO); 291} 292 293static int 294psycho_attach(device_t dev) 295{ 296 struct psycho_softc *sc; 297 struct psycho_softc *osc = NULL; 298 struct psycho_softc *asc; 299 struct upa_regs *reg; 300#ifndef OFW_NEWPCI 301 struct ofw_pci_bdesc obd; 302#endif 303 struct psycho_desc *desc; 304 phandle_t node; 305 u_int64_t csr; 306 u_long mlen; 307 int psycho_br[2]; 308 int n, i, nreg, rid; 309#ifdef PSYCHO_DEBUG 310 bus_addr_t map, clr; 311 u_int64_t mr; 312#endif 313 314 node = nexus_get_node(dev); 315 sc = device_get_softc(dev); 316 desc = psycho_get_desc(node, nexus_get_model(dev)); 317 318 sc->sc_node = node; 319 sc->sc_dev = dev; 320 sc->sc_dmatag = nexus_get_dmatag(dev); 321 sc->sc_mode = desc->pd_mode; 322 323 /* 324 * The psycho gets three register banks: 325 * (0) per-PBM configuration and status registers 326 * (1) per-PBM PCI configuration space, containing only the 327 * PBM 256-byte PCI header 328 * (2) the shared psycho configuration registers 329 */ 330 reg = nexus_get_reg(dev); 331 nreg = nexus_get_nreg(dev); 332 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 333 if (nreg <= 2) 334 panic("psycho_attach: %d not enough registers", nreg); 335 sc->sc_basepaddr = (vm_paddr_t)UPA_REG_PHYS(®[2]); 336 mlen = UPA_REG_SIZE(®[2]); 337 sc->sc_pcictl = UPA_REG_PHYS(®[0]) - sc->sc_basepaddr; 338 switch (sc->sc_pcictl) { 339 case PSR_PCICTL0: 340 sc->sc_half = 0; 341 break; 342 case PSR_PCICTL1: 343 sc->sc_half = 1; 344 break; 345 default: 346 panic("psycho_attach: bogus pci control register " 347 "location"); 348 } 349 } else { 350 if (nreg <= 0) 351 panic("psycho_attach: %d not enough registers", nreg); 352 sc->sc_basepaddr = (vm_paddr_t)UPA_REG_PHYS(®[0]); 353 mlen = UPA_REG_SIZE(reg); 354 sc->sc_pcictl = PSR_PCICTL0; 355 sc->sc_half = 0; 356 } 357 358 /* 359 * Match other psycho's that are already configured against 360 * the base physical address. This will be the same for a 361 * pair of devices that share register space. 362 */ 363 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 364 if (asc->sc_basepaddr == sc->sc_basepaddr) { 365 /* Found partner */ 366 osc = asc; 367 break; 368 } 369 } 370 371 if (osc == NULL) { 372 rid = 0; 373 sc->sc_mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 374 sc->sc_basepaddr, sc->sc_basepaddr + mlen - 1, mlen, 375 RF_ACTIVE); 376 if (sc->sc_mem_res == NULL || 377 rman_get_start(sc->sc_mem_res) != sc->sc_basepaddr) 378 panic("psycho_attach: can't allocate device memory"); 379 sc->sc_bustag = rman_get_bustag(sc->sc_mem_res); 380 sc->sc_bushandle = rman_get_bushandle(sc->sc_mem_res); 381 } else { 382 /* 383 * There's another psycho using the same register space. Copy the 384 * relevant stuff. 385 */ 386 sc->sc_mem_res = NULL; 387 sc->sc_bustag = osc->sc_bustag; 388 sc->sc_bushandle = osc->sc_bushandle; 389 } 390 csr = PSYCHO_READ8(sc, PSR_CS); 391 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 392 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 393 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 394 395 device_printf(dev, "%s, impl %d, version %d, ign %#x, bus %c\n", 396 desc->pd_name, (int)PSYCHO_GCSR_IMPL(csr), 397 (int)PSYCHO_GCSR_VERS(csr), sc->sc_ign, 'A' + sc->sc_half); 398 399 /* Setup the PCI control register. */ 400 csr = PCICTL_READ8(sc, PCR_CS); 401 csr |= PCICTL_MRLM | PCICTL_ARB_PARK | PCICTL_ERRINTEN | PCICTL_4ENABLE; 402 csr &= ~(PCICTL_SERR | PCICTL_CPU_PRIO | PCICTL_ARB_PRIO | 403 PCICTL_RTRYWAIT); 404 PCICTL_WRITE8(sc, PCR_CS, csr); 405 406 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 407 /* Use the PROM preset for now. */ 408 csr = PCICTL_READ8(sc, PCR_TAS); 409 if (csr == 0) 410 panic("psycho_attach: sabre TAS not initialized."); 411 sc->sc_dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT; 412 } else 413 sc->sc_dvmabase = -1; 414 415 /* Initialize memory and i/o rmans */ 416 sc->sc_io_rman.rm_type = RMAN_ARRAY; 417 sc->sc_io_rman.rm_descr = "Psycho PCI I/O Ports"; 418 if (rman_init(&sc->sc_io_rman) != 0 || 419 rman_manage_region(&sc->sc_io_rman, 0, PSYCHO_IO_SIZE) != 0) 420 panic("psycho_probe: failed to set up i/o rman"); 421 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 422 sc->sc_mem_rman.rm_descr = "Psycho PCI Memory"; 423 if (rman_init(&sc->sc_mem_rman) != 0 || 424 rman_manage_region(&sc->sc_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 425 panic("psycho_probe: failed to set up memory rman"); 426 427 sc->sc_nrange = OF_getprop_alloc(sc->sc_node, "ranges", 428 sizeof(*sc->sc_range), (void **)&sc->sc_range); 429 if (sc->sc_nrange == -1) 430 panic("could not get psycho ranges"); 431 /* 432 * Find the addresses of the various bus spaces. 433 * There should not be multiple ones of one kind. 434 * The physical start addresses of the ranges are the configuration, 435 * memory and IO handles. 436 */ 437 for (n = 0; n < sc->sc_nrange; n++) { 438 i = UPA_RANGE_CS(&sc->sc_range[n]); 439 if (sc->sc_bh[i] != 0) 440 panic("psycho_attach: duplicate range for space %d", i); 441 sc->sc_bh[i] = UPA_RANGE_PHYS(&sc->sc_range[n]); 442 } 443 /* 444 * Check that all needed handles are present. The PCI_CS_MEM64 one is 445 * not currently used. 446 */ 447 for (n = 0; n < 3; n++) { 448 if (sc->sc_bh[n] == 0) 449 panic("psycho_attach: range %d missing", n); 450 } 451 452 /* Register the softc, this is needed for paired psychos. */ 453 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 454 455 /* 456 * If we're a sabre or the first of a pair of psycho's to arrive here, 457 * start up the IOMMU. 458 */ 459 if (osc == NULL) { 460 /* 461 * Establish handlers for interesting interrupts.... 462 * 463 * XXX We need to remember these and remove this to support 464 * hotplug on the UPA/FHC bus. 465 * 466 * XXX Not all controllers have these, but installing them 467 * is better than trying to sort through this mess. 468 */ 469 psycho_set_intr(sc, 0, dev, PSR_UE_INT_MAP, INTR_FAST, 470 psycho_ue); 471 psycho_set_intr(sc, 1, dev, PSR_CE_INT_MAP, 0, psycho_ce); 472 psycho_set_intr(sc, 2, dev, PSR_PCIAERR_INT_MAP, INTR_FAST, 473 psycho_bus_a); 474 psycho_set_intr(sc, 4, dev, PSR_POWER_INT_MAP, 475 PSYCHO_PWRFAIL_INT_FLAGS, psycho_powerfail); 476 /* Psycho-specific initialization. */ 477 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 478 /* 479 * Sabres do not have the following two interrupts. 480 */ 481 psycho_set_intr(sc, 3, dev, PSR_PCIBERR_INT_MAP, 482 INTR_FAST, psycho_bus_b); 483#ifdef PSYCHO_MAP_WAKEUP 484 /* 485 * psycho_wakeup() doesn't do anything useful right 486 * now. 487 */ 488 psycho_set_intr(sc, 5, dev, PSR_PWRMGT_INT_MAP, 0, 489 psycho_wakeup); 490#endif /* PSYCHO_MAP_WAKEUP */ 491 492 /* Initialize the counter-timer. */ 493 sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, 494 PSR_TC0); 495 } 496 497 /* 498 * Setup IOMMU and PCI configuration if we're the first 499 * of a pair of psycho's to arrive here. 500 * 501 * We should calculate a TSB size based on amount of RAM 502 * and number of bus controllers and number and type of 503 * child devices. 504 * 505 * For the moment, 32KB should be more than enough. 506 */ 507 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 508 M_NOWAIT); 509 if (sc->sc_is == NULL) 510 panic("psycho_attach: malloc iommu_state failed"); 511 sc->sc_is->is_sb[0] = 0; 512 sc->sc_is->is_sb[1] = 0; 513 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 514 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 515 psycho_iommu_init(sc, 3); 516 } else { 517 /* Just copy IOMMU state, config tag and address */ 518 sc->sc_is = osc->sc_is; 519 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 520 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 521 iommu_reset(sc->sc_is); 522 } 523 524 /* Allocate our tags. */ 525 sc->sc_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 526 sc->sc_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 527 sc->sc_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 528 if (bus_dma_tag_create(sc->sc_dmatag, 8, 1, 0, 0x3ffffffff, NULL, NULL, 529 0x3ffffffff, 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_dmat) != 0) 530 panic("psycho_attach: bus_dma_tag_create failed"); 531 /* Customize the tag. */ 532 sc->sc_dmat->dt_cookie = sc->sc_is; 533 sc->sc_dmat->dt_mt = &iommu_dma_methods; 534 /* XXX: register as root dma tag (kludge). */ 535 sparc64_root_dma_tag = sc->sc_dmat; 536 537#ifdef PSYCHO_DEBUG 538 /* 539 * Enable all interrupts and clear all interrupt states. 540 * This aids the debugging of interrupt routing problems. 541 */ 542 for (map = PSR_PCIA0_INT_MAP, clr = PSR_PCIA0_INT_CLR, n = 0; 543 map <= PSR_PCIB3_INT_MAP; map += 8, clr += 32, n++) { 544 mr = PSYCHO_READ8(sc, map); 545 device_printf(dev, "intr map (pci) %d: %#lx\n", n, (u_long)mr); 546 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 547 for (i = 0; i < 4; i++) 548 PCICTL_WRITE8(sc, clr + i * 8, 0); 549 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 550 } 551 for (map = PSR_SCSI_INT_MAP, clr = PSR_SCSI_INT_CLR, n = 0; 552 map <= PSR_SERIAL_INT_MAP; map += 8, clr += 8, n++) { 553 mr = PSYCHO_READ8(sc, map); 554 device_printf(dev, "intr map (obio) %d: %#lx, clr: %#lx\n", n, 555 (u_long)mr, (u_long)clr); 556 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 557 PSYCHO_WRITE8(sc, clr, 0); 558 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 559 } 560#endif /* PSYCHO_DEBUG */ 561 562 /* 563 * Get the bus range from the firmware; it is used solely for obtaining 564 * the inital bus number, and cannot be trusted on all machines. 565 */ 566 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br)); 567 if (n == -1) 568 panic("could not get psycho bus-range"); 569 if (n != sizeof(psycho_br)) 570 panic("broken psycho bus-range (%d)", n); 571 572 sc->sc_secbus = sc->sc_subbus = ofw_pci_alloc_busno(sc->sc_node); 573 /* 574 * Program the bus range registers. 575 * NOTE: for the psycho, the second write changes the bus number the 576 * psycho itself uses for it's configuration space, so these 577 * writes must be kept in this order! 578 * The sabre always uses bus 0, but there only can be one sabre per 579 * machine. 580 */ 581 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SUBBUS, 582 sc->sc_subbus, 1); 583 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SECBUS, 584 sc->sc_secbus, 1); 585 586#ifdef OFW_NEWPCI 587 ofw_bus_setup_iinfo(node, &sc->sc_iinfo, sizeof(ofw_pci_intr_t)); 588#else 589 obd.obd_bus = obd.obd_secbus = sc->sc_secbus; 590 obd.obd_subbus = sc->sc_subbus; 591 obd.obd_slot = PCS_DEVICE; 592 obd.obd_func = PCS_FUNC; 593 obd.obd_init = psycho_binit; 594 obd.obd_super = NULL; 595 596 /* 597 * Initialize the interrupt registers of all devices hanging from 598 * the host bridge directly or indirectly via PCI-PCI bridges. 599 * The MI code (and the PCI spec) assume that this is done during 600 * system initialization, however the firmware does not do this 601 * at least on some models, and we probably shouldn't trust that 602 * the firmware uses the same model as this driver if it does. 603 * Additionally, set up the bus numbers and ranges. 604 */ 605 ofw_pci_init(dev, sc->sc_node, sc->sc_ign, &obd); 606#endif /* OFW_NEWPCI */ 607 608 device_add_child(dev, "pci", sc->sc_secbus); 609 return (bus_generic_attach(dev)); 610} 611 612static void 613psycho_set_intr(struct psycho_softc *sc, int index, 614 device_t dev, bus_addr_t map, int iflags, driver_intr_t handler) 615{ 616 int rid, vec; 617 u_int64_t mr; 618 619 mr = PSYCHO_READ8(sc, map); 620 vec = INTVEC(mr); 621 sc->sc_irq_res[index] = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 622 vec, vec, 1, RF_ACTIVE); 623 if (sc->sc_irq_res[index] == NULL) 624 panic("psycho_set_intr: failed to get interrupt"); 625 bus_setup_intr(dev, sc->sc_irq_res[index], INTR_TYPE_MISC | iflags, 626 handler, sc, &sc->sc_ihand[index]); 627 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 628} 629 630static int 631psycho_find_intrmap(struct psycho_softc *sc, int ino, bus_addr_t *intrmapptr, 632 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 633{ 634 bus_addr_t intrmap, intrclr; 635 u_int64_t im; 636 u_long diag; 637 int found; 638 639 found = 0; 640 /* Hunt thru obio first */ 641 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 642 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 643 intrmap <= PSR_SERIAL_INT_MAP; intrmap += 8, intrclr += 8, 644 diag >>= 2) { 645 im = PSYCHO_READ8(sc, intrmap); 646 if (INTINO(im) == ino) { 647 diag &= 2; 648 found = 1; 649 break; 650 } 651 } 652 653 if (!found) { 654 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 655 /* Now do PCI interrupts */ 656 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 657 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 658 diag >>= 8) { 659 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 660 (intrmap == PSR_PCIA2_INT_MAP || 661 intrmap == PSR_PCIA3_INT_MAP)) 662 continue; 663 im = PSYCHO_READ8(sc, intrmap); 664 if (((im ^ ino) & 0x3c) == 0) { 665 intrclr += 8 * (ino & 3); 666 diag = (diag >> ((ino & 3) * 2)) & 2; 667 found = 1; 668 break; 669 } 670 } 671 } 672 if (intrmapptr != NULL) 673 *intrmapptr = intrmap; 674 if (intrclrptr != NULL) 675 *intrclrptr = intrclr; 676 if (intrdiagptr != NULL) 677 *intrdiagptr = diag; 678 return (found); 679} 680 681/* 682 * Interrupt handlers. 683 */ 684static void 685psycho_ue(void *arg) 686{ 687 struct psycho_softc *sc = (struct psycho_softc *)arg; 688 u_int64_t afar, afsr; 689 690 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 691 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 692 /* 693 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 694 * the AFAR to be set to the physical address of the TTE entry that 695 * was invalid/write protected. Call into the iommu code to have 696 * them decoded to virtual IO addresses. 697 */ 698 if ((afsr & UEAFSR_P_DTE) != 0) 699 iommu_decode_fault(sc->sc_is, afar); 700 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx", 701 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 702} 703 704static void 705psycho_ce(void *arg) 706{ 707 struct psycho_softc *sc = (struct psycho_softc *)arg; 708 u_int64_t afar, afsr; 709 710 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 711 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 712 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx " 713 "AFSR %#lx\n", (u_long)afar, (u_long)afsr); 714 /* Clear the error bits that we caught. */ 715 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr & CEAFSR_ERRMASK); 716 PSYCHO_WRITE8(sc, PSR_CE_INT_CLR, 0); 717} 718 719static void 720psycho_bus_a(void *arg) 721{ 722 struct psycho_softc *sc = (struct psycho_softc *)arg; 723 u_int64_t afar, afsr; 724 725 afar = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFA); 726 afsr = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFS); 727 panic("%s: PCI bus A error AFAR %#lx AFSR %#lx", 728 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 729} 730 731static void 732psycho_bus_b(void *arg) 733{ 734 struct psycho_softc *sc = (struct psycho_softc *)arg; 735 u_int64_t afar, afsr; 736 737 afar = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFA); 738 afsr = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFS); 739 panic("%s: PCI bus B error AFAR %#lx AFSR %#lx", 740 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 741} 742 743static void 744psycho_powerfail(void *arg) 745{ 746 747#ifdef DEBUGGER_ON_POWERFAIL 748 struct psycho_softc *sc = (struct psycho_softc *)arg; 749 750 Debugger("powerfail"); 751 PSYCHO_WRITE8(sc, PSR_POWER_INT_CLR, 0); 752#else 753 printf("Power Failure Detected: Shutting down NOW.\n"); 754 shutdown_nice(0); 755#endif 756} 757 758#ifdef PSYCHO_MAP_WAKEUP 759static void 760psycho_wakeup(void *arg) 761{ 762 struct psycho_softc *sc = (struct psycho_softc *)arg; 763 764 PSYCHO_WRITE8(sc, PSR_PWRMGT_INT_CLR, 0); 765 /* Gee, we don't really have a framework to deal with this properly. */ 766 device_printf(sc->sc_dev, "power management wakeup\n"); 767} 768#endif /* PSYCHO_MAP_WAKEUP */ 769 770void 771psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 772{ 773 char *name; 774 struct iommu_state *is = sc->sc_is; 775 776 /* punch in our copies */ 777 is->is_bustag = sc->sc_bustag; 778 is->is_bushandle = sc->sc_bushandle; 779 is->is_iommu = PSR_IOMMU; 780 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 781 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 782 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 783 is->is_dva = PSR_IOMMU_SVADIAG; 784 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 785 786 /* give us a nice name.. */ 787 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 788 if (name == 0) 789 panic("couldn't malloc iommu name"); 790 snprintf(name, 32, "%s dvma", device_get_nameunit(sc->sc_dev)); 791 792 iommu_init(name, is, tsbsize, sc->sc_dvmabase, 0); 793} 794 795#ifndef OFW_NEWPCI 796static void 797psycho_binit(device_t busdev, struct ofw_pci_bdesc *obd) 798{ 799 800#ifdef PSYCHO_DEBUG 801 printf("psycho at %u/%u/%u: setting bus #s to %u/%u/%u\n", 802 obd->obd_bus, obd->obd_slot, obd->obd_func, obd->obd_bus, 803 obd->obd_secbus, obd->obd_subbus); 804#endif /* PSYCHO_DEBUG */ 805 PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func, 806 PCSR_SUBBUS, obd->obd_subbus, 1); 807} 808#endif 809 810static int 811psycho_maxslots(device_t dev) 812{ 813 814 /* XXX: is this correct? */ 815 return (PCI_SLOTMAX); 816} 817 818#ifndef OFW_NEWPCI 819/* 820 * Keep a table of quirky PCI devices that need fixups before the MI PCI code 821 * creates the resource lists. This needs to be moved around once other bus 822 * drivers are added. Moving it to the MI code should maybe be reconsidered 823 * if one of these devices appear in non-sparc64 boxen. It's likely that not 824 * all BIOSes/firmwares can deal with them. 825 */ 826struct psycho_dquirk { 827 u_int32_t dq_devid; 828 int dq_quirk; 829}; 830 831/* Quirk types. May be or'ed together. */ 832#define DQT_BAD_INTPIN 1 /* Intpin reg 0, but intpin used */ 833 834static struct psycho_dquirk dquirks[] = { 835 { 0x1001108e, DQT_BAD_INTPIN }, /* Sun HME (PCIO func. 1) */ 836 { 0x1101108e, DQT_BAD_INTPIN }, /* Sun GEM (PCIO2 func. 1) */ 837 { 0x1102108e, DQT_BAD_INTPIN }, /* Sun FireWire ctl. (PCIO2 func. 2) */ 838 { 0x1103108e, DQT_BAD_INTPIN }, /* Sun USB ctl. (PCIO2 func. 3) */ 839}; 840#endif /* !OFW_NEWPCI */ 841 842#define NDQUIRKS (sizeof(dquirks) / sizeof(dquirks[0])) 843 844static u_int32_t 845psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 846 int width) 847{ 848 struct psycho_softc *sc; 849 bus_space_handle_t bh; 850 u_long offset = 0; 851#ifndef OFW_NEWPCI 852 u_int32_t devid; 853#endif 854 u_int8_t byte; 855 u_int16_t shrt; 856 u_int32_t wrd; 857 u_int32_t r; 858 int i; 859 860 sc = (struct psycho_softc *)device_get_softc(dev); 861 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 862 bh = sc->sc_bh[PCI_CS_CONFIG]; 863 switch (width) { 864 case 1: 865 i = bus_space_peek_1(sc->sc_cfgt, bh, offset, &byte); 866 r = byte; 867 break; 868 case 2: 869 i = bus_space_peek_2(sc->sc_cfgt, bh, offset, &shrt); 870 r = shrt; 871 break; 872 case 4: 873 i = bus_space_peek_4(sc->sc_cfgt, bh, offset, &wrd); 874 r = wrd; 875 break; 876 default: 877 panic("psycho_read_config: bad width"); 878 } 879 880 if (i) { 881#ifdef PSYCHO_DEBUG 882 printf("psycho read data error reading: %d.%d.%d: 0x%x\n", 883 bus, slot, func, reg); 884#endif 885 r = -1; 886 } 887 888#ifndef OFW_NEWPCI 889 if (reg == PCIR_INTPIN && r == 0) { 890 /* Check for DQT_BAD_INTPIN quirk. */ 891 devid = psycho_read_config(dev, bus, slot, func, 892 PCIR_DEVVENDOR, 4); 893 for (i = 0; i < NDQUIRKS; i++) { 894 if (dquirks[i].dq_devid == devid) { 895 /* 896 * Need to set the intpin to a value != 0 so 897 * that the MI code will think that this device 898 * has an interrupt. 899 * Just use 1 (intpin a) for now. This is, of 900 * course, bogus, but since interrupts are 901 * routed in advance, this does not really 902 * matter. 903 */ 904 if ((dquirks[i].dq_quirk & DQT_BAD_INTPIN) != 0) 905 r = 1; 906 break; 907 } 908 } 909 } 910#endif /* !OFW_NEWPCI */ 911 return (r); 912} 913 914static void 915psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, 916 u_int reg, u_int32_t val, int width) 917{ 918 struct psycho_softc *sc; 919 bus_space_handle_t bh; 920 u_long offset = 0; 921 922 sc = (struct psycho_softc *)device_get_softc(dev); 923 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 924 bh = sc->sc_bh[PCI_CS_CONFIG]; 925 switch (width) { 926 case 1: 927 bus_space_write_1(sc->sc_cfgt, bh, offset, val); 928 break; 929 case 2: 930 bus_space_write_2(sc->sc_cfgt, bh, offset, val); 931 break; 932 case 4: 933 bus_space_write_4(sc->sc_cfgt, bh, offset, val); 934 break; 935 default: 936 panic("psycho_write_config: bad width"); 937 } 938} 939 940static int 941psycho_route_interrupt(device_t bridge, device_t dev, int pin) 942{ 943#ifdef OFW_NEWPCI 944 struct psycho_softc *sc = device_get_softc(bridge); 945 struct ofw_pci_register reg; 946 bus_addr_t intrmap; 947 phandle_t node = ofw_pci_get_node(dev); 948 ofw_pci_intr_t pintr, mintr; 949 u_int8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 950 951 pintr = pin; 952 if (ofw_bus_lookup_imap(node, &sc->sc_iinfo, ®, sizeof(reg), 953 &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) 954 return (mintr); 955 /* 956 * If this is outside of the range for an intpin, it's likely a full 957 * INO, and no mapping is required at all; this happens on the u30, 958 * where there's no interrupt map at the psycho node. Fortunately, 959 * there seem to be no INOs in the intpin range on this boxen, so 960 * this easy heuristics will do. 961 */ 962 if (pin > 4) 963 return (pin); 964 /* 965 * Guess the INO; we always assume that this is a non-OBIO 966 * device, and that pin is a "real" intpin number. Determine 967 * the mapping register to be used by the slot number. 968 * We only need to do this on e450s, it seems; here, the slot numbers 969 * for bus A are one-based, while those for bus B seemingly have an 970 * offset of 2 (hence the factor of 3 below). 971 */ 972 intrmap = PSR_PCIA0_INT_MAP + 973 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half); 974 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1; 975 device_printf(bridge, "guessing interrupt %d for device %d/%d pin %d\n", 976 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin); 977 return (mintr); 978#else 979 /* 980 * XXX: ugly loathsome hack: 981 * We can't use ofw_pci_route_intr() here; the device passed may be 982 * the one of a bridge, so the original device can't be recovered. 983 * 984 * We need to use the firmware to route interrupts, however it has 985 * no interface which could be used to interpret intpins; instead, 986 * all assignments are done by device. 987 * 988 * The MI pci code will try to reroute interrupts of 0, although they 989 * are correct; all other interrupts are preinitialized, so if we 990 * get here, the intline is either 0 (so return 0), or we hit a 991 * device which was not preinitialized (e.g. hotplugged stuff), in 992 * which case we are lost. 993 */ 994 return (0); 995#endif /* OFW_NEWPCI */ 996} 997 998static int 999psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1000{ 1001 struct psycho_softc *sc; 1002 1003 sc = (struct psycho_softc *)device_get_softc(dev); 1004 switch (which) { 1005 case PCIB_IVAR_BUS: 1006 *result = sc->sc_secbus; 1007 return (0); 1008 } 1009 return (ENOENT); 1010} 1011 1012/* Write to the correct clr register, and call the actual handler. */ 1013static void 1014psycho_intr_stub(void *arg) 1015{ 1016 struct psycho_clr *pc; 1017 1018 pc = (struct psycho_clr *)arg; 1019 pc->pci_handler(pc->pci_arg); 1020 PSYCHO_WRITE8(pc->pci_sc, pc->pci_clr, 0); 1021} 1022 1023static int 1024psycho_setup_intr(device_t dev, device_t child, 1025 struct resource *ires, int flags, driver_intr_t *intr, void *arg, 1026 void **cookiep) 1027{ 1028 struct psycho_softc *sc; 1029 struct psycho_clr *pc; 1030 bus_addr_t intrmapptr, intrclrptr; 1031 long vec = rman_get_start(ires); 1032 u_int64_t mr; 1033 int ino, error; 1034 1035 sc = (struct psycho_softc *)device_get_softc(dev); 1036 pc = (struct psycho_clr *)malloc(sizeof(*pc), M_DEVBUF, M_NOWAIT); 1037 if (pc == NULL) 1038 return (0); 1039 1040 /* 1041 * Hunt through all the interrupt mapping regs to look for our 1042 * interrupt vector. 1043 * 1044 * XXX We only compare INOs rather than IGNs since the firmware may 1045 * not provide the IGN and the IGN is constant for all devices on that 1046 * PCI controller. This could cause problems for the FFB/external 1047 * interrupt which has a full vector that can be set arbitrarily. 1048 */ 1049 ino = INTINO(vec); 1050 1051 if (!psycho_find_intrmap(sc, ino, &intrmapptr, &intrclrptr, NULL)) { 1052 device_printf(dev, "Cannot find interrupt vector %lx\n", vec); 1053 free(pc, M_DEVBUF); 1054 return (0); 1055 } 1056 1057#ifdef PSYCHO_DEBUG 1058 device_printf(dev, "psycho_setup_intr: INO %d, map %#lx, clr %#lx\n", 1059 ino, (u_long)intrmapptr, (u_long)intrclrptr); 1060#endif 1061 pc->pci_sc = sc; 1062 pc->pci_arg = arg; 1063 pc->pci_handler = intr; 1064 pc->pci_clr = intrclrptr; 1065 /* Disable the interrupt while we fiddle with it */ 1066 mr = PSYCHO_READ8(sc, intrmapptr); 1067 PSYCHO_WRITE8(sc, intrmapptr, mr & ~INTMAP_V); 1068 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 1069 psycho_intr_stub, pc, cookiep); 1070 if (error != 0) { 1071 free(pc, M_DEVBUF); 1072 return (error); 1073 } 1074 pc->pci_cookie = *cookiep; 1075 *cookiep = pc; 1076 1077 /* 1078 * Clear the interrupt, it might have been triggered before it was 1079 * set up. 1080 */ 1081 PSYCHO_WRITE8(sc, intrclrptr, 0); 1082 /* 1083 * Enable the interrupt and program the target module now we have the 1084 * handler installed. 1085 */ 1086 PSYCHO_WRITE8(sc, intrmapptr, INTMAP_ENABLE(mr, PCPU_GET(mid))); 1087 return (error); 1088} 1089 1090static int 1091psycho_teardown_intr(device_t dev, device_t child, 1092 struct resource *vec, void *cookie) 1093{ 1094 struct psycho_clr *pc; 1095 int error; 1096 1097 pc = (struct psycho_clr *)cookie; 1098 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 1099 pc->pci_cookie); 1100 /* 1101 * Don't disable the interrupt for now, so that stray interupts get 1102 * detected... 1103 */ 1104 if (error != 0) 1105 free(pc, M_DEVBUF); 1106 return (error); 1107} 1108 1109static struct resource * 1110psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1111 u_long start, u_long end, u_long count, u_int flags) 1112{ 1113 struct psycho_softc *sc; 1114 struct resource *rv; 1115 struct rman *rm; 1116 bus_space_tag_t bt; 1117 bus_space_handle_t bh; 1118 int needactivate = flags & RF_ACTIVE; 1119 1120 flags &= ~RF_ACTIVE; 1121 1122 sc = (struct psycho_softc *)device_get_softc(bus); 1123 if (type == SYS_RES_IRQ) { 1124 /* 1125 * XXX: Don't accept blank ranges for now, only single 1126 * interrupts. The other case should not happen with the MI pci 1127 * code... 1128 * XXX: This may return a resource that is out of the range 1129 * that was specified. Is this correct...? 1130 */ 1131 if (start != end) 1132 panic("psycho_alloc_resource: XXX: interrupt range"); 1133 start = end |= sc->sc_ign; 1134 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, 1135 rid, start, end, count, flags)); 1136 } 1137 switch (type) { 1138 case SYS_RES_MEMORY: 1139 rm = &sc->sc_mem_rman; 1140 bt = sc->sc_memt; 1141 bh = sc->sc_bh[PCI_CS_MEM32]; 1142 break; 1143 case SYS_RES_IOPORT: 1144 rm = &sc->sc_io_rman; 1145 bt = sc->sc_iot; 1146 bh = sc->sc_bh[PCI_CS_IO]; 1147 break; 1148 default: 1149 return (NULL); 1150 } 1151 1152 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1153 if (rv == NULL) 1154 return (NULL); 1155 1156 bh += rman_get_start(rv); 1157 rman_set_bustag(rv, bt); 1158 rman_set_bushandle(rv, bh); 1159 1160 if (needactivate) { 1161 if (bus_activate_resource(child, type, *rid, rv)) { 1162 rman_release_resource(rv); 1163 return (NULL); 1164 } 1165 } 1166 1167 return (rv); 1168} 1169 1170static int 1171psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1172 struct resource *r) 1173{ 1174 void *p; 1175 int error; 1176 1177 if (type == SYS_RES_IRQ) 1178 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1179 type, rid, r)); 1180 if (type == SYS_RES_MEMORY) { 1181 /* 1182 * Need to memory-map the device space, as some drivers depend 1183 * on the virtual address being set and useable. 1184 */ 1185 error = sparc64_bus_mem_map(rman_get_bustag(r), 1186 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1187 if (error != 0) 1188 return (error); 1189 rman_set_virtual(r, p); 1190 } 1191 return (rman_activate_resource(r)); 1192} 1193 1194static int 1195psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1196 struct resource *r) 1197{ 1198 1199 if (type == SYS_RES_IRQ) 1200 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1201 type, rid, r)); 1202 if (type == SYS_RES_MEMORY) { 1203 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1204 rman_set_virtual(r, NULL); 1205 } 1206 return (rman_deactivate_resource(r)); 1207} 1208 1209static int 1210psycho_release_resource(device_t bus, device_t child, int type, int rid, 1211 struct resource *r) 1212{ 1213 int error; 1214 1215 if (type == SYS_RES_IRQ) 1216 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1217 type, rid, r)); 1218 if (rman_get_flags(r) & RF_ACTIVE) { 1219 error = bus_deactivate_resource(child, type, rid, r); 1220 if (error) 1221 return error; 1222 } 1223 return (rman_release_resource(r)); 1224} 1225 1226static int 1227psycho_intr_pending(device_t dev, ofw_pci_intr_t intr) 1228{ 1229 struct psycho_softc *sc; 1230 u_long diag; 1231 1232 sc = (struct psycho_softc *)device_get_softc(dev); 1233 if (!psycho_find_intrmap(sc, intr, NULL, NULL, &diag)) { 1234 device_printf(dev, "psycho_intr_pending: mapping not found for" 1235 " %d\n", intr); 1236 return (0); 1237 } 1238 return (diag != 0); 1239} 1240 1241#ifndef OFW_NEWPCI 1242static ofw_pci_intr_t 1243psycho_guess_ino(device_t dev, phandle_t node, u_int slot, u_int pin) 1244{ 1245 struct psycho_softc *sc = (struct psycho_softc *)device_get_softc(dev); 1246 bus_addr_t intrmap; 1247 1248 /* 1249 * If this is not for one of our direct children (i.e. we are mapping 1250 * at our node), tell the interrupt mapper to go on - we need the 1251 * slot number of the device or it's topmost parent bridge to guess 1252 * the INO. 1253 */ 1254 if (node != sc->sc_node) 1255 return (PCI_INVALID_IRQ); 1256 /* 1257 * Actually guess the INO. We always assume that this is a non-OBIO 1258 * device, and use from the slot number to determine it. 1259 * We only need to do this on e450s, it seems; here, the slot numbers 1260 * for bus A are one-based, while those for bus B seemingly have an 1261 * offset of 2 (hence the factor of 3 below). 1262 */ 1263 intrmap = PSR_PCIA0_INT_MAP + 8 * (slot - 1 + 3 * sc->sc_half); 1264 return (INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1); 1265} 1266#endif /* !OFW_NEWPCI */ 1267 1268static bus_space_handle_t 1269psycho_get_bus_handle(device_t dev, int type, bus_space_handle_t childhdl, 1270 bus_space_tag_t *tag) 1271{ 1272 struct psycho_softc *sc; 1273 1274 sc = (struct psycho_softc *)device_get_softc(dev); 1275 switch (type) { 1276 case SYS_RES_IOPORT: 1277 *tag = sc->sc_iot; 1278 return (sc->sc_bh[PCI_CS_IO] + childhdl); 1279 case SYS_RES_MEMORY: 1280 *tag = sc->sc_memt; 1281 return (sc->sc_bh[PCI_CS_MEM32] + childhdl); 1282 default: 1283 panic("psycho_get_bus_handle: illegal space\n"); 1284 } 1285} 1286 1287#ifdef OFW_NEWPCI 1288static phandle_t 1289psycho_get_node(device_t bus, device_t dev) 1290{ 1291 struct psycho_softc *sc = device_get_softc(bus); 1292 1293 /* We only have one child, the PCI bus, which needs our own node. */ 1294 return (sc->sc_node); 1295} 1296 1297static void 1298psycho_adjust_busrange(device_t dev, u_int subbus) 1299{ 1300 struct psycho_softc *sc = device_get_softc(dev); 1301 1302 /* If necessary, adjust the subordinate bus number register. */ 1303 if (subbus > sc->sc_subbus) { 1304#ifdef PSYCHO_DEBUG 1305 device_printf(dev, 1306 "adjusting secondary bus number from %d to %d\n", 1307 sc->sc_subbus, subbus); 1308#endif 1309 sc->sc_subbus = subbus; 1310 PCIB_WRITE_CONFIG(dev, sc->sc_secbus, PCS_DEVICE, PCS_FUNC, 1311 PCSR_SUBBUS, subbus, 1); 1312 } 1313} 1314#endif 1315 1316static bus_space_tag_t 1317psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1318{ 1319 bus_space_tag_t bt; 1320 1321 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1322 M_NOWAIT | M_ZERO); 1323 if (bt == NULL) 1324 panic("psycho_alloc_bus_tag: out of memory"); 1325 1326 bzero(bt, sizeof *bt); 1327 bt->bst_cookie = sc; 1328 bt->bst_parent = sc->sc_bustag; 1329 bt->bst_type = type; 1330 return (bt); 1331} 1332