psycho.c revision 119291
1/* 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 30 * 31 * $FreeBSD: head/sys/sparc64/pci/psycho.c 119291 2003-08-22 07:39:05Z imp $ 32 */ 33 34/* 35 * Support for `psycho' and `psycho+' UPA to PCI bridge and 36 * UltraSPARC IIi and IIe `sabre' PCI controllers. 37 */ 38 39#include "opt_ofw_pci.h" 40#include "opt_psycho.h" 41 42#include <sys/param.h> 43#include <sys/systm.h> 44#include <sys/bus.h> 45#include <sys/kernel.h> 46#include <sys/malloc.h> 47#include <sys/pcpu.h> 48 49#include <ofw/openfirm.h> 50#include <ofw/ofw_pci.h> 51 52#include <machine/bus.h> 53#include <machine/bus_private.h> 54#include <machine/iommureg.h> 55#include <machine/bus_common.h> 56#include <machine/frame.h> 57#include <machine/intr_machdep.h> 58#include <machine/nexusvar.h> 59#include <machine/ofw_bus.h> 60#include <machine/ofw_upa.h> 61#include <machine/resource.h> 62#include <machine/cpu.h> 63 64#include <sys/rman.h> 65 66#include <machine/iommuvar.h> 67 68#include <dev/pci/pcivar.h> 69#include <dev/pci/pcireg.h> 70 71#include <sparc64/pci/ofw_pci.h> 72#include <sparc64/pci/psychoreg.h> 73#include <sparc64/pci/psychovar.h> 74 75#include "pcib_if.h" 76 77static void psycho_get_ranges(phandle_t, struct upa_ranges **, int *); 78static void psycho_set_intr(struct psycho_softc *, int, device_t, bus_addr_t, 79 int, driver_intr_t); 80static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *, 81 bus_addr_t *, u_long *); 82static void psycho_intr_stub(void *); 83static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 84#ifndef OFW_NEWPCI 85static ofw_pci_binit_t psycho_binit; 86#endif 87 88/* Interrupt handlers */ 89static void psycho_ue(void *); 90static void psycho_ce(void *); 91static void psycho_bus_a(void *); 92static void psycho_bus_b(void *); 93static void psycho_powerfail(void *); 94#ifdef PSYCHO_MAP_WAKEUP 95static void psycho_wakeup(void *); 96#endif 97 98/* IOMMU support */ 99static void psycho_iommu_init(struct psycho_softc *, int); 100 101/* 102 * Methods. 103 */ 104static device_probe_t psycho_probe; 105static device_attach_t psycho_attach; 106static bus_read_ivar_t psycho_read_ivar; 107static bus_setup_intr_t psycho_setup_intr; 108static bus_teardown_intr_t psycho_teardown_intr; 109static bus_alloc_resource_t psycho_alloc_resource; 110static bus_activate_resource_t psycho_activate_resource; 111static bus_deactivate_resource_t psycho_deactivate_resource; 112static bus_release_resource_t psycho_release_resource; 113static pcib_maxslots_t psycho_maxslots; 114static pcib_read_config_t psycho_read_config; 115static pcib_write_config_t psycho_write_config; 116static pcib_route_interrupt_t psycho_route_interrupt; 117static ofw_pci_intr_pending_t psycho_intr_pending; 118#ifndef OFW_NEWPCI 119static ofw_pci_guess_ino_t psycho_guess_ino; 120#endif 121static ofw_pci_get_bus_handle_t psycho_get_bus_handle; 122#ifdef OFW_NEWPCI 123static ofw_pci_get_node_t psycho_get_node; 124static ofw_pci_adjust_busrange_t psycho_adjust_busrange; 125#endif 126 127static device_method_t psycho_methods[] = { 128 /* Device interface */ 129 DEVMETHOD(device_probe, psycho_probe), 130 DEVMETHOD(device_attach, psycho_attach), 131 132 /* Bus interface */ 133 DEVMETHOD(bus_print_child, bus_generic_print_child), 134 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 135 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 136 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 137 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 138 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 139 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 140 DEVMETHOD(bus_release_resource, psycho_release_resource), 141 142 /* pcib interface */ 143 DEVMETHOD(pcib_maxslots, psycho_maxslots), 144 DEVMETHOD(pcib_read_config, psycho_read_config), 145 DEVMETHOD(pcib_write_config, psycho_write_config), 146 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 147 148 /* ofw_pci interface */ 149 DEVMETHOD(ofw_pci_intr_pending, psycho_intr_pending), 150#ifndef OFW_NEWPCI 151 DEVMETHOD(ofw_pci_guess_ino, psycho_guess_ino), 152#endif 153 DEVMETHOD(ofw_pci_get_bus_handle, psycho_get_bus_handle), 154#ifdef OFW_NEWPCI 155 DEVMETHOD(ofw_pci_get_node, psycho_get_node), 156 DEVMETHOD(ofw_pci_adjust_busrange, psycho_adjust_busrange), 157#endif 158 159 { 0, 0 } 160}; 161 162static driver_t psycho_driver = { 163 "pcib", 164 psycho_methods, 165 sizeof(struct psycho_softc), 166}; 167 168static devclass_t psycho_devclass; 169 170DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 171 172SLIST_HEAD(, psycho_softc) psycho_softcs = 173 SLIST_HEAD_INITIALIZER(psycho_softcs); 174 175struct psycho_clr { 176 struct psycho_softc *pci_sc; 177 bus_addr_t pci_clr; /* clear register */ 178 driver_intr_t *pci_handler; /* handler to call */ 179 void *pci_arg; /* argument for the handler */ 180 void *pci_cookie; /* interrupt cookie of parent bus */ 181}; 182 183struct psycho_strayclr { 184 struct psycho_softc *psc_sc; 185 bus_addr_t psc_clr; /* clear register */ 186}; 187 188#define PSYCHO_READ8(sc, off) \ 189 bus_space_read_8((sc)->sc_bustag, (sc)->sc_bushandle, (off)) 190#define PSYCHO_WRITE8(sc, off, v) \ 191 bus_space_write_8((sc)->sc_bustag, (sc)->sc_bushandle, (off), (v)) 192#define PCICTL_READ8(sc, off) \ 193 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 194#define PCICTL_WRITE8(sc, off, v) \ 195 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 196 197/* 198 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 199 * single PCI bus and does not have a streaming buffer. It often has an APB 200 * (advanced PCI bridge) connected to it, which was designed specifically for 201 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 202 * appears as two "simba"'s underneath the sabre. 203 * 204 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 205 * and manages two PCI buses. "psycho" has two 64-bit 33MHz buses, while 206 * "psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 207 * will usually find a "psycho+" since I don't think the original "psycho" 208 * ever shipped, and if it did it would be in the U30. 209 * 210 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 211 * both part of the same IC, they only have a single register space. As such, 212 * they need to be configured together, even though the autoconfiguration will 213 * attach them separately. 214 * 215 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 216 * as pci1 and pci2, although they have been implemented with other PCI bus 217 * numbers on some machines. 218 * 219 * On UltraII machines, there can be any number of "psycho+" ICs, each 220 * providing two PCI buses. 221 * 222 * 223 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 224 * the values of the following interrupts in this order: 225 * 226 * PCI Bus Error (30) 227 * DMA UE (2e) 228 * DMA CE (2f) 229 * Power Fail (25) 230 * 231 * We really should attach handlers for each. 232 */ 233#ifdef DEBUGGER_ON_POWERFAIL 234#define PSYCHO_PWRFAIL_INT_FLAGS INTR_FAST 235#else 236#define PSYCHO_PWRFAIL_INT_FLAGS 0 237#endif 238 239#define OFW_PCI_TYPE "pci" 240 241struct psycho_desc { 242 char *pd_string; 243 int pd_mode; 244 char *pd_name; 245}; 246 247static struct psycho_desc psycho_compats[] = { 248 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 249 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre (US-IIi) compatible" }, 250 { "pci108e,a001", PSYCHO_MODE_SABRE, "Sabre (US-IIe) compatible" }, 251 { NULL, 0, NULL } 252}; 253 254static struct psycho_desc psycho_models[] = { 255 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 256 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 257 { NULL, 0, NULL } 258}; 259 260static struct psycho_desc * 261psycho_find_desc(struct psycho_desc *table, char *string) 262{ 263 struct psycho_desc *desc; 264 265 for (desc = table; desc->pd_string != NULL; desc++) { 266 if (strcmp(desc->pd_string, string) == 0) 267 return (desc); 268 } 269 return (NULL); 270} 271 272static struct psycho_desc * 273psycho_get_desc(phandle_t node, char *model) 274{ 275 struct psycho_desc *rv; 276 char compat[32]; 277 278 rv = NULL; 279 if (model != NULL) 280 rv = psycho_find_desc(psycho_models, model); 281 if (rv == NULL && 282 OF_getprop(node, "compatible", compat, sizeof(compat)) != -1) 283 rv = psycho_find_desc(psycho_compats, compat); 284 return (rv); 285} 286 287static int 288psycho_probe(device_t dev) 289{ 290 phandle_t node; 291 char *dtype; 292 293 node = nexus_get_node(dev); 294 dtype = nexus_get_device_type(dev); 295 if (nexus_get_reg(dev) != NULL && dtype != NULL && 296 strcmp(dtype, OFW_PCI_TYPE) == 0 && 297 psycho_get_desc(node, nexus_get_model(dev)) != NULL) { 298 device_set_desc(dev, "U2P UPA-PCI bridge"); 299 return (0); 300 } 301 302 return (ENXIO); 303} 304 305/* 306 * SUNW,psycho initialisation .. 307 * - find the per-psycho registers 308 * - figure out the IGN. 309 * - find our partner psycho 310 * - configure ourselves 311 * - bus range, bus, 312 * - interrupt map, 313 * - setup the chipsets. 314 * - if we're the first of the pair, initialise the IOMMU, otherwise 315 * just copy it's tags and addresses. 316 */ 317static int 318psycho_attach(device_t dev) 319{ 320 struct psycho_softc *sc; 321 struct psycho_softc *osc = NULL; 322 struct psycho_softc *asc; 323 struct upa_regs *reg; 324#ifndef OFW_NEWPCI 325 struct ofw_pci_bdesc obd; 326#endif 327 struct psycho_desc *desc; 328 phandle_t node; 329 u_int64_t csr; 330 u_long mlen; 331 int psycho_br[2]; 332 int n, i, nreg, rid; 333#ifdef PSYCHO_DEBUG 334 bus_addr_t map, clr; 335 u_int64_t mr; 336#endif 337 338 node = nexus_get_node(dev); 339 sc = device_get_softc(dev); 340 desc = psycho_get_desc(node, nexus_get_model(dev)); 341 342 sc->sc_node = node; 343 sc->sc_dev = dev; 344 sc->sc_dmatag = nexus_get_dmatag(dev); 345 sc->sc_mode = desc->pd_mode; 346 347 /* 348 * The psycho gets three register banks: 349 * (0) per-PBM configuration and status registers 350 * (1) per-PBM PCI configuration space, containing only the 351 * PBM 256-byte PCI header 352 * (2) the shared psycho configuration registers (struct psychoreg) 353 */ 354 reg = nexus_get_reg(dev); 355 nreg = nexus_get_nreg(dev); 356 /* Register layouts are different. stuupid. */ 357 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 358 if (nreg <= 2) 359 panic("psycho_attach: %d not enough registers", nreg); 360 sc->sc_basepaddr = (vm_paddr_t)UPA_REG_PHYS(®[2]); 361 mlen = UPA_REG_SIZE(®[2]); 362 sc->sc_pcictl = UPA_REG_PHYS(®[0]) - sc->sc_basepaddr; 363 switch (sc->sc_pcictl) { 364 case PSR_PCICTL0: 365 sc->sc_half = 0; 366 break; 367 case PSR_PCICTL1: 368 sc->sc_half = 1; 369 break; 370 default: 371 panic("psycho_attach: bogus pci control register " 372 "location"); 373 } 374 } else { 375 if (nreg <= 0) 376 panic("psycho_attach: %d not enough registers", nreg); 377 sc->sc_basepaddr = (vm_paddr_t)UPA_REG_PHYS(®[0]); 378 mlen = UPA_REG_SIZE(reg); 379 sc->sc_pcictl = PSR_PCICTL0; 380 sc->sc_half = 0; 381 } 382 383 /* 384 * Match other psycho's that are already configured against 385 * the base physical address. This will be the same for a 386 * pair of devices that share register space. 387 */ 388 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 389 if (asc->sc_basepaddr == sc->sc_basepaddr) { 390 /* Found partner */ 391 osc = asc; 392 break; 393 } 394 } 395 396 if (osc == NULL) { 397 rid = 0; 398 sc->sc_mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 399 sc->sc_basepaddr, sc->sc_basepaddr + mlen - 1, mlen, 400 RF_ACTIVE); 401 if (sc->sc_mem_res == NULL || 402 rman_get_start(sc->sc_mem_res) != sc->sc_basepaddr) 403 panic("psycho_attach: can't allocate device memory"); 404 sc->sc_bustag = rman_get_bustag(sc->sc_mem_res); 405 sc->sc_bushandle = rman_get_bushandle(sc->sc_mem_res); 406 } else { 407 /* 408 * There's another psycho using the same register space. Copy the 409 * relevant stuff. 410 */ 411 sc->sc_mem_res = NULL; 412 sc->sc_bustag = osc->sc_bustag; 413 sc->sc_bushandle = osc->sc_bushandle; 414 } 415 csr = PSYCHO_READ8(sc, PSR_CS); 416 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 417 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 418 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 419 420 device_printf(dev, "%s, impl %d, version %d, ign %#x, bus %c\n", 421 desc->pd_name, (int)PSYCHO_GCSR_IMPL(csr), 422 (int)PSYCHO_GCSR_VERS(csr), sc->sc_ign, 'A' + sc->sc_half); 423 424 /* 425 * Setup the PCI control register 426 */ 427 csr = PCICTL_READ8(sc, PCR_CS); 428 csr |= PCICTL_MRLM | PCICTL_ARB_PARK | PCICTL_ERRINTEN | PCICTL_4ENABLE; 429 csr &= ~(PCICTL_SERR | PCICTL_CPU_PRIO | PCICTL_ARB_PRIO | 430 PCICTL_RTRYWAIT); 431 PCICTL_WRITE8(sc, PCR_CS, csr); 432 433 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 434 /* 435 * Use the PROM preset for now. 436 */ 437 csr = PCICTL_READ8(sc, PCR_TAS); 438 if (csr == 0) 439 panic("psycho_attach: sabre TAS not initialized."); 440 sc->sc_dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT; 441 } else 442 sc->sc_dvmabase = -1; 443 444 /* Grab the psycho ranges */ 445 psycho_get_ranges(sc->sc_node, &sc->sc_range, &sc->sc_nrange); 446 447 /* Initialize memory and i/o rmans */ 448 sc->sc_io_rman.rm_type = RMAN_ARRAY; 449 sc->sc_io_rman.rm_descr = "Psycho PCI I/O Ports"; 450 if (rman_init(&sc->sc_io_rman) != 0 || 451 rman_manage_region(&sc->sc_io_rman, 0, PSYCHO_IO_SIZE) != 0) 452 panic("psycho_probe: failed to set up i/o rman"); 453 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 454 sc->sc_mem_rman.rm_descr = "Psycho PCI Memory"; 455 if (rman_init(&sc->sc_mem_rman) != 0 || 456 rman_manage_region(&sc->sc_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 457 panic("psycho_probe: failed to set up memory rman"); 458 /* 459 * Find the addresses of the various bus spaces. 460 * There should not be multiple ones of one kind. 461 * The physical start addresses of the ranges are the configuration, 462 * memory and IO handles. 463 */ 464 for (n = 0; n < sc->sc_nrange; n++) { 465 i = UPA_RANGE_CS(&sc->sc_range[n]); 466 if (sc->sc_bh[i] != 0) 467 panic("psycho_attach: duplicate range for space %d", i); 468 sc->sc_bh[i] = UPA_RANGE_PHYS(&sc->sc_range[n]); 469 } 470 /* 471 * Check that all needed handles are present. The PCI_CS_MEM64 one is 472 * not currently used. 473 */ 474 for (n = 0; n < 3; n++) { 475 if (sc->sc_bh[n] == 0) 476 panic("psycho_attach: range %d missing", n); 477 } 478 479 /* Register the softc, this is needed for paired psychos. */ 480 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 481 482 /* 483 * If we're a sabre or the first of a pair of psycho's to arrive here, 484 * start up the IOMMU. 485 */ 486 if (osc == NULL) { 487 /* 488 * Establish handlers for interesting interrupts.... 489 * 490 * XXX We need to remember these and remove this to support 491 * hotplug on the UPA/FHC bus. 492 * 493 * XXX Not all controllers have these, but installing them 494 * is better than trying to sort through this mess. 495 */ 496 psycho_set_intr(sc, 0, dev, PSR_UE_INT_MAP, INTR_FAST, 497 psycho_ue); 498 psycho_set_intr(sc, 1, dev, PSR_CE_INT_MAP, 0, psycho_ce); 499 psycho_set_intr(sc, 2, dev, PSR_PCIAERR_INT_MAP, INTR_FAST, 500 psycho_bus_a); 501 psycho_set_intr(sc, 4, dev, PSR_POWER_INT_MAP, 502 PSYCHO_PWRFAIL_INT_FLAGS, psycho_powerfail); 503 /* Psycho-specific initialization. */ 504 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 505 /* 506 * Sabres do not have the following two interrupts. 507 */ 508 psycho_set_intr(sc, 3, dev, PSR_PCIBERR_INT_MAP, 509 INTR_FAST, psycho_bus_b); 510#ifdef PSYCHO_MAP_WAKEUP 511 /* 512 * psycho_wakeup() doesn't do anything useful right 513 * now. 514 */ 515 psycho_set_intr(sc, 5, dev, PSR_PWRMGT_INT_MAP, 0, 516 psycho_wakeup); 517#endif /* PSYCHO_MAP_WAKEUP */ 518 519 /* Initialize the counter-timer. */ 520 sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, 521 PSR_TC0); 522 } 523 524 /* 525 * Setup IOMMU and PCI configuration if we're the first 526 * of a pair of psycho's to arrive here. 527 * 528 * We should calculate a TSB size based on amount of RAM 529 * and number of bus controllers and number and type of 530 * child devices. 531 * 532 * For the moment, 32KB should be more than enough. 533 */ 534 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 535 M_NOWAIT); 536 if (sc->sc_is == NULL) 537 panic("psycho_attach: malloc iommu_state failed"); 538 sc->sc_is->is_sb[0] = 0; 539 sc->sc_is->is_sb[1] = 0; 540 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 541 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 542 psycho_iommu_init(sc, 3); 543 } else { 544 /* Just copy IOMMU state, config tag and address */ 545 sc->sc_is = osc->sc_is; 546 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 547 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 548 iommu_reset(sc->sc_is); 549 } 550 551 /* Allocate our tags. */ 552 sc->sc_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 553 sc->sc_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 554 sc->sc_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 555 if (bus_dma_tag_create(sc->sc_dmatag, 8, 1, 0, 0x3ffffffff, NULL, NULL, 556 0x3ffffffff, 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_dmat) != 0) 557 panic("psycho_attach: bus_dma_tag_create failed"); 558 /* Customize the tag. */ 559 sc->sc_dmat->dt_cookie = sc->sc_is; 560 sc->sc_dmat->dt_mt = &iommu_dma_methods; 561 /* XXX: register as root dma tag (kludge). */ 562 sparc64_root_dma_tag = sc->sc_dmat; 563 564#ifdef PSYCHO_DEBUG 565 /* 566 * Enable all interrupts and clear all interrupt states. 567 * This aids the debugging of interrupt routing problems. 568 */ 569 for (map = PSR_PCIA0_INT_MAP, clr = PSR_PCIA0_INT_CLR, n = 0; 570 map <= PSR_PCIB3_INT_MAP; map += 8, clr += 32, n++) { 571 mr = PSYCHO_READ8(sc, map); 572 device_printf(dev, "intr map (pci) %d: %#lx\n", n, (u_long)mr); 573 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 574 for (i = 0; i < 4; i++) 575 PCICTL_WRITE8(sc, clr + i * 8, 0); 576 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 577 } 578 for (map = PSR_SCSI_INT_MAP, clr = PSR_SCSI_INT_CLR, n = 0; 579 map <= PSR_SERIAL_INT_MAP; map += 8, clr += 8, n++) { 580 mr = PSYCHO_READ8(sc, map); 581 device_printf(dev, "intr map (obio) %d: %#lx, clr: %#lx\n", n, 582 (u_long)mr, (u_long)clr); 583 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 584 PSYCHO_WRITE8(sc, clr, 0); 585 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 586 } 587#endif /* PSYCHO_DEBUG */ 588 589 /* 590 * Get the bus range from the firmware; it is used solely for obtaining 591 * the inital bus number, and cannot be trusted on all machines. 592 */ 593 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br)); 594 if (n == -1) 595 panic("could not get psycho bus-range"); 596 if (n != sizeof(psycho_br)) 597 panic("broken psycho bus-range (%d)", n); 598 599 sc->sc_secbus = sc->sc_subbus = ofw_pci_alloc_busno(sc->sc_node); 600 /* 601 * Program the bus range registers. 602 * NOTE: the psycho, the second write changes the bus number the 603 * psycho itself uses for it's configuration space, so these 604 * writes must be kept in this order! 605 * The sabre always uses bus 0, but there only can be one sabre per 606 * machine. 607 */ 608 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SUBBUS, 609 sc->sc_subbus, 1); 610 PCIB_WRITE_CONFIG(dev, psycho_br[0], PCS_DEVICE, PCS_FUNC, PCSR_SECBUS, 611 sc->sc_secbus, 1); 612 613#ifdef OFW_NEWPCI 614 ofw_bus_setup_iinfo(node, &sc->sc_iinfo, sizeof(ofw_pci_intr_t)); 615#else 616 obd.obd_bus = obd.obd_secbus = sc->sc_secbus; 617 obd.obd_subbus = sc->sc_subbus; 618 obd.obd_slot = PCS_DEVICE; 619 obd.obd_func = PCS_FUNC; 620 obd.obd_init = psycho_binit; 621 obd.obd_super = NULL; 622 623 /* 624 * Initialize the interrupt registers of all devices hanging from 625 * the host bridge directly or indirectly via PCI-PCI bridges. 626 * The MI code (and the PCI spec) assume that this is done during 627 * system initialization, however the firmware does not do this 628 * at least on some models, and we probably shouldn't trust that 629 * the firmware uses the same model as this driver if it does. 630 * Additionally, set up the bus numbers and ranges. 631 */ 632 ofw_pci_init(dev, sc->sc_node, sc->sc_ign, &obd); 633#endif /* OFW_NEWPCI */ 634 635 device_add_child(dev, "pci", sc->sc_secbus); 636 return (bus_generic_attach(dev)); 637} 638 639static void 640psycho_set_intr(struct psycho_softc *sc, int index, 641 device_t dev, bus_addr_t map, int iflags, driver_intr_t handler) 642{ 643 int rid, vec; 644 u_int64_t mr; 645 646 mr = PSYCHO_READ8(sc, map); 647 vec = INTVEC(mr); 648 sc->sc_irq_res[index] = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 649 vec, vec, 1, RF_ACTIVE); 650 if (sc->sc_irq_res[index] == NULL) 651 panic("psycho_set_intr: failed to get interrupt"); 652 bus_setup_intr(dev, sc->sc_irq_res[index], INTR_TYPE_MISC | iflags, 653 handler, sc, &sc->sc_ihand[index]); 654 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 655} 656 657static int 658psycho_find_intrmap(struct psycho_softc *sc, int ino, bus_addr_t *intrmapptr, 659 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 660{ 661 bus_addr_t intrmap, intrclr; 662 u_int64_t im; 663 u_long diag; 664 int found; 665 666 found = 0; 667 /* Hunt thru obio first */ 668 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 669 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 670 intrmap <= PSR_SERIAL_INT_MAP; intrmap += 8, intrclr += 8, 671 diag >>= 2) { 672 im = PSYCHO_READ8(sc, intrmap); 673 if (INTINO(im) == ino) { 674 diag &= 2; 675 found = 1; 676 break; 677 } 678 } 679 680 if (!found) { 681 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 682 /* Now do PCI interrupts */ 683 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 684 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 685 diag >>= 8) { 686 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 687 (intrmap == PSR_PCIA2_INT_MAP || 688 intrmap == PSR_PCIA3_INT_MAP)) 689 continue; 690 im = PSYCHO_READ8(sc, intrmap); 691 if (((im ^ ino) & 0x3c) == 0) { 692 intrclr += 8 * (ino & 3); 693 diag = (diag >> ((ino & 3) * 2)) & 2; 694 found = 1; 695 break; 696 } 697 } 698 } 699 if (intrmapptr != NULL) 700 *intrmapptr = intrmap; 701 if (intrclrptr != NULL) 702 *intrclrptr = intrclr; 703 if (intrdiagptr != NULL) 704 *intrdiagptr = diag; 705 return (found); 706} 707 708/* grovel the OBP for various psycho properties */ 709static void 710psycho_get_ranges(phandle_t node, struct upa_ranges **rp, int *np) 711{ 712 713 *np = OF_getprop_alloc(node, "ranges", sizeof(**rp), (void **)rp); 714 if (*np == -1) 715 panic("could not get psycho ranges"); 716} 717 718/* 719 * Interrupt handlers. 720 */ 721static void 722psycho_ue(void *arg) 723{ 724 struct psycho_softc *sc = (struct psycho_softc *)arg; 725 u_int64_t afar, afsr; 726 727 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 728 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 729 /* 730 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 731 * the AFAR to be set to the physical address of the TTE entry that 732 * was invalid/write protected. Call into the iommu code to have 733 * them decoded to virtual IO addresses. 734 */ 735 if ((afsr & UEAFSR_P_DTE) != 0) 736 iommu_decode_fault(sc->sc_is, afar); 737 /* It's uncorrectable. Dump the regs and panic. */ 738 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx", 739 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 740} 741 742static void 743psycho_ce(void *arg) 744{ 745 struct psycho_softc *sc = (struct psycho_softc *)arg; 746 u_int64_t afar, afsr; 747 748 PSYCHO_WRITE8(sc, PSR_CE_INT_CLR, 0); 749 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 750 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 751 /* It's correctable. Dump the regs and continue. */ 752 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx " 753 "AFSR %#lx\n", (u_long)afar, (u_long)afsr); 754} 755 756static void 757psycho_bus_a(void *arg) 758{ 759 struct psycho_softc *sc = (struct psycho_softc *)arg; 760 u_int64_t afar, afsr; 761 762 afar = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFA); 763 afsr = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFS); 764 /* It's uncorrectable. Dump the regs and panic. */ 765 panic("%s: PCI bus A error AFAR %#lx AFSR %#lx", 766 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 767} 768 769static void 770psycho_bus_b(void *arg) 771{ 772 struct psycho_softc *sc = (struct psycho_softc *)arg; 773 u_int64_t afar, afsr; 774 775 afar = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFA); 776 afsr = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFS); 777 /* It's uncorrectable. Dump the regs and panic. */ 778 panic("%s: PCI bus B error AFAR %#lx AFSR %#lx", 779 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 780} 781 782static void 783psycho_powerfail(void *arg) 784{ 785 786 /* We lost power. Try to shut down NOW. */ 787#ifdef DEBUGGER_ON_POWERFAIL 788 struct psycho_softc *sc = (struct psycho_softc *)arg; 789 790 Debugger("powerfail"); 791 PSYCHO_WRITE8(sc, PSR_POWER_INT_CLR, 0); 792#else 793 printf("Power Failure Detected: Shutting down NOW.\n"); 794 shutdown_nice(0); 795#endif 796} 797 798#ifdef PSYCHO_MAP_WAKEUP 799static void 800psycho_wakeup(void *arg) 801{ 802 struct psycho_softc *sc = (struct psycho_softc *)arg; 803 804 PSYCHO_WRITE8(sc, PSR_PWRMGT_INT_CLR, 0); 805 /* Gee, we don't really have a framework to deal with this properly. */ 806 device_printf(sc->sc_dev, "power management wakeup\n"); 807} 808#endif /* PSYCHO_MAP_WAKEUP */ 809 810/* initialise the IOMMU... */ 811void 812psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 813{ 814 char *name; 815 struct iommu_state *is = sc->sc_is; 816 817 /* punch in our copies */ 818 is->is_bustag = sc->sc_bustag; 819 is->is_bushandle = sc->sc_bushandle; 820 is->is_iommu = PSR_IOMMU; 821 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 822 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 823 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 824 is->is_dva = PSR_IOMMU_SVADIAG; 825 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 826 827 /* give us a nice name.. */ 828 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 829 if (name == 0) 830 panic("couldn't malloc iommu name"); 831 snprintf(name, 32, "%s dvma", device_get_name(sc->sc_dev)); 832 833 iommu_init(name, is, tsbsize, sc->sc_dvmabase, 0); 834} 835 836#ifndef OFW_NEWPCI 837static void 838psycho_binit(device_t busdev, struct ofw_pci_bdesc *obd) 839{ 840 841#ifdef PSYCHO_DEBUG 842 printf("psycho at %u/%u/%u: setting bus #s to %u/%u/%u\n", 843 obd->obd_bus, obd->obd_slot, obd->obd_func, obd->obd_bus, 844 obd->obd_secbus, obd->obd_subbus); 845#endif /* PSYCHO_DEBUG */ 846 PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func, 847 PCSR_SUBBUS, obd->obd_subbus, 1); 848} 849#endif 850 851static int 852psycho_maxslots(device_t dev) 853{ 854 855 /* XXX: is this correct? */ 856 return (PCI_SLOTMAX); 857} 858 859#ifndef OFW_NEWPCI 860/* 861 * Keep a table of quirky PCI devices that need fixups before the MI PCI code 862 * creates the resource lists. This needs to be moved around once other bus 863 * drivers are added. Moving it to the MI code should maybe be reconsidered 864 * if one of these devices appear in non-sparc64 boxen. It's likely that not 865 * all BIOSes/firmwares can deal with them. 866 */ 867struct psycho_dquirk { 868 u_int32_t dq_devid; 869 int dq_quirk; 870}; 871 872/* Quirk types. May be or'ed together. */ 873#define DQT_BAD_INTPIN 1 /* Intpin reg 0, but intpin used */ 874 875static struct psycho_dquirk dquirks[] = { 876 { 0x1001108e, DQT_BAD_INTPIN }, /* Sun HME (PCIO func. 1) */ 877 { 0x1101108e, DQT_BAD_INTPIN }, /* Sun GEM (PCIO2 func. 1) */ 878 { 0x1102108e, DQT_BAD_INTPIN }, /* Sun FireWire ctl. (PCIO2 func. 2) */ 879 { 0x1103108e, DQT_BAD_INTPIN }, /* Sun USB ctl. (PCIO2 func. 3) */ 880}; 881#endif /* !OFW_NEWPCI */ 882 883#define NDQUIRKS (sizeof(dquirks) / sizeof(dquirks[0])) 884 885static u_int32_t 886psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 887 int width) 888{ 889 struct psycho_softc *sc; 890 bus_space_handle_t bh; 891 u_long offset = 0; 892#ifndef OFW_NEWPCI 893 u_int32_t devid; 894#endif 895 u_int8_t byte; 896 u_int16_t shrt; 897 u_int32_t wrd; 898 u_int32_t r; 899 int i; 900 901 sc = (struct psycho_softc *)device_get_softc(dev); 902 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 903 bh = sc->sc_bh[PCI_CS_CONFIG]; 904 switch (width) { 905 case 1: 906 i = bus_space_peek_1(sc->sc_cfgt, bh, offset, &byte); 907 r = byte; 908 break; 909 case 2: 910 i = bus_space_peek_2(sc->sc_cfgt, bh, offset, &shrt); 911 r = shrt; 912 break; 913 case 4: 914 i = bus_space_peek_4(sc->sc_cfgt, bh, offset, &wrd); 915 r = wrd; 916 break; 917 default: 918 panic("psycho_read_config: bad width"); 919 } 920 921 if (i) { 922#ifdef PSYCHO_DEBUG 923 printf("psycho read data error reading: %d.%d.%d: 0x%x\n", 924 bus, slot, func, reg); 925#endif 926 r = -1; 927 } 928 929#ifndef OFW_NEWPCI 930 if (reg == PCIR_INTPIN && r == 0) { 931 /* Check for DQT_BAD_INTPIN quirk. */ 932 devid = psycho_read_config(dev, bus, slot, func, 933 PCIR_DEVVENDOR, 4); 934 for (i = 0; i < NDQUIRKS; i++) { 935 if (dquirks[i].dq_devid == devid) { 936 /* 937 * Need to set the intpin to a value != 0 so 938 * that the MI code will think that this device 939 * has an interrupt. 940 * Just use 1 (intpin a) for now. This is, of 941 * course, bogus, but since interrupts are 942 * routed in advance, this does not really 943 * matter. 944 */ 945 if ((dquirks[i].dq_quirk & DQT_BAD_INTPIN) != 0) 946 r = 1; 947 break; 948 } 949 } 950 } 951#endif /* !OFW_NEWPCI */ 952 return (r); 953} 954 955static void 956psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, 957 u_int reg, u_int32_t val, int width) 958{ 959 struct psycho_softc *sc; 960 bus_space_handle_t bh; 961 u_long offset = 0; 962 963 sc = (struct psycho_softc *)device_get_softc(dev); 964 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 965 bh = sc->sc_bh[PCI_CS_CONFIG]; 966 switch (width) { 967 case 1: 968 bus_space_write_1(sc->sc_cfgt, bh, offset, val); 969 break; 970 case 2: 971 bus_space_write_2(sc->sc_cfgt, bh, offset, val); 972 break; 973 case 4: 974 bus_space_write_4(sc->sc_cfgt, bh, offset, val); 975 break; 976 default: 977 panic("psycho_write_config: bad width"); 978 } 979} 980 981static int 982psycho_route_interrupt(device_t bridge, device_t dev, int pin) 983{ 984#ifdef OFW_NEWPCI 985 struct psycho_softc *sc = device_get_softc(bridge); 986 struct ofw_pci_register reg; 987 bus_addr_t intrmap; 988 phandle_t node = ofw_pci_get_node(dev); 989 ofw_pci_intr_t pintr, mintr; 990 u_int8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 991 992 pintr = pin; 993 if (ofw_bus_lookup_imap(node, &sc->sc_iinfo, ®, sizeof(reg), 994 &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) 995 return (mintr); 996 /* 997 * If this is outside of the range for an intpin, it's likely a full 998 * INO, and no mapping is required at all; this happens on the u30, 999 * where there's no interrupt map at the psycho node. Fortunately, 1000 * there seem to be no INOs in the intpin range on this boxen, so 1001 * this easy heuristics will do. 1002 */ 1003 if (pin > 4) 1004 return (pin); 1005 /* 1006 * Guess the INO; we always assume that this is a non-OBIO 1007 * device, and that pin is a "real" intpin number. Determine 1008 * the mapping register to be used by the slot number. 1009 * We only need to do this on e450s, it seems; here, the slot numbers 1010 * for bus A are one-based, while those for bus B seemingly have an 1011 * offset of 2 (hence the factor of 3 below). 1012 */ 1013 intrmap = PSR_PCIA0_INT_MAP + 1014 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half); 1015 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1; 1016 device_printf(bridge, "guessing interrupt %d for device %d/%d pin %d\n", 1017 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin); 1018 return (mintr); 1019#else 1020 /* 1021 * XXX: ugly loathsome hack: 1022 * We can't use ofw_pci_route_intr() here; the device passed may be 1023 * the one of a bridge, so the original device can't be recovered. 1024 * 1025 * We need to use the firmware to route interrupts, however it has 1026 * no interface which could be used to interpret intpins; instead, 1027 * all assignments are done by device. 1028 * 1029 * The MI pci code will try to reroute interrupts of 0, although they 1030 * are correct; all other interrupts are preinitialized, so if we 1031 * get here, the intline is either 0 (so return 0), or we hit a 1032 * device which was not preinitialized (e.g. hotplugged stuff), in 1033 * which case we are lost. 1034 */ 1035 return (0); 1036#endif /* OFW_NEWPCI */ 1037} 1038 1039static int 1040psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1041{ 1042 struct psycho_softc *sc; 1043 1044 sc = (struct psycho_softc *)device_get_softc(dev); 1045 switch (which) { 1046 case PCIB_IVAR_BUS: 1047 *result = sc->sc_secbus; 1048 return (0); 1049 } 1050 return (ENOENT); 1051} 1052 1053/* Write to the correct clr register, and call the actual handler. */ 1054static void 1055psycho_intr_stub(void *arg) 1056{ 1057 struct psycho_clr *pc; 1058 1059 pc = (struct psycho_clr *)arg; 1060 pc->pci_handler(pc->pci_arg); 1061 PSYCHO_WRITE8(pc->pci_sc, pc->pci_clr, 0); 1062} 1063 1064static int 1065psycho_setup_intr(device_t dev, device_t child, 1066 struct resource *ires, int flags, driver_intr_t *intr, void *arg, 1067 void **cookiep) 1068{ 1069 struct psycho_softc *sc; 1070 struct psycho_clr *pc; 1071 bus_addr_t intrmapptr, intrclrptr; 1072 long vec = rman_get_start(ires); 1073 u_int64_t mr; 1074 int ino, error; 1075 1076 sc = (struct psycho_softc *)device_get_softc(dev); 1077 pc = (struct psycho_clr *)malloc(sizeof(*pc), M_DEVBUF, M_NOWAIT); 1078 if (pc == NULL) 1079 return (NULL); 1080 1081 /* 1082 * Hunt through all the interrupt mapping regs to look for our 1083 * interrupt vector. 1084 * 1085 * XXX We only compare INOs rather than IGNs since the firmware may 1086 * not provide the IGN and the IGN is constant for all device on that 1087 * PCI controller. This could cause problems for the FFB/external 1088 * interrupt which has a full vector that can be set arbitrarily. 1089 */ 1090 ino = INTINO(vec); 1091 1092 if (!psycho_find_intrmap(sc, ino, &intrmapptr, &intrclrptr, NULL)) { 1093 device_printf(dev, "Cannot find interrupt vector %lx\n", vec); 1094 free(pc, M_DEVBUF); 1095 return (NULL); 1096 } 1097 1098#ifdef PSYCHO_DEBUG 1099 device_printf(dev, "psycho_setup_intr: INO %d, map %#lx, clr %#lx\n", 1100 ino, (u_long)intrmapptr, (u_long)intrclrptr); 1101#endif 1102 pc->pci_sc = sc; 1103 pc->pci_arg = arg; 1104 pc->pci_handler = intr; 1105 pc->pci_clr = intrclrptr; 1106 /* Disable the interrupt while we fiddle with it */ 1107 mr = PSYCHO_READ8(sc, intrmapptr); 1108 PSYCHO_WRITE8(sc, intrmapptr, mr & ~INTMAP_V); 1109 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 1110 psycho_intr_stub, pc, cookiep); 1111 if (error != 0) { 1112 free(pc, M_DEVBUF); 1113 return (error); 1114 } 1115 pc->pci_cookie = *cookiep; 1116 *cookiep = pc; 1117 1118 /* 1119 * Clear the interrupt, it might have been triggered before it was 1120 * set up. 1121 */ 1122 PSYCHO_WRITE8(sc, intrclrptr, 0); 1123 /* 1124 * Enable the interrupt and program the target module now we have the 1125 * handler installed. 1126 */ 1127 PSYCHO_WRITE8(sc, intrmapptr, INTMAP_ENABLE(mr, PCPU_GET(mid))); 1128 return (error); 1129} 1130 1131static int 1132psycho_teardown_intr(device_t dev, device_t child, 1133 struct resource *vec, void *cookie) 1134{ 1135 struct psycho_clr *pc; 1136 int error; 1137 1138 pc = (struct psycho_clr *)cookie; 1139 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 1140 pc->pci_cookie); 1141 /* 1142 * Don't disable the interrupt for now, so that stray interupts get 1143 * detected... 1144 */ 1145 if (error != 0) 1146 free(pc, M_DEVBUF); 1147 return (error); 1148} 1149 1150static struct resource * 1151psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1152 u_long start, u_long end, u_long count, u_int flags) 1153{ 1154 struct psycho_softc *sc; 1155 struct resource *rv; 1156 struct rman *rm; 1157 bus_space_tag_t bt; 1158 bus_space_handle_t bh; 1159 int needactivate = flags & RF_ACTIVE; 1160 1161 flags &= ~RF_ACTIVE; 1162 1163 sc = (struct psycho_softc *)device_get_softc(bus); 1164 if (type == SYS_RES_IRQ) { 1165 /* 1166 * XXX: Don't accept blank ranges for now, only single 1167 * interrupts. The other case should not happen with the MI pci 1168 * code... 1169 * XXX: This may return a resource that is out of the range 1170 * that was specified. Is this correct...? 1171 */ 1172 if (start != end) 1173 panic("psycho_alloc_resource: XXX: interrupt range"); 1174 start = end |= sc->sc_ign; 1175 return (bus_alloc_resource(bus, type, rid, start, end, 1176 count, flags)); 1177 } 1178 switch (type) { 1179 case SYS_RES_MEMORY: 1180 rm = &sc->sc_mem_rman; 1181 bt = sc->sc_memt; 1182 bh = sc->sc_bh[PCI_CS_MEM32]; 1183 break; 1184 case SYS_RES_IOPORT: 1185 rm = &sc->sc_io_rman; 1186 bt = sc->sc_iot; 1187 bh = sc->sc_bh[PCI_CS_IO]; 1188 break; 1189 default: 1190 return (NULL); 1191 } 1192 1193 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1194 if (rv == NULL) 1195 return (NULL); 1196 1197 bh += rman_get_start(rv); 1198 rman_set_bustag(rv, bt); 1199 rman_set_bushandle(rv, bh); 1200 1201 if (needactivate) { 1202 if (bus_activate_resource(child, type, *rid, rv)) { 1203 rman_release_resource(rv); 1204 return (NULL); 1205 } 1206 } 1207 1208 return (rv); 1209} 1210 1211static int 1212psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1213 struct resource *r) 1214{ 1215 void *p; 1216 int error; 1217 1218 if (type == SYS_RES_IRQ) 1219 return (bus_activate_resource(bus, type, rid, r)); 1220 if (type == SYS_RES_MEMORY) { 1221 /* 1222 * Need to memory-map the device space, as some drivers depend 1223 * on the virtual address being set and useable. 1224 */ 1225 error = sparc64_bus_mem_map(rman_get_bustag(r), 1226 rman_get_bushandle(r), rman_get_size(r), 0, NULL, &p); 1227 if (error != 0) 1228 return (error); 1229 rman_set_virtual(r, p); 1230 } 1231 return (rman_activate_resource(r)); 1232} 1233 1234static int 1235psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1236 struct resource *r) 1237{ 1238 1239 if (type == SYS_RES_IRQ) 1240 return (bus_deactivate_resource(bus, type, rid, r)); 1241 if (type == SYS_RES_MEMORY) { 1242 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1243 rman_set_virtual(r, NULL); 1244 } 1245 return (rman_deactivate_resource(r)); 1246} 1247 1248static int 1249psycho_release_resource(device_t bus, device_t child, int type, int rid, 1250 struct resource *r) 1251{ 1252 int error; 1253 1254 if (type == SYS_RES_IRQ) 1255 return (bus_release_resource(bus, type, rid, r)); 1256 if (rman_get_flags(r) & RF_ACTIVE) { 1257 error = bus_deactivate_resource(child, type, rid, r); 1258 if (error) 1259 return error; 1260 } 1261 return (rman_release_resource(r)); 1262} 1263 1264static int 1265psycho_intr_pending(device_t dev, ofw_pci_intr_t intr) 1266{ 1267 struct psycho_softc *sc; 1268 u_long diag; 1269 1270 sc = (struct psycho_softc *)device_get_softc(dev); 1271 if (!psycho_find_intrmap(sc, intr, NULL, NULL, &diag)) { 1272 device_printf(dev, "psycho_intr_pending: mapping not found for" 1273 " %d\n", intr); 1274 return (0); 1275 } 1276 return (diag != 0); 1277} 1278 1279#ifndef OFW_NEWPCI 1280static ofw_pci_intr_t 1281psycho_guess_ino(device_t dev, phandle_t node, u_int slot, u_int pin) 1282{ 1283 struct psycho_softc *sc = (struct psycho_softc *)device_get_softc(dev); 1284 bus_addr_t intrmap; 1285 1286 /* 1287 * If this is not for one of our direct children (i.e. we are mapping 1288 * at our node), tell the interrupt mapper to go on - we need the 1289 * slot number of the device or it's topmost parent bridge to guess 1290 * the INO. 1291 */ 1292 if (node != sc->sc_node) 1293 return (PCI_INVALID_IRQ); 1294 /* 1295 * Actually guess the INO. We always assume that this is a non-OBIO 1296 * device, and use from the slot number to determine it. 1297 * We only need to do this on e450s, it seems; here, the slot numbers 1298 * for bus A are one-based, while those for bus B seemingly have an 1299 * offset of 2 (hence the factor of 3 below). 1300 */ 1301 intrmap = PSR_PCIA0_INT_MAP + 8 * (slot - 1 + 3 * sc->sc_half); 1302 return (INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1); 1303} 1304#endif /* !OFW_NEWPCI */ 1305 1306static bus_space_handle_t 1307psycho_get_bus_handle(device_t dev, int type, bus_space_handle_t childhdl, 1308 bus_space_tag_t *tag) 1309{ 1310 struct psycho_softc *sc; 1311 1312 sc = (struct psycho_softc *)device_get_softc(dev); 1313 switch (type) { 1314 case SYS_RES_IOPORT: 1315 *tag = sc->sc_iot; 1316 return (sc->sc_bh[PCI_CS_IO] + childhdl); 1317 case SYS_RES_MEMORY: 1318 *tag = sc->sc_memt; 1319 return (sc->sc_bh[PCI_CS_MEM32] + childhdl); 1320 default: 1321 panic("psycho_get_bus_handle: illegal space\n"); 1322 } 1323} 1324 1325#ifdef OFW_NEWPCI 1326static phandle_t 1327psycho_get_node(device_t bus, device_t dev) 1328{ 1329 struct psycho_softc *sc = device_get_softc(bus); 1330 1331 /* We only have one child, the PCI bus, which needs our own node. */ 1332 return (sc->sc_node); 1333} 1334 1335static void 1336psycho_adjust_busrange(device_t dev, u_int subbus) 1337{ 1338 struct psycho_softc *sc = device_get_softc(dev); 1339 1340 /* If necessary, adjust the subordinate bus number register. */ 1341 if (subbus > sc->sc_subbus) { 1342#ifdef PSYCHO_DEBUG 1343 device_printf(dev, 1344 "adjusting secondary bus number from %d to %d\n", 1345 sc->sc_subbus, subbus); 1346#endif 1347 sc->sc_subbus = subbus; 1348 PCIB_WRITE_CONFIG(dev, sc->sc_secbus, PCS_DEVICE, PCS_FUNC, 1349 PCSR_SUBBUS, subbus, 1); 1350 } 1351} 1352#endif 1353 1354/* 1355 * below here is bus space and bus dma support 1356 */ 1357static bus_space_tag_t 1358psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1359{ 1360 bus_space_tag_t bt; 1361 1362 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1363 M_NOWAIT | M_ZERO); 1364 if (bt == NULL) 1365 panic("psycho_alloc_bus_tag: out of memory"); 1366 1367 bzero(bt, sizeof *bt); 1368 bt->bst_cookie = sc; 1369 bt->bst_parent = sc->sc_bustag; 1370 bt->bst_type = type; 1371 return (bt); 1372} 1373