psycho.c revision 116659
1/* 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * All rights reserved. 4 * Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 30 * 31 * $FreeBSD: head/sys/sparc64/pci/psycho.c 116659 2003-06-22 01:26:08Z jmg $ 32 */ 33 34/* 35 * Support for `psycho' and `psycho+' UPA to PCI bridge and 36 * UltraSPARC IIi and IIe `sabre' PCI controllers. 37 */ 38 39#include "opt_psycho.h" 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/kernel.h> 45#include <sys/malloc.h> 46#include <sys/pcpu.h> 47 48#include <ofw/openfirm.h> 49#include <ofw/ofw_pci.h> 50 51#include <machine/bus.h> 52#include <machine/bus_private.h> 53#include <machine/iommureg.h> 54#include <machine/bus_common.h> 55#include <machine/frame.h> 56#include <machine/intr_machdep.h> 57#include <machine/nexusvar.h> 58#include <machine/ofw_upa.h> 59#include <machine/resource.h> 60#include <machine/cpu.h> 61 62#include <sys/rman.h> 63 64#include <machine/iommuvar.h> 65 66#include <pci/pcivar.h> 67#include <pci/pcireg.h> 68 69#include <sparc64/pci/ofw_pci.h> 70#include <sparc64/pci/psychoreg.h> 71#include <sparc64/pci/psychovar.h> 72 73#include "pcib_if.h" 74#include "sparcbus_if.h" 75 76static void psycho_get_ranges(phandle_t, struct upa_ranges **, int *); 77static void psycho_set_intr(struct psycho_softc *, int, device_t, bus_addr_t, 78 int, driver_intr_t); 79static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *, 80 bus_addr_t *, u_long *); 81static void psycho_intr_stub(void *); 82static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 83 84 85/* Interrupt handlers */ 86static void psycho_ue(void *); 87static void psycho_ce(void *); 88static void psycho_bus_a(void *); 89static void psycho_bus_b(void *); 90static void psycho_powerfail(void *); 91#ifdef PSYCHO_MAP_WAKEUP 92static void psycho_wakeup(void *); 93#endif 94 95/* IOMMU support */ 96static void psycho_iommu_init(struct psycho_softc *, int); 97static ofw_pci_binit_t psycho_binit; 98 99/* 100 * autoconfiguration 101 */ 102static int psycho_probe(device_t); 103static int psycho_attach(device_t); 104static int psycho_read_ivar(device_t, device_t, int, u_long *); 105static int psycho_setup_intr(device_t, device_t, struct resource *, int, 106 driver_intr_t *, void *, void **); 107static int psycho_teardown_intr(device_t, device_t, struct resource *, void *); 108static struct resource *psycho_alloc_resource(device_t, device_t, int, int *, 109 u_long, u_long, u_long, u_int); 110static int psycho_activate_resource(device_t, device_t, int, int, 111 struct resource *); 112static int psycho_deactivate_resource(device_t, device_t, int, int, 113 struct resource *); 114static int psycho_release_resource(device_t, device_t, int, int, 115 struct resource *); 116static int psycho_maxslots(device_t); 117static u_int32_t psycho_read_config(device_t, u_int, u_int, u_int, u_int, int); 118static void psycho_write_config(device_t, u_int, u_int, u_int, u_int, u_int32_t, 119 int); 120static int psycho_route_interrupt(device_t, device_t, int); 121static int psycho_intr_pending(device_t, int); 122static u_int32_t psycho_guess_ino(device_t, phandle_t, u_int, u_int); 123static bus_space_handle_t psycho_get_bus_handle(device_t dev, enum sbbt_id id, 124 bus_space_handle_t childhdl, bus_space_tag_t *tag); 125 126static device_method_t psycho_methods[] = { 127 /* Device interface */ 128 DEVMETHOD(device_probe, psycho_probe), 129 DEVMETHOD(device_attach, psycho_attach), 130 131 /* Bus interface */ 132 DEVMETHOD(bus_print_child, bus_generic_print_child), 133 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 134 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 135 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 136 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 137 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 138 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 139 DEVMETHOD(bus_release_resource, psycho_release_resource), 140 141 /* pcib interface */ 142 DEVMETHOD(pcib_maxslots, psycho_maxslots), 143 DEVMETHOD(pcib_read_config, psycho_read_config), 144 DEVMETHOD(pcib_write_config, psycho_write_config), 145 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 146 147 /* sparcbus interface */ 148 DEVMETHOD(sparcbus_intr_pending, psycho_intr_pending), 149 DEVMETHOD(sparcbus_guess_ino, psycho_guess_ino), 150 DEVMETHOD(sparcbus_get_bus_handle, psycho_get_bus_handle), 151 152 { 0, 0 } 153}; 154 155static driver_t psycho_driver = { 156 "pcib", 157 psycho_methods, 158 sizeof(struct psycho_softc), 159}; 160 161static devclass_t psycho_devclass; 162 163DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 164 165SLIST_HEAD(, psycho_softc) psycho_softcs = 166 SLIST_HEAD_INITIALIZER(psycho_softcs); 167 168struct psycho_clr { 169 struct psycho_softc *pci_sc; 170 bus_addr_t pci_clr; /* clear register */ 171 driver_intr_t *pci_handler; /* handler to call */ 172 void *pci_arg; /* argument for the handler */ 173 void *pci_cookie; /* interrupt cookie of parent bus */ 174}; 175 176struct psycho_strayclr { 177 struct psycho_softc *psc_sc; 178 bus_addr_t psc_clr; /* clear register */ 179}; 180 181#define PSYCHO_READ8(sc, off) \ 182 bus_space_read_8((sc)->sc_bustag, (sc)->sc_bushandle, (off)) 183#define PSYCHO_WRITE8(sc, off, v) \ 184 bus_space_write_8((sc)->sc_bustag, (sc)->sc_bushandle, (off), (v)) 185#define PCICTL_READ8(sc, off) \ 186 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 187#define PCICTL_WRITE8(sc, off, v) \ 188 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 189 190/* 191 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 192 * single PCI bus and does not have a streaming buffer. It often has an APB 193 * (advanced PCI bridge) connected to it, which was designed specifically for 194 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 195 * appears as two "simba"'s underneath the sabre. 196 * 197 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 198 * and manages two PCI buses. "psycho" has two 64-bit 33MHz buses, while 199 * "psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 200 * will usually find a "psycho+" since I don't think the original "psycho" 201 * ever shipped, and if it did it would be in the U30. 202 * 203 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 204 * both part of the same IC, they only have a single register space. As such, 205 * they need to be configured together, even though the autoconfiguration will 206 * attach them separately. 207 * 208 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 209 * as pci1 and pci2, although they have been implemented with other PCI bus 210 * numbers on some machines. 211 * 212 * On UltraII machines, there can be any number of "psycho+" ICs, each 213 * providing two PCI buses. 214 * 215 * 216 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 217 * the values of the following interrupts in this order: 218 * 219 * PCI Bus Error (30) 220 * DMA UE (2e) 221 * DMA CE (2f) 222 * Power Fail (25) 223 * 224 * We really should attach handlers for each. 225 */ 226#ifdef DEBUGGER_ON_POWERFAIL 227#define PSYCHO_PWRFAIL_INT_FLAGS INTR_FAST 228#else 229#define PSYCHO_PWRFAIL_INT_FLAGS 0 230#endif 231 232#define OFW_PCI_TYPE "pci" 233 234struct psycho_desc { 235 char *pd_string; 236 int pd_mode; 237 char *pd_name; 238}; 239 240static struct psycho_desc psycho_compats[] = { 241 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 242 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre (US-IIi) compatible" }, 243 { "pci108e,a001", PSYCHO_MODE_SABRE, "Sabre (US-IIe) compatible" }, 244 { NULL, 0, NULL } 245}; 246 247static struct psycho_desc psycho_models[] = { 248 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 249 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 250 { NULL, 0, NULL } 251}; 252 253static struct psycho_desc * 254psycho_find_desc(struct psycho_desc *table, char *string) 255{ 256 struct psycho_desc *desc; 257 258 for (desc = table; desc->pd_string != NULL; desc++) { 259 if (strcmp(desc->pd_string, string) == 0) 260 return (desc); 261 } 262 return (NULL); 263} 264 265static struct psycho_desc * 266psycho_get_desc(phandle_t node, char *model) 267{ 268 struct psycho_desc *rv; 269 char compat[32]; 270 271 rv = NULL; 272 if (model != NULL) 273 rv = psycho_find_desc(psycho_models, model); 274 if (rv == NULL && 275 OF_getprop(node, "compatible", compat, sizeof(compat)) != -1) 276 rv = psycho_find_desc(psycho_compats, compat); 277 return (rv); 278} 279 280static int 281psycho_probe(device_t dev) 282{ 283 phandle_t node; 284 char *dtype; 285 286 node = nexus_get_node(dev); 287 dtype = nexus_get_device_type(dev); 288 if (nexus_get_reg(dev) != NULL && dtype != NULL && 289 strcmp(dtype, OFW_PCI_TYPE) == 0 && 290 psycho_get_desc(node, nexus_get_model(dev)) != NULL) { 291 device_set_desc(dev, "U2P UPA-PCI bridge"); 292 return (0); 293 } 294 295 return (ENXIO); 296} 297 298/* 299 * SUNW,psycho initialisation .. 300 * - find the per-psycho registers 301 * - figure out the IGN. 302 * - find our partner psycho 303 * - configure ourselves 304 * - bus range, bus, 305 * - interrupt map, 306 * - setup the chipsets. 307 * - if we're the first of the pair, initialise the IOMMU, otherwise 308 * just copy it's tags and addresses. 309 */ 310static int 311psycho_attach(device_t dev) 312{ 313 struct psycho_softc *sc; 314 struct psycho_softc *osc = NULL; 315 struct psycho_softc *asc; 316 struct upa_regs *reg; 317 struct ofw_pci_bdesc obd; 318 struct psycho_desc *desc; 319 phandle_t node; 320 u_int64_t csr; 321 u_long mlen; 322 int psycho_br[2]; 323 int n, i, nreg, rid; 324#ifdef PSYCHO_DEBUG 325 bus_addr_t map, clr; 326 u_int64_t mr; 327#endif 328 329 node = nexus_get_node(dev); 330 sc = device_get_softc(dev); 331 desc = psycho_get_desc(node, nexus_get_model(dev)); 332 333 sc->sc_node = node; 334 sc->sc_dev = dev; 335 sc->sc_dmatag = nexus_get_dmatag(dev); 336 sc->sc_mode = desc->pd_mode; 337 338 /* 339 * The psycho gets three register banks: 340 * (0) per-PBM configuration and status registers 341 * (1) per-PBM PCI configuration space, containing only the 342 * PBM 256-byte PCI header 343 * (2) the shared psycho configuration registers (struct psychoreg) 344 */ 345 reg = nexus_get_reg(dev); 346 nreg = nexus_get_nreg(dev); 347 /* Register layouts are different. stuupid. */ 348 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 349 if (nreg <= 2) 350 panic("psycho_attach: %d not enough registers", nreg); 351 sc->sc_basepaddr = (vm_paddr_t)UPA_REG_PHYS(®[2]); 352 mlen = UPA_REG_SIZE(®[2]); 353 sc->sc_pcictl = UPA_REG_PHYS(®[0]) - sc->sc_basepaddr; 354 switch (sc->sc_pcictl) { 355 case PSR_PCICTL0: 356 sc->sc_half = 0; 357 break; 358 case PSR_PCICTL1: 359 sc->sc_half = 1; 360 break; 361 default: 362 panic("psycho_attach: bogus pci control register " 363 "location"); 364 } 365 } else { 366 if (nreg <= 0) 367 panic("psycho_attach: %d not enough registers", nreg); 368 sc->sc_basepaddr = (vm_paddr_t)UPA_REG_PHYS(®[0]); 369 mlen = UPA_REG_SIZE(reg); 370 sc->sc_pcictl = PSR_PCICTL0; 371 sc->sc_half = 0; 372 } 373 374 /* 375 * Match other psycho's that are already configured against 376 * the base physical address. This will be the same for a 377 * pair of devices that share register space. 378 */ 379 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 380 if (asc->sc_basepaddr == sc->sc_basepaddr) { 381 /* Found partner */ 382 osc = asc; 383 break; 384 } 385 } 386 387 if (osc == NULL) { 388 rid = 0; 389 sc->sc_mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 390 sc->sc_basepaddr, sc->sc_basepaddr + mlen - 1, mlen, 391 RF_ACTIVE); 392 if (sc->sc_mem_res == NULL || 393 rman_get_start(sc->sc_mem_res) != sc->sc_basepaddr) 394 panic("psycho_attach: can't allocate device memory"); 395 sc->sc_bustag = rman_get_bustag(sc->sc_mem_res); 396 sc->sc_bushandle = rman_get_bushandle(sc->sc_mem_res); 397 } else { 398 /* 399 * There's another psycho using the same register space. Copy the 400 * relevant stuff. 401 */ 402 sc->sc_mem_res = NULL; 403 sc->sc_bustag = osc->sc_bustag; 404 sc->sc_bushandle = osc->sc_bushandle; 405 } 406 csr = PSYCHO_READ8(sc, PSR_CS); 407 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 408 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 409 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 410 411 device_printf(dev, "%s, impl %d, version %d, ign %#x, bus %c\n", 412 desc->pd_name, (int)PSYCHO_GCSR_IMPL(csr), 413 (int)PSYCHO_GCSR_VERS(csr), sc->sc_ign, 'A' + sc->sc_half); 414 415 /* 416 * Setup the PCI control register 417 */ 418 csr = PCICTL_READ8(sc, PCR_CS); 419 csr |= PCICTL_MRLM | PCICTL_ARB_PARK | PCICTL_ERRINTEN | PCICTL_4ENABLE; 420 csr &= ~(PCICTL_SERR | PCICTL_CPU_PRIO | PCICTL_ARB_PRIO | 421 PCICTL_RTRYWAIT); 422 PCICTL_WRITE8(sc, PCR_CS, csr); 423 424 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 425 /* 426 * Use the PROM preset for now. 427 */ 428 csr = PCICTL_READ8(sc, PCR_TAS); 429 if (csr == 0) 430 panic("psycho_attach: sabre TAS not initialized."); 431 sc->sc_dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT; 432 } else 433 sc->sc_dvmabase = -1; 434 435 /* Grab the psycho ranges */ 436 psycho_get_ranges(sc->sc_node, &sc->sc_range, &sc->sc_nrange); 437 438 /* Initialize memory and i/o rmans */ 439 sc->sc_io_rman.rm_type = RMAN_ARRAY; 440 sc->sc_io_rman.rm_descr = "Psycho PCI I/O Ports"; 441 if (rman_init(&sc->sc_io_rman) != 0 || 442 rman_manage_region(&sc->sc_io_rman, 0, PSYCHO_IO_SIZE) != 0) 443 panic("psycho_probe: failed to set up i/o rman"); 444 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 445 sc->sc_mem_rman.rm_descr = "Psycho PCI Memory"; 446 if (rman_init(&sc->sc_mem_rman) != 0 || 447 rman_manage_region(&sc->sc_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 448 panic("psycho_probe: failed to set up memory rman"); 449 /* 450 * Find the addresses of the various bus spaces. 451 * There should not be multiple ones of one kind. 452 * The physical start addresses of the ranges are the configuration, 453 * memory and IO handles. 454 */ 455 for (n = 0; n < sc->sc_nrange; n++) { 456 i = UPA_RANGE_CS(&sc->sc_range[n]); 457 if (sc->sc_bh[i] != 0) 458 panic("psycho_attach: duplicate range for space %d", i); 459 sc->sc_bh[i] = UPA_RANGE_PHYS(&sc->sc_range[n]); 460 } 461 /* 462 * Check that all needed handles are present. The PCI_CS_MEM64 one is 463 * not currently used. 464 */ 465 for (n = 0; n < 3; n++) { 466 if (sc->sc_bh[n] == 0) 467 panic("psycho_attach: range %d missing", n); 468 } 469 470 /* Register the softc, this is needed for paired psychos. */ 471 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 472 473 /* 474 * If we're a sabre or the first of a pair of psycho's to arrive here, 475 * start up the IOMMU. 476 */ 477 if (osc == NULL) { 478 /* 479 * Establish handlers for interesting interrupts.... 480 * 481 * XXX We need to remember these and remove this to support 482 * hotplug on the UPA/FHC bus. 483 * 484 * XXX Not all controllers have these, but installing them 485 * is better than trying to sort through this mess. 486 */ 487 psycho_set_intr(sc, 0, dev, PSR_UE_INT_MAP, INTR_FAST, 488 psycho_ue); 489 psycho_set_intr(sc, 1, dev, PSR_CE_INT_MAP, 0, psycho_ce); 490 psycho_set_intr(sc, 2, dev, PSR_PCIAERR_INT_MAP, INTR_FAST, 491 psycho_bus_a); 492 psycho_set_intr(sc, 4, dev, PSR_POWER_INT_MAP, 493 PSYCHO_PWRFAIL_INT_FLAGS, psycho_powerfail); 494 /* Psycho-specific initialization. */ 495 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 496 /* 497 * Sabres do not have the following two interrupts. 498 */ 499 psycho_set_intr(sc, 3, dev, PSR_PCIBERR_INT_MAP, 500 INTR_FAST, psycho_bus_b); 501#ifdef PSYCHO_MAP_WAKEUP 502 /* 503 * psycho_wakeup() doesn't do anything useful right 504 * now. 505 */ 506 psycho_set_intr(sc, 5, dev, PSR_PWRMGT_INT_MAP, 0, 507 psycho_wakeup); 508#endif /* PSYCHO_MAP_WAKEUP */ 509 510 /* Initialize the counter-timer. */ 511 sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, 512 PSR_TC0); 513 } 514 515 /* 516 * Setup IOMMU and PCI configuration if we're the first 517 * of a pair of psycho's to arrive here. 518 * 519 * We should calculate a TSB size based on amount of RAM 520 * and number of bus controllers and number and type of 521 * child devices. 522 * 523 * For the moment, 32KB should be more than enough. 524 */ 525 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 526 M_NOWAIT); 527 if (sc->sc_is == NULL) 528 panic("psycho_attach: malloc iommu_state failed"); 529 sc->sc_is->is_sb[0] = 0; 530 sc->sc_is->is_sb[1] = 0; 531 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 532 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 533 psycho_iommu_init(sc, 3); 534 } else { 535 /* Just copy IOMMU state, config tag and address */ 536 sc->sc_is = osc->sc_is; 537 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 538 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 539 iommu_reset(sc->sc_is); 540 } 541 542 /* Allocate our tags. */ 543 sc->sc_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 544 sc->sc_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 545 sc->sc_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 546 if (bus_dma_tag_create(sc->sc_dmatag, 8, 1, 0, 0x3ffffffff, NULL, NULL, 547 0x3ffffffff, 0xff, 0xffffffff, 0, &sc->sc_dmat) != 0) 548 panic("psycho_attach: bus_dma_tag_create failed"); 549 /* Customize the tag. */ 550 sc->sc_dmat->dt_cookie = sc->sc_is; 551 sc->sc_dmat->dt_mt = &iommu_dma_methods; 552 /* XXX: register as root dma tag (kludge). */ 553 sparc64_root_dma_tag = sc->sc_dmat; 554 555#ifdef PSYCHO_DEBUG 556 /* 557 * Enable all interrupts and clear all interrupt states. 558 * This aids the debugging of interrupt routing problems. 559 */ 560 for (map = PSR_PCIA0_INT_MAP, clr = PSR_PCIA0_INT_CLR, n = 0; 561 map <= PSR_PCIB3_INT_MAP; map += 8, clr += 32, n++) { 562 mr = PSYCHO_READ8(sc, map); 563 device_printf(dev, "intr map (pci) %d: %#lx\n", n, (u_long)mr); 564 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 565 for (i = 0; i < 4; i++) 566 PCICTL_WRITE8(sc, clr + i * 8, 0); 567 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 568 } 569 for (map = PSR_SCSI_INT_MAP, clr = PSR_SCSI_INT_CLR, n = 0; 570 map <= PSR_SERIAL_INT_MAP; map += 8, clr += 8, n++) { 571 mr = PSYCHO_READ8(sc, map); 572 device_printf(dev, "intr map (obio) %d: %#lx, clr: %#lx\n", n, 573 (u_long)mr, (u_long)clr); 574 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 575 PSYCHO_WRITE8(sc, clr, 0); 576 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 577 } 578#endif /* PSYCHO_DEBUG */ 579 580 /* 581 * Get the bus range from the firmware; it is used solely for obtaining 582 * the inital bus number, and cannot be trusted on all machines. 583 */ 584 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br)); 585 if (n == -1) 586 panic("could not get psycho bus-range"); 587 if (n != sizeof(psycho_br)) 588 panic("broken psycho bus-range (%d)", n); 589 590 sc->sc_busno = ofw_pci_alloc_busno(sc->sc_node); 591 obd.obd_bus = psycho_br[0]; 592 obd.obd_secbus = obd.obd_subbus = sc->sc_busno; 593 obd.obd_slot = PCS_DEVICE; 594 obd.obd_func = PCS_FUNC; 595 obd.obd_init = psycho_binit; 596 obd.obd_super = NULL; 597 /* Initial setup. */ 598 psycho_binit(dev, &obd); 599 /* Update the bus number to what was just programmed. */ 600 obd.obd_bus = obd.obd_secbus; 601 /* 602 * Initialize the interrupt registers of all devices hanging from 603 * the host bridge directly or indirectly via PCI-PCI bridges. 604 * The MI code (and the PCI spec) assume that this is done during 605 * system initialization, however the firmware does not do this 606 * at least on some models, and we probably shouldn't trust that 607 * the firmware uses the same model as this driver if it does. 608 * Additionally, set up the bus numbers and ranges. 609 */ 610 ofw_pci_init(dev, sc->sc_node, sc->sc_ign, &obd); 611 612 device_add_child(dev, "pci", device_get_unit(dev)); 613 return (bus_generic_attach(dev)); 614} 615 616static void 617psycho_set_intr(struct psycho_softc *sc, int index, 618 device_t dev, bus_addr_t map, int iflags, driver_intr_t handler) 619{ 620 int rid, vec; 621 u_int64_t mr; 622 623 mr = PSYCHO_READ8(sc, map); 624 vec = INTVEC(mr); 625 sc->sc_irq_res[index] = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 626 vec, vec, 1, RF_ACTIVE); 627 if (sc->sc_irq_res[index] == NULL) 628 panic("psycho_set_intr: failed to get interrupt"); 629 bus_setup_intr(dev, sc->sc_irq_res[index], INTR_TYPE_MISC | iflags, 630 handler, sc, &sc->sc_ihand[index]); 631 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 632} 633 634static int 635psycho_find_intrmap(struct psycho_softc *sc, int ino, bus_addr_t *intrmapptr, 636 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 637{ 638 bus_addr_t intrmap, intrclr; 639 u_int64_t im; 640 u_long diag; 641 int found; 642 643 found = 0; 644 /* Hunt thru obio first */ 645 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 646 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 647 intrmap <= PSR_SERIAL_INT_MAP; intrmap += 8, intrclr += 8, 648 diag >>= 2) { 649 im = PSYCHO_READ8(sc, intrmap); 650 if (INTINO(im) == ino) { 651 diag &= 2; 652 found = 1; 653 break; 654 } 655 } 656 657 if (!found) { 658 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 659 /* Now do PCI interrupts */ 660 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 661 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 662 diag >>= 8) { 663 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 664 (intrmap == PSR_PCIA2_INT_MAP || 665 intrmap == PSR_PCIA3_INT_MAP)) 666 continue; 667 im = PSYCHO_READ8(sc, intrmap); 668 if (((im ^ ino) & 0x3c) == 0) { 669 intrclr += 8 * (ino & 3); 670 diag = (diag >> ((ino & 3) * 2)) & 2; 671 found = 1; 672 break; 673 } 674 } 675 } 676 if (intrmapptr != NULL) 677 *intrmapptr = intrmap; 678 if (intrclrptr != NULL) 679 *intrclrptr = intrclr; 680 if (intrdiagptr != NULL) 681 *intrdiagptr = diag; 682 return (found); 683} 684 685/* grovel the OBP for various psycho properties */ 686static void 687psycho_get_ranges(phandle_t node, struct upa_ranges **rp, int *np) 688{ 689 690 *np = OF_getprop_alloc(node, "ranges", sizeof(**rp), (void **)rp); 691 if (*np == -1) 692 panic("could not get psycho ranges"); 693} 694 695/* 696 * Interrupt handlers. 697 */ 698static void 699psycho_ue(void *arg) 700{ 701 struct psycho_softc *sc = (struct psycho_softc *)arg; 702 u_int64_t afar, afsr; 703 704 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 705 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 706 /* 707 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 708 * the AFAR to be set to the physical address of the TTE entry that 709 * was invalid/write protected. Call into the iommu code to have 710 * them decoded to virtual IO addresses. 711 */ 712 if ((afsr & UEAFSR_P_DTE) != 0) 713 iommu_decode_fault(sc->sc_is, afar); 714 /* It's uncorrectable. Dump the regs and panic. */ 715 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx", 716 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 717} 718 719static void 720psycho_ce(void *arg) 721{ 722 struct psycho_softc *sc = (struct psycho_softc *)arg; 723 u_int64_t afar, afsr; 724 725 PSYCHO_WRITE8(sc, PSR_CE_INT_CLR, 0); 726 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 727 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 728 /* It's correctable. Dump the regs and continue. */ 729 printf("%s: correctable DMA error AFAR %#lx AFSR %#lx\n", 730 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 731} 732 733static void 734psycho_bus_a(void *arg) 735{ 736 struct psycho_softc *sc = (struct psycho_softc *)arg; 737 u_int64_t afar, afsr; 738 739 afar = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFA); 740 afsr = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFS); 741 /* It's uncorrectable. Dump the regs and panic. */ 742 panic("%s: PCI bus A error AFAR %#lx AFSR %#lx", 743 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 744} 745 746static void 747psycho_bus_b(void *arg) 748{ 749 struct psycho_softc *sc = (struct psycho_softc *)arg; 750 u_int64_t afar, afsr; 751 752 afar = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFA); 753 afsr = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFS); 754 /* It's uncorrectable. Dump the regs and panic. */ 755 panic("%s: PCI bus B error AFAR %#lx AFSR %#lx", 756 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 757} 758 759static void 760psycho_powerfail(void *arg) 761{ 762 763 /* We lost power. Try to shut down NOW. */ 764#ifdef DEBUGGER_ON_POWERFAIL 765 struct psycho_softc *sc = (struct psycho_softc *)arg; 766 767 Debugger("powerfail"); 768 PSYCHO_WRITE8(sc, PSR_POWER_INT_CLR, 0); 769#else 770 printf("Power Failure Detected: Shutting down NOW.\n"); 771 shutdown_nice(0); 772#endif 773} 774 775#ifdef PSYCHO_MAP_WAKEUP 776static void 777psycho_wakeup(void *arg) 778{ 779 struct psycho_softc *sc = (struct psycho_softc *)arg; 780 781 PSYCHO_WRITE8(sc, PSR_PWRMGT_INT_CLR, 0); 782 /* Gee, we don't really have a framework to deal with this properly. */ 783 printf("%s: power management wakeup\n", device_get_name(sc->sc_dev)); 784} 785#endif /* PSYCHO_MAP_WAKEUP */ 786 787/* initialise the IOMMU... */ 788void 789psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 790{ 791 char *name; 792 struct iommu_state *is = sc->sc_is; 793 794 /* punch in our copies */ 795 is->is_bustag = sc->sc_bustag; 796 is->is_bushandle = sc->sc_bushandle; 797 is->is_iommu = PSR_IOMMU; 798 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 799 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 800 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 801 is->is_dva = PSR_IOMMU_SVADIAG; 802 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 803 804 /* give us a nice name.. */ 805 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 806 if (name == 0) 807 panic("couldn't malloc iommu name"); 808 snprintf(name, 32, "%s dvma", device_get_name(sc->sc_dev)); 809 810 iommu_init(name, is, tsbsize, sc->sc_dvmabase, 0); 811} 812 813static void 814psycho_binit(device_t busdev, struct ofw_pci_bdesc *obd) 815{ 816 817#ifdef PSYCHO_DEBUG 818 printf("psycho at %u/%u/%u: setting bus #s to %u/%u/%u\n", 819 obd->obd_bus, obd->obd_slot, obd->obd_func, obd->obd_bus, 820 obd->obd_secbus, obd->obd_subbus); 821#endif /* PSYCHO_DEBUG */ 822 /* 823 * NOTE: this must be kept in this order, since the last write will 824 * change the config space address of the psycho. 825 */ 826 PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func, 827 PCSR_SUBBUS, obd->obd_subbus, 1); 828 PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func, 829 PCSR_SECBUS, obd->obd_secbus, 1); 830} 831 832static int 833psycho_maxslots(device_t dev) 834{ 835 836 /* 837 * XXX: is this correct? At any rate, a number that is too high 838 * shouldn't do any harm, if only because of the way things are 839 * handled in psycho_read_config. 840 */ 841 return (31); 842} 843 844/* 845 * Keep a table of quirky PCI devices that need fixups before the MI PCI code 846 * creates the resource lists. This needs to be moved around once other bus 847 * drivers are added. Moving it to the MI code should maybe be reconsidered 848 * if one of these devices appear in non-sparc64 boxen. It's likely that not 849 * all BIOSes/firmwares can deal with them. 850 */ 851struct psycho_dquirk { 852 u_int32_t dq_devid; 853 int dq_quirk; 854}; 855 856/* Quirk types. May be or'ed together. */ 857#define DQT_BAD_INTPIN 1 /* Intpin reg 0, but intpin used */ 858 859static struct psycho_dquirk dquirks[] = { 860 { 0x1001108e, DQT_BAD_INTPIN }, /* Sun HME (PCIO func. 1) */ 861 { 0x1101108e, DQT_BAD_INTPIN }, /* Sun GEM (PCIO2 func. 1) */ 862 { 0x1102108e, DQT_BAD_INTPIN }, /* Sun FireWire ctl. (PCIO2 func. 2) */ 863 { 0x1103108e, DQT_BAD_INTPIN }, /* Sun USB ctl. (PCIO2 func. 3) */ 864}; 865 866#define NDQUIRKS (sizeof(dquirks) / sizeof(dquirks[0])) 867 868static u_int32_t 869psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 870 int width) 871{ 872 struct psycho_softc *sc; 873 bus_space_handle_t bh; 874 u_long offset = 0; 875 u_int32_t r, devid; 876 u_int8_t byte; 877 u_int16_t shrt; 878 u_int32_t wrd; 879 int i; 880 881 sc = (struct psycho_softc *)device_get_softc(dev); 882 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 883 bh = sc->sc_bh[PCI_CS_CONFIG]; 884 switch (width) { 885 case 1: 886 i = bus_space_peek_1(sc->sc_cfgt, bh, offset, &byte); 887 r = byte; 888 break; 889 case 2: 890 i = bus_space_peek_2(sc->sc_cfgt, bh, offset, &shrt); 891 r = shrt; 892 break; 893 case 4: 894 i = bus_space_peek_4(sc->sc_cfgt, bh, offset, &wrd); 895 r = wrd; 896 break; 897 default: 898 panic("psycho_read_config: bad width"); 899 } 900 901 if (i) { 902#ifdef PSYCHO_DEBUG 903 printf("psycho read data error reading: %d.%d.%d: 0x%x\n", 904 bus, slot, func, reg); 905#endif 906 r = -1; 907 } 908 909 if (reg == PCIR_INTPIN && r == 0) { 910 /* Check for DQT_BAD_INTPIN quirk. */ 911 devid = psycho_read_config(dev, bus, slot, func, 912 PCIR_DEVVENDOR, 4); 913 for (i = 0; i < NDQUIRKS; i++) { 914 if (dquirks[i].dq_devid == devid) { 915 /* 916 * Need to set the intpin to a value != 0 so 917 * that the MI code will think that this device 918 * has an interrupt. 919 * Just use 1 (intpin a) for now. This is, of 920 * course, bogus, but since interrupts are 921 * routed in advance, this does not really 922 * matter. 923 */ 924 if ((dquirks[i].dq_quirk & DQT_BAD_INTPIN) != 0) 925 r = 1; 926 break; 927 } 928 } 929 } 930 return (r); 931} 932 933static void 934psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, 935 u_int reg, u_int32_t val, int width) 936{ 937 struct psycho_softc *sc; 938 bus_space_handle_t bh; 939 u_long offset = 0; 940 941 sc = (struct psycho_softc *)device_get_softc(dev); 942 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 943 bh = sc->sc_bh[PCI_CS_CONFIG]; 944 switch (width) { 945 case 1: 946 bus_space_write_1(sc->sc_cfgt, bh, offset, val); 947 break; 948 case 2: 949 bus_space_write_2(sc->sc_cfgt, bh, offset, val); 950 break; 951 case 4: 952 bus_space_write_4(sc->sc_cfgt, bh, offset, val); 953 break; 954 default: 955 panic("psycho_write_config: bad width"); 956 } 957} 958 959static int 960psycho_route_interrupt(device_t bus, device_t dev, int pin) 961{ 962 963 /* 964 * XXX: ugly loathsome hack: 965 * We can't use ofw_pci_route_intr() here; the device passed may be 966 * the one of a bridge, so the original device can't be recovered. 967 * 968 * We need to use the firmware to route interrupts, however it has 969 * no interface which could be used to interpret intpins; instead, 970 * all assignments are done by device. 971 * 972 * The MI pci code will try to reroute interrupts of 0, although they 973 * are correct; all other interrupts are preinitialized, so if we 974 * get here, the intline is either 0 (so return 0), or we hit a 975 * device which was not preinitialized (e.g. hotplugged stuff), in 976 * which case we are lost. 977 */ 978 return (0); 979} 980 981static int 982psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 983{ 984 struct psycho_softc *sc; 985 986 sc = (struct psycho_softc *)device_get_softc(dev); 987 switch (which) { 988 case PCIB_IVAR_BUS: 989 *result = sc->sc_busno; 990 return (0); 991 } 992 return (ENOENT); 993} 994 995/* Write to the correct clr register, and call the actual handler. */ 996static void 997psycho_intr_stub(void *arg) 998{ 999 struct psycho_clr *pc; 1000 1001 pc = (struct psycho_clr *)arg; 1002 pc->pci_handler(pc->pci_arg); 1003 PSYCHO_WRITE8(pc->pci_sc, pc->pci_clr, 0); 1004} 1005 1006static int 1007psycho_setup_intr(device_t dev, device_t child, 1008 struct resource *ires, int flags, driver_intr_t *intr, void *arg, 1009 void **cookiep) 1010{ 1011 struct psycho_softc *sc; 1012 struct psycho_clr *pc; 1013 bus_addr_t intrmapptr, intrclrptr; 1014 long vec = rman_get_start(ires); 1015 u_int64_t mr; 1016 int ino, error; 1017 1018 sc = (struct psycho_softc *)device_get_softc(dev); 1019 pc = (struct psycho_clr *)malloc(sizeof(*pc), M_DEVBUF, M_NOWAIT); 1020 if (pc == NULL) 1021 return (NULL); 1022 1023 /* 1024 * Hunt through all the interrupt mapping regs to look for our 1025 * interrupt vector. 1026 * 1027 * XXX We only compare INOs rather than IGNs since the firmware may 1028 * not provide the IGN and the IGN is constant for all device on that 1029 * PCI controller. This could cause problems for the FFB/external 1030 * interrupt which has a full vector that can be set arbitrarily. 1031 */ 1032 ino = INTINO(vec); 1033 1034 if (!psycho_find_intrmap(sc, ino, &intrmapptr, &intrclrptr, NULL)) { 1035 printf("Cannot find interrupt vector %lx\n", vec); 1036 free(pc, M_DEVBUF); 1037 return (NULL); 1038 } 1039 1040#ifdef PSYCHO_DEBUG 1041 device_printf(dev, "psycho_setup_intr: INO %d, map %#lx, clr %#lx\n", 1042 ino, (u_long)intrmapptr, (u_long)intrclrptr); 1043#endif 1044 pc->pci_sc = sc; 1045 pc->pci_arg = arg; 1046 pc->pci_handler = intr; 1047 pc->pci_clr = intrclrptr; 1048 /* Disable the interrupt while we fiddle with it */ 1049 mr = PSYCHO_READ8(sc, intrmapptr); 1050 PSYCHO_WRITE8(sc, intrmapptr, mr & ~INTMAP_V); 1051 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 1052 psycho_intr_stub, pc, cookiep); 1053 if (error != 0) { 1054 free(pc, M_DEVBUF); 1055 return (error); 1056 } 1057 pc->pci_cookie = *cookiep; 1058 *cookiep = pc; 1059 1060 /* 1061 * Clear the interrupt, it might have been triggered before it was 1062 * set up. 1063 */ 1064 PSYCHO_WRITE8(sc, intrclrptr, 0); 1065 /* 1066 * Enable the interrupt and program the target module now we have the 1067 * handler installed. 1068 */ 1069 PSYCHO_WRITE8(sc, intrmapptr, INTMAP_ENABLE(mr, PCPU_GET(mid))); 1070 return (error); 1071} 1072 1073static int 1074psycho_teardown_intr(device_t dev, device_t child, 1075 struct resource *vec, void *cookie) 1076{ 1077 struct psycho_clr *pc; 1078 int error; 1079 1080 pc = (struct psycho_clr *)cookie; 1081 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 1082 pc->pci_cookie); 1083 /* 1084 * Don't disable the interrupt for now, so that stray interupts get 1085 * detected... 1086 */ 1087 if (error != 0) 1088 free(pc, M_DEVBUF); 1089 return (error); 1090} 1091 1092static struct resource * 1093psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1094 u_long start, u_long end, u_long count, u_int flags) 1095{ 1096 struct psycho_softc *sc; 1097 struct resource *rv; 1098 struct rman *rm; 1099 bus_space_tag_t bt; 1100 bus_space_handle_t bh; 1101 int needactivate = flags & RF_ACTIVE; 1102 1103 flags &= ~RF_ACTIVE; 1104 1105 sc = (struct psycho_softc *)device_get_softc(bus); 1106 if (type == SYS_RES_IRQ) { 1107 /* 1108 * XXX: Don't accept blank ranges for now, only single 1109 * interrupts. The other case should not happen with the MI pci 1110 * code... 1111 * XXX: This may return a resource that is out of the range 1112 * that was specified. Is this correct...? 1113 */ 1114 if (start != end) 1115 panic("psycho_alloc_resource: XXX: interrupt range"); 1116 start = end |= sc->sc_ign; 1117 return (bus_alloc_resource(bus, type, rid, start, end, 1118 count, flags)); 1119 } 1120 switch (type) { 1121 case SYS_RES_MEMORY: 1122 rm = &sc->sc_mem_rman; 1123 bt = sc->sc_memt; 1124 bh = sc->sc_bh[PCI_CS_MEM32]; 1125 break; 1126 case SYS_RES_IOPORT: 1127 rm = &sc->sc_io_rman; 1128 bt = sc->sc_iot; 1129 bh = sc->sc_bh[PCI_CS_IO]; 1130 break; 1131 default: 1132 return (NULL); 1133 } 1134 1135 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1136 if (rv == NULL) 1137 return (NULL); 1138 1139 bh += rman_get_start(rv); 1140 rman_set_bustag(rv, bt); 1141 rman_set_bushandle(rv, bh); 1142 1143 if (needactivate) { 1144 if (bus_activate_resource(child, type, *rid, rv)) { 1145 rman_release_resource(rv); 1146 return (NULL); 1147 } 1148 } 1149 1150 return (rv); 1151} 1152 1153static int 1154psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1155 struct resource *r) 1156{ 1157 void *p; 1158 int error; 1159 1160 if (type == SYS_RES_IRQ) 1161 return (bus_activate_resource(bus, type, rid, r)); 1162 if (type == SYS_RES_MEMORY) { 1163 /* 1164 * Need to memory-map the device space, as some drivers depend 1165 * on the virtual address being set and useable. 1166 */ 1167 error = sparc64_bus_mem_map(rman_get_bustag(r), 1168 rman_get_bushandle(r), rman_get_size(r), 0, NULL, &p); 1169 if (error != 0) 1170 return (error); 1171 rman_set_virtual(r, p); 1172 } 1173 return (rman_activate_resource(r)); 1174} 1175 1176static int 1177psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1178 struct resource *r) 1179{ 1180 1181 if (type == SYS_RES_IRQ) 1182 return (bus_deactivate_resource(bus, type, rid, r)); 1183 if (type == SYS_RES_MEMORY) { 1184 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1185 rman_set_virtual(r, NULL); 1186 } 1187 return (rman_deactivate_resource(r)); 1188} 1189 1190static int 1191psycho_release_resource(device_t bus, device_t child, int type, int rid, 1192 struct resource *r) 1193{ 1194 int error; 1195 1196 if (type == SYS_RES_IRQ) 1197 return (bus_release_resource(bus, type, rid, r)); 1198 if (rman_get_flags(r) & RF_ACTIVE) { 1199 error = bus_deactivate_resource(child, type, rid, r); 1200 if (error) 1201 return error; 1202 } 1203 return (rman_release_resource(r)); 1204} 1205 1206static int 1207psycho_intr_pending(device_t dev, int intr) 1208{ 1209 struct psycho_softc *sc; 1210 u_long diag; 1211 1212 sc = (struct psycho_softc *)device_get_softc(dev); 1213 if (!psycho_find_intrmap(sc, intr, NULL, NULL, &diag)) { 1214 printf("psycho_intr_pending: mapping not found for %d\n", intr); 1215 return (0); 1216 } 1217 return (diag != 0); 1218} 1219 1220static u_int32_t 1221psycho_guess_ino(device_t dev, phandle_t node, u_int slot, u_int pin) 1222{ 1223 struct psycho_softc *sc = (struct psycho_softc *)device_get_softc(dev); 1224 bus_addr_t intrmap; 1225 1226 /* 1227 * If this is not for one of our direct children (i.e. we are mapping 1228 * at our node), tell the interrupt mapper to go on - we need the 1229 * slot number of the device or it's topmost parent bridge to guess 1230 * the INO. 1231 */ 1232 if (node != sc->sc_node) 1233 return (255); 1234 /* 1235 * Actually guess the INO. We always assume that this is a non-OBIO 1236 * device, and use from the slot number to determine it. 1237 * We only need to do this on e450s, it seems; here, the slot numbers 1238 * for bus A are one-based, while those for bus B seemingly have an 1239 * offset of 2 (hence the factor of 3 below). 1240 */ 1241 intrmap = PSR_PCIA0_INT_MAP + 8 * (slot - 1 + 3 * sc->sc_half); 1242 return (INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1); 1243} 1244 1245static bus_space_handle_t 1246psycho_get_bus_handle(device_t dev, enum sbbt_id id, 1247 bus_space_handle_t childhdl, bus_space_tag_t *tag) 1248{ 1249 struct psycho_softc *sc; 1250 1251 sc = (struct psycho_softc *)device_get_softc(dev); 1252 switch(id) { 1253 case SBBT_IO: 1254 *tag = sc->sc_iot; 1255 return (sc->sc_bh[PCI_CS_IO] + childhdl); 1256 case SBBT_MEM: 1257 *tag = sc->sc_memt; 1258 return (sc->sc_bh[PCI_CS_MEM32] + childhdl); 1259 default: 1260 panic("psycho_get_bus_handle: illegal space\n"); 1261 } 1262} 1263 1264/* 1265 * below here is bus space and bus dma support 1266 */ 1267static bus_space_tag_t 1268psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1269{ 1270 bus_space_tag_t bt; 1271 1272 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1273 M_NOWAIT | M_ZERO); 1274 if (bt == NULL) 1275 panic("psycho_alloc_bus_tag: out of memory"); 1276 1277 bzero(bt, sizeof *bt); 1278 bt->bst_cookie = sc; 1279 bt->bst_parent = sc->sc_bustag; 1280 bt->bst_type = type; 1281 return (bt); 1282} 1283