psycho.c revision 116541
1/* 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * All rights reserved. 4 * Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 30 * 31 * $FreeBSD: head/sys/sparc64/pci/psycho.c 116541 2003-06-18 16:41:36Z tmm $ 32 */ 33 34/* 35 * Support for `psycho' and `psycho+' UPA to PCI bridge and 36 * UltraSPARC IIi and IIe `sabre' PCI controllers. 37 */ 38 39#include "opt_psycho.h" 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/kernel.h> 45#include <sys/malloc.h> 46#include <sys/pcpu.h> 47 48#include <ofw/openfirm.h> 49#include <ofw/ofw_pci.h> 50 51#include <machine/bus.h> 52#include <machine/bus_private.h> 53#include <machine/iommureg.h> 54#include <machine/bus_common.h> 55#include <machine/frame.h> 56#include <machine/intr_machdep.h> 57#include <machine/nexusvar.h> 58#include <machine/ofw_upa.h> 59#include <machine/resource.h> 60 61#include <sys/rman.h> 62 63#include <machine/iommuvar.h> 64 65#include <pci/pcivar.h> 66#include <pci/pcireg.h> 67 68#include <sparc64/pci/ofw_pci.h> 69#include <sparc64/pci/psychoreg.h> 70#include <sparc64/pci/psychovar.h> 71 72#include "pcib_if.h" 73#include "sparcbus_if.h" 74 75static void psycho_get_ranges(phandle_t, struct upa_ranges **, int *); 76static void psycho_set_intr(struct psycho_softc *, int, device_t, bus_addr_t, 77 int, driver_intr_t); 78static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *, 79 bus_addr_t *, u_long *); 80static void psycho_intr_stub(void *); 81static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 82 83 84/* Interrupt handlers */ 85static void psycho_ue(void *); 86static void psycho_ce(void *); 87static void psycho_bus_a(void *); 88static void psycho_bus_b(void *); 89static void psycho_powerfail(void *); 90#ifdef PSYCHO_MAP_WAKEUP 91static void psycho_wakeup(void *); 92#endif 93 94/* IOMMU support */ 95static void psycho_iommu_init(struct psycho_softc *, int); 96static ofw_pci_binit_t psycho_binit; 97 98/* 99 * autoconfiguration 100 */ 101static int psycho_probe(device_t); 102static int psycho_attach(device_t); 103static int psycho_read_ivar(device_t, device_t, int, u_long *); 104static int psycho_setup_intr(device_t, device_t, struct resource *, int, 105 driver_intr_t *, void *, void **); 106static int psycho_teardown_intr(device_t, device_t, struct resource *, void *); 107static struct resource *psycho_alloc_resource(device_t, device_t, int, int *, 108 u_long, u_long, u_long, u_int); 109static int psycho_activate_resource(device_t, device_t, int, int, 110 struct resource *); 111static int psycho_deactivate_resource(device_t, device_t, int, int, 112 struct resource *); 113static int psycho_release_resource(device_t, device_t, int, int, 114 struct resource *); 115static int psycho_maxslots(device_t); 116static u_int32_t psycho_read_config(device_t, u_int, u_int, u_int, u_int, int); 117static void psycho_write_config(device_t, u_int, u_int, u_int, u_int, u_int32_t, 118 int); 119static int psycho_route_interrupt(device_t, device_t, int); 120static int psycho_intr_pending(device_t, int); 121static u_int32_t psycho_guess_ino(device_t, phandle_t, u_int, u_int); 122static bus_space_handle_t psycho_get_bus_handle(device_t dev, enum sbbt_id id, 123 bus_space_handle_t childhdl, bus_space_tag_t *tag); 124 125static device_method_t psycho_methods[] = { 126 /* Device interface */ 127 DEVMETHOD(device_probe, psycho_probe), 128 DEVMETHOD(device_attach, psycho_attach), 129 130 /* Bus interface */ 131 DEVMETHOD(bus_print_child, bus_generic_print_child), 132 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 133 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 134 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 135 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 136 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 137 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 138 DEVMETHOD(bus_release_resource, psycho_release_resource), 139 140 /* pcib interface */ 141 DEVMETHOD(pcib_maxslots, psycho_maxslots), 142 DEVMETHOD(pcib_read_config, psycho_read_config), 143 DEVMETHOD(pcib_write_config, psycho_write_config), 144 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 145 146 /* sparcbus interface */ 147 DEVMETHOD(sparcbus_intr_pending, psycho_intr_pending), 148 DEVMETHOD(sparcbus_guess_ino, psycho_guess_ino), 149 DEVMETHOD(sparcbus_get_bus_handle, psycho_get_bus_handle), 150 151 { 0, 0 } 152}; 153 154static driver_t psycho_driver = { 155 "pcib", 156 psycho_methods, 157 sizeof(struct psycho_softc), 158}; 159 160static devclass_t psycho_devclass; 161 162DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 163 164SLIST_HEAD(, psycho_softc) psycho_softcs = 165 SLIST_HEAD_INITIALIZER(psycho_softcs); 166 167struct psycho_clr { 168 struct psycho_softc *pci_sc; 169 bus_addr_t pci_clr; /* clear register */ 170 driver_intr_t *pci_handler; /* handler to call */ 171 void *pci_arg; /* argument for the handler */ 172 void *pci_cookie; /* interrupt cookie of parent bus */ 173}; 174 175struct psycho_strayclr { 176 struct psycho_softc *psc_sc; 177 bus_addr_t psc_clr; /* clear register */ 178}; 179 180#define PSYCHO_READ8(sc, off) \ 181 bus_space_read_8((sc)->sc_bustag, (sc)->sc_bushandle, (off)) 182#define PSYCHO_WRITE8(sc, off, v) \ 183 bus_space_write_8((sc)->sc_bustag, (sc)->sc_bushandle, (off), (v)) 184#define PCICTL_READ8(sc, off) \ 185 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 186#define PCICTL_WRITE8(sc, off, v) \ 187 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 188 189/* 190 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 191 * single PCI bus and does not have a streaming buffer. It often has an APB 192 * (advanced PCI bridge) connected to it, which was designed specifically for 193 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 194 * appears as two "simba"'s underneath the sabre. 195 * 196 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 197 * and manages two PCI buses. "psycho" has two 64-bit 33MHz buses, while 198 * "psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 199 * will usually find a "psycho+" since I don't think the original "psycho" 200 * ever shipped, and if it did it would be in the U30. 201 * 202 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 203 * both part of the same IC, they only have a single register space. As such, 204 * they need to be configured together, even though the autoconfiguration will 205 * attach them separately. 206 * 207 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 208 * as pci1 and pci2, although they have been implemented with other PCI bus 209 * numbers on some machines. 210 * 211 * On UltraII machines, there can be any number of "psycho+" ICs, each 212 * providing two PCI buses. 213 * 214 * 215 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 216 * the values of the following interrupts in this order: 217 * 218 * PCI Bus Error (30) 219 * DMA UE (2e) 220 * DMA CE (2f) 221 * Power Fail (25) 222 * 223 * We really should attach handlers for each. 224 */ 225#ifdef DEBUGGER_ON_POWERFAIL 226#define PSYCHO_PWRFAIL_INT_FLAGS INTR_FAST 227#else 228#define PSYCHO_PWRFAIL_INT_FLAGS 0 229#endif 230 231#define OFW_PCI_TYPE "pci" 232 233struct psycho_desc { 234 char *pd_string; 235 int pd_mode; 236 char *pd_name; 237}; 238 239static struct psycho_desc psycho_compats[] = { 240 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 241 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre (US-IIi) compatible" }, 242 { "pci108e,a001", PSYCHO_MODE_SABRE, "Sabre (US-IIe) compatible" }, 243 { NULL, 0, NULL } 244}; 245 246static struct psycho_desc psycho_models[] = { 247 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 248 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 249 { NULL, 0, NULL } 250}; 251 252static struct psycho_desc * 253psycho_find_desc(struct psycho_desc *table, char *string) 254{ 255 struct psycho_desc *desc; 256 257 for (desc = table; desc->pd_string != NULL; desc++) { 258 if (strcmp(desc->pd_string, string) == 0) 259 return (desc); 260 } 261 return (NULL); 262} 263 264static struct psycho_desc * 265psycho_get_desc(phandle_t node, char *model) 266{ 267 struct psycho_desc *rv; 268 char compat[32]; 269 270 rv = NULL; 271 if (model != NULL) 272 rv = psycho_find_desc(psycho_models, model); 273 if (rv == NULL && 274 OF_getprop(node, "compatible", compat, sizeof(compat)) != -1) 275 rv = psycho_find_desc(psycho_compats, compat); 276 return (rv); 277} 278 279static int 280psycho_probe(device_t dev) 281{ 282 phandle_t node; 283 char *dtype; 284 285 node = nexus_get_node(dev); 286 dtype = nexus_get_device_type(dev); 287 if (nexus_get_reg(dev) != NULL && dtype != NULL && 288 strcmp(dtype, OFW_PCI_TYPE) == 0 && 289 psycho_get_desc(node, nexus_get_model(dev)) != NULL) { 290 device_set_desc(dev, "U2P UPA-PCI bridge"); 291 return (0); 292 } 293 294 return (ENXIO); 295} 296 297/* 298 * SUNW,psycho initialisation .. 299 * - find the per-psycho registers 300 * - figure out the IGN. 301 * - find our partner psycho 302 * - configure ourselves 303 * - bus range, bus, 304 * - interrupt map, 305 * - setup the chipsets. 306 * - if we're the first of the pair, initialise the IOMMU, otherwise 307 * just copy it's tags and addresses. 308 */ 309static int 310psycho_attach(device_t dev) 311{ 312 struct psycho_softc *sc; 313 struct psycho_softc *osc = NULL; 314 struct psycho_softc *asc; 315 struct upa_regs *reg; 316 struct ofw_pci_bdesc obd; 317 struct psycho_desc *desc; 318 phandle_t node; 319 u_int64_t csr; 320 u_long mlen; 321 int psycho_br[2]; 322 int n, i, nreg, rid; 323#ifdef PSYCHO_DEBUG 324 bus_addr_t map, clr; 325 u_int64_t mr; 326#endif 327 328 node = nexus_get_node(dev); 329 sc = device_get_softc(dev); 330 desc = psycho_get_desc(node, nexus_get_model(dev)); 331 332 sc->sc_node = node; 333 sc->sc_dev = dev; 334 sc->sc_dmatag = nexus_get_dmatag(dev); 335 sc->sc_mode = desc->pd_mode; 336 337 /* 338 * The psycho gets three register banks: 339 * (0) per-PBM configuration and status registers 340 * (1) per-PBM PCI configuration space, containing only the 341 * PBM 256-byte PCI header 342 * (2) the shared psycho configuration registers (struct psychoreg) 343 */ 344 reg = nexus_get_reg(dev); 345 nreg = nexus_get_nreg(dev); 346 /* Register layouts are different. stuupid. */ 347 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 348 if (nreg <= 2) 349 panic("psycho_attach: %d not enough registers", nreg); 350 sc->sc_basepaddr = (vm_paddr_t)UPA_REG_PHYS(®[2]); 351 mlen = UPA_REG_SIZE(®[2]); 352 sc->sc_pcictl = UPA_REG_PHYS(®[0]) - sc->sc_basepaddr; 353 switch (sc->sc_pcictl) { 354 case PSR_PCICTL0: 355 sc->sc_half = 0; 356 break; 357 case PSR_PCICTL1: 358 sc->sc_half = 1; 359 break; 360 default: 361 panic("psycho_attach: bogus pci control register " 362 "location"); 363 } 364 } else { 365 if (nreg <= 0) 366 panic("psycho_attach: %d not enough registers", nreg); 367 sc->sc_basepaddr = (vm_paddr_t)UPA_REG_PHYS(®[0]); 368 mlen = UPA_REG_SIZE(reg); 369 sc->sc_pcictl = PSR_PCICTL0; 370 sc->sc_half = 0; 371 } 372 373 /* 374 * Match other psycho's that are already configured against 375 * the base physical address. This will be the same for a 376 * pair of devices that share register space. 377 */ 378 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 379 if (asc->sc_basepaddr == sc->sc_basepaddr) { 380 /* Found partner */ 381 osc = asc; 382 break; 383 } 384 } 385 386 if (osc == NULL) { 387 rid = 0; 388 sc->sc_mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 389 sc->sc_basepaddr, sc->sc_basepaddr + mlen - 1, mlen, 390 RF_ACTIVE); 391 if (sc->sc_mem_res == NULL || 392 rman_get_start(sc->sc_mem_res) != sc->sc_basepaddr) 393 panic("psycho_attach: can't allocate device memory"); 394 sc->sc_bustag = rman_get_bustag(sc->sc_mem_res); 395 sc->sc_bushandle = rman_get_bushandle(sc->sc_mem_res); 396 } else { 397 /* 398 * There's another psycho using the same register space. Copy the 399 * relevant stuff. 400 */ 401 sc->sc_mem_res = NULL; 402 sc->sc_bustag = osc->sc_bustag; 403 sc->sc_bushandle = osc->sc_bushandle; 404 } 405 csr = PSYCHO_READ8(sc, PSR_CS); 406 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 407 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 408 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 409 410 device_printf(dev, "%s, impl %d, version %d, ign %#x, bus %c\n", 411 desc->pd_name, (int)PSYCHO_GCSR_IMPL(csr), 412 (int)PSYCHO_GCSR_VERS(csr), sc->sc_ign, 'A' + sc->sc_half); 413 414 /* 415 * Setup the PCI control register 416 */ 417 csr = PCICTL_READ8(sc, PCR_CS); 418 csr |= PCICTL_MRLM | PCICTL_ARB_PARK | PCICTL_ERRINTEN | PCICTL_4ENABLE; 419 csr &= ~(PCICTL_SERR | PCICTL_CPU_PRIO | PCICTL_ARB_PRIO | 420 PCICTL_RTRYWAIT); 421 PCICTL_WRITE8(sc, PCR_CS, csr); 422 423 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 424 /* 425 * Use the PROM preset for now. 426 */ 427 csr = PCICTL_READ8(sc, PCR_TAS); 428 if (csr == 0) 429 panic("psycho_attach: sabre TAS not initialized."); 430 sc->sc_dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT; 431 } else 432 sc->sc_dvmabase = -1; 433 434 /* Grab the psycho ranges */ 435 psycho_get_ranges(sc->sc_node, &sc->sc_range, &sc->sc_nrange); 436 437 /* Initialize memory and i/o rmans */ 438 sc->sc_io_rman.rm_type = RMAN_ARRAY; 439 sc->sc_io_rman.rm_descr = "Psycho PCI I/O Ports"; 440 if (rman_init(&sc->sc_io_rman) != 0 || 441 rman_manage_region(&sc->sc_io_rman, 0, PSYCHO_IO_SIZE) != 0) 442 panic("psycho_probe: failed to set up i/o rman"); 443 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 444 sc->sc_mem_rman.rm_descr = "Psycho PCI Memory"; 445 if (rman_init(&sc->sc_mem_rman) != 0 || 446 rman_manage_region(&sc->sc_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 447 panic("psycho_probe: failed to set up memory rman"); 448 /* 449 * Find the addresses of the various bus spaces. 450 * There should not be multiple ones of one kind. 451 * The physical start addresses of the ranges are the configuration, 452 * memory and IO handles. 453 */ 454 for (n = 0; n < sc->sc_nrange; n++) { 455 i = UPA_RANGE_CS(&sc->sc_range[n]); 456 if (sc->sc_bh[i] != 0) 457 panic("psycho_attach: duplicate range for space %d", i); 458 sc->sc_bh[i] = UPA_RANGE_PHYS(&sc->sc_range[n]); 459 } 460 /* 461 * Check that all needed handles are present. The PCI_CS_MEM64 one is 462 * not currently used. 463 */ 464 for (n = 0; n < 3; n++) { 465 if (sc->sc_bh[n] == 0) 466 panic("psycho_attach: range %d missing", n); 467 } 468 469 /* Register the softc, this is needed for paired psychos. */ 470 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 471 472 /* 473 * If we're a sabre or the first of a pair of psycho's to arrive here, 474 * start up the IOMMU. 475 */ 476 if (osc == NULL) { 477 /* 478 * Establish handlers for interesting interrupts.... 479 * 480 * XXX We need to remember these and remove this to support 481 * hotplug on the UPA/FHC bus. 482 * 483 * XXX Not all controllers have these, but installing them 484 * is better than trying to sort through this mess. 485 */ 486 psycho_set_intr(sc, 0, dev, PSR_UE_INT_MAP, INTR_FAST, 487 psycho_ue); 488 psycho_set_intr(sc, 1, dev, PSR_CE_INT_MAP, 0, psycho_ce); 489 psycho_set_intr(sc, 2, dev, PSR_PCIAERR_INT_MAP, INTR_FAST, 490 psycho_bus_a); 491 psycho_set_intr(sc, 4, dev, PSR_POWER_INT_MAP, 492 PSYCHO_PWRFAIL_INT_FLAGS, psycho_powerfail); 493 /* Psycho-specific initialization. */ 494 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 495 /* 496 * Sabres do not have the following two interrupts. 497 */ 498 psycho_set_intr(sc, 3, dev, PSR_PCIBERR_INT_MAP, 499 INTR_FAST, psycho_bus_b); 500#ifdef PSYCHO_MAP_WAKEUP 501 /* 502 * psycho_wakeup() doesn't do anything useful right 503 * now. 504 */ 505 psycho_set_intr(sc, 5, dev, PSR_PWRMGT_INT_MAP, 0, 506 psycho_wakeup); 507#endif /* PSYCHO_MAP_WAKEUP */ 508 509 /* Initialize the counter-timer. */ 510 sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, 511 PSR_TC0); 512 } 513 514 /* 515 * Setup IOMMU and PCI configuration if we're the first 516 * of a pair of psycho's to arrive here. 517 * 518 * We should calculate a TSB size based on amount of RAM 519 * and number of bus controllers and number and type of 520 * child devices. 521 * 522 * For the moment, 32KB should be more than enough. 523 */ 524 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 525 M_NOWAIT); 526 if (sc->sc_is == NULL) 527 panic("psycho_attach: malloc iommu_state failed"); 528 sc->sc_is->is_sb[0] = 0; 529 sc->sc_is->is_sb[1] = 0; 530 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 531 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 532 psycho_iommu_init(sc, 3); 533 } else { 534 /* Just copy IOMMU state, config tag and address */ 535 sc->sc_is = osc->sc_is; 536 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 537 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 538 iommu_reset(sc->sc_is); 539 } 540 541 /* Allocate our tags. */ 542 sc->sc_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 543 sc->sc_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 544 sc->sc_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 545 if (bus_dma_tag_create(sc->sc_dmatag, 8, 1, 0, 0x3ffffffff, NULL, NULL, 546 0x3ffffffff, 0xff, 0xffffffff, 0, &sc->sc_dmat) != 0) 547 panic("psycho_attach: bus_dma_tag_create failed"); 548 /* Customize the tag. */ 549 sc->sc_dmat->dt_cookie = sc->sc_is; 550 sc->sc_dmat->dt_mt = &iommu_dma_methods; 551 /* XXX: register as root dma tag (kludge). */ 552 sparc64_root_dma_tag = sc->sc_dmat; 553 554#ifdef PSYCHO_DEBUG 555 /* 556 * Enable all interrupts and clear all interrupt states. 557 * This aids the debugging of interrupt routing problems. 558 */ 559 for (map = PSR_PCIA0_INT_MAP, clr = PSR_PCIA0_INT_CLR, n = 0; 560 map <= PSR_PCIB3_INT_MAP; map += 8, clr += 32, n++) { 561 mr = PSYCHO_READ8(sc, map); 562 device_printf(dev, "intr map (pci) %d: %#lx\n", n, (u_long)mr); 563 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 564 for (i = 0; i < 4; i++) 565 PCICTL_WRITE8(sc, clr + i * 8, 0); 566 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 567 } 568 for (map = PSR_SCSI_INT_MAP, clr = PSR_SCSI_INT_CLR, n = 0; 569 map <= PSR_SERIAL_INT_MAP; map += 8, clr += 8, n++) { 570 mr = PSYCHO_READ8(sc, map); 571 device_printf(dev, "intr map (obio) %d: %#lx, clr: %#lx\n", n, 572 (u_long)mr, (u_long)clr); 573 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 574 PSYCHO_WRITE8(sc, clr, 0); 575 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 576 } 577#endif /* PSYCHO_DEBUG */ 578 579 /* 580 * Get the bus range from the firmware; it is used solely for obtaining 581 * the inital bus number, and cannot be trusted on all machines. 582 */ 583 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br)); 584 if (n == -1) 585 panic("could not get psycho bus-range"); 586 if (n != sizeof(psycho_br)) 587 panic("broken psycho bus-range (%d)", n); 588 589 sc->sc_busno = ofw_pci_alloc_busno(sc->sc_node); 590 obd.obd_bus = psycho_br[0]; 591 obd.obd_secbus = obd.obd_subbus = sc->sc_busno; 592 obd.obd_slot = PCS_DEVICE; 593 obd.obd_func = PCS_FUNC; 594 obd.obd_init = psycho_binit; 595 obd.obd_super = NULL; 596 /* Initial setup. */ 597 psycho_binit(dev, &obd); 598 /* Update the bus number to what was just programmed. */ 599 obd.obd_bus = obd.obd_secbus; 600 /* 601 * Initialize the interrupt registers of all devices hanging from 602 * the host bridge directly or indirectly via PCI-PCI bridges. 603 * The MI code (and the PCI spec) assume that this is done during 604 * system initialization, however the firmware does not do this 605 * at least on some models, and we probably shouldn't trust that 606 * the firmware uses the same model as this driver if it does. 607 * Additionally, set up the bus numbers and ranges. 608 */ 609 ofw_pci_init(dev, sc->sc_node, sc->sc_ign, &obd); 610 611 device_add_child(dev, "pci", device_get_unit(dev)); 612 return (bus_generic_attach(dev)); 613} 614 615static void 616psycho_set_intr(struct psycho_softc *sc, int index, 617 device_t dev, bus_addr_t map, int iflags, driver_intr_t handler) 618{ 619 int rid, vec; 620 u_int64_t mr; 621 622 mr = PSYCHO_READ8(sc, map); 623 vec = INTVEC(mr); 624 sc->sc_irq_res[index] = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 625 vec, vec, 1, RF_ACTIVE); 626 if (sc->sc_irq_res[index] == NULL) 627 panic("psycho_set_intr: failed to get interrupt"); 628 bus_setup_intr(dev, sc->sc_irq_res[index], INTR_TYPE_MISC | iflags, 629 handler, sc, &sc->sc_ihand[index]); 630 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 631} 632 633static int 634psycho_find_intrmap(struct psycho_softc *sc, int ino, bus_addr_t *intrmapptr, 635 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 636{ 637 bus_addr_t intrmap, intrclr; 638 u_int64_t im; 639 u_long diag; 640 int found; 641 642 found = 0; 643 /* Hunt thru obio first */ 644 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 645 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 646 intrmap <= PSR_SERIAL_INT_MAP; intrmap += 8, intrclr += 8, 647 diag >>= 2) { 648 im = PSYCHO_READ8(sc, intrmap); 649 if (INTINO(im) == ino) { 650 diag &= 2; 651 found = 1; 652 break; 653 } 654 } 655 656 if (!found) { 657 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 658 /* Now do PCI interrupts */ 659 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 660 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 661 diag >>= 8) { 662 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 663 (intrmap == PSR_PCIA2_INT_MAP || 664 intrmap == PSR_PCIA3_INT_MAP)) 665 continue; 666 im = PSYCHO_READ8(sc, intrmap); 667 if (((im ^ ino) & 0x3c) == 0) { 668 intrclr += 8 * (ino & 3); 669 diag = (diag >> ((ino & 3) * 2)) & 2; 670 found = 1; 671 break; 672 } 673 } 674 } 675 if (intrmapptr != NULL) 676 *intrmapptr = intrmap; 677 if (intrclrptr != NULL) 678 *intrclrptr = intrclr; 679 if (intrdiagptr != NULL) 680 *intrdiagptr = diag; 681 return (found); 682} 683 684/* grovel the OBP for various psycho properties */ 685static void 686psycho_get_ranges(phandle_t node, struct upa_ranges **rp, int *np) 687{ 688 689 *np = OF_getprop_alloc(node, "ranges", sizeof(**rp), (void **)rp); 690 if (*np == -1) 691 panic("could not get psycho ranges"); 692} 693 694/* 695 * Interrupt handlers. 696 */ 697static void 698psycho_ue(void *arg) 699{ 700 struct psycho_softc *sc = (struct psycho_softc *)arg; 701 u_int64_t afar, afsr; 702 703 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 704 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 705 /* 706 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 707 * the AFAR to be set to the physical address of the TTE entry that 708 * was invalid/write protected. Call into the iommu code to have 709 * them decoded to virtual IO addresses. 710 */ 711 if ((afsr & UEAFSR_P_DTE) != 0) 712 iommu_decode_fault(sc->sc_is, afar); 713 /* It's uncorrectable. Dump the regs and panic. */ 714 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx", 715 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 716} 717 718static void 719psycho_ce(void *arg) 720{ 721 struct psycho_softc *sc = (struct psycho_softc *)arg; 722 u_int64_t afar, afsr; 723 724 PSYCHO_WRITE8(sc, PSR_CE_INT_CLR, 0); 725 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 726 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 727 /* It's correctable. Dump the regs and continue. */ 728 printf("%s: correctable DMA error AFAR %#lx AFSR %#lx\n", 729 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 730} 731 732static void 733psycho_bus_a(void *arg) 734{ 735 struct psycho_softc *sc = (struct psycho_softc *)arg; 736 u_int64_t afar, afsr; 737 738 afar = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFA); 739 afsr = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFS); 740 /* It's uncorrectable. Dump the regs and panic. */ 741 panic("%s: PCI bus A error AFAR %#lx AFSR %#lx", 742 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 743} 744 745static void 746psycho_bus_b(void *arg) 747{ 748 struct psycho_softc *sc = (struct psycho_softc *)arg; 749 u_int64_t afar, afsr; 750 751 afar = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFA); 752 afsr = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFS); 753 /* It's uncorrectable. Dump the regs and panic. */ 754 panic("%s: PCI bus B error AFAR %#lx AFSR %#lx", 755 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 756} 757 758static void 759psycho_powerfail(void *arg) 760{ 761 762 /* We lost power. Try to shut down NOW. */ 763#ifdef DEBUGGER_ON_POWERFAIL 764 struct psycho_softc *sc = (struct psycho_softc *)arg; 765 766 Debugger("powerfail"); 767 PSYCHO_WRITE8(sc, PSR_POWER_INT_CLR, 0); 768#else 769 printf("Power Failure Detected: Shutting down NOW.\n"); 770 shutdown_nice(0); 771#endif 772} 773 774#ifdef PSYCHO_MAP_WAKEUP 775static void 776psycho_wakeup(void *arg) 777{ 778 struct psycho_softc *sc = (struct psycho_softc *)arg; 779 780 PSYCHO_WRITE8(sc, PSR_PWRMGT_INT_CLR, 0); 781 /* Gee, we don't really have a framework to deal with this properly. */ 782 printf("%s: power management wakeup\n", device_get_name(sc->sc_dev)); 783} 784#endif /* PSYCHO_MAP_WAKEUP */ 785 786/* initialise the IOMMU... */ 787void 788psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 789{ 790 char *name; 791 struct iommu_state *is = sc->sc_is; 792 793 /* punch in our copies */ 794 is->is_bustag = sc->sc_bustag; 795 is->is_bushandle = sc->sc_bushandle; 796 is->is_iommu = PSR_IOMMU; 797 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 798 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 799 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 800 is->is_dva = PSR_IOMMU_SVADIAG; 801 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 802 803 /* give us a nice name.. */ 804 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 805 if (name == 0) 806 panic("couldn't malloc iommu name"); 807 snprintf(name, 32, "%s dvma", device_get_name(sc->sc_dev)); 808 809 iommu_init(name, is, tsbsize, sc->sc_dvmabase, 0); 810} 811 812static void 813psycho_binit(device_t busdev, struct ofw_pci_bdesc *obd) 814{ 815 816#ifdef PSYCHO_DEBUG 817 printf("psycho at %u/%u/%u: setting bus #s to %u/%u/%u\n", 818 obd->obd_bus, obd->obd_slot, obd->obd_func, obd->obd_bus, 819 obd->obd_secbus, obd->obd_subbus); 820#endif /* PSYCHO_DEBUG */ 821 /* 822 * NOTE: this must be kept in this order, since the last write will 823 * change the config space address of the psycho. 824 */ 825 PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func, 826 PCSR_SUBBUS, obd->obd_subbus, 1); 827 PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func, 828 PCSR_SECBUS, obd->obd_secbus, 1); 829} 830 831static int 832psycho_maxslots(device_t dev) 833{ 834 835 /* 836 * XXX: is this correct? At any rate, a number that is too high 837 * shouldn't do any harm, if only because of the way things are 838 * handled in psycho_read_config. 839 */ 840 return (31); 841} 842 843/* 844 * Keep a table of quirky PCI devices that need fixups before the MI PCI code 845 * creates the resource lists. This needs to be moved around once other bus 846 * drivers are added. Moving it to the MI code should maybe be reconsidered 847 * if one of these devices appear in non-sparc64 boxen. It's likely that not 848 * all BIOSes/firmwares can deal with them. 849 */ 850struct psycho_dquirk { 851 u_int32_t dq_devid; 852 int dq_quirk; 853}; 854 855/* Quirk types. May be or'ed together. */ 856#define DQT_BAD_INTPIN 1 /* Intpin reg 0, but intpin used */ 857 858static struct psycho_dquirk dquirks[] = { 859 { 0x1001108e, DQT_BAD_INTPIN }, /* Sun HME (PCIO func. 1) */ 860 { 0x1101108e, DQT_BAD_INTPIN }, /* Sun GEM (PCIO2 func. 1) */ 861 { 0x1102108e, DQT_BAD_INTPIN }, /* Sun FireWire ctl. (PCIO2 func. 2) */ 862 { 0x1103108e, DQT_BAD_INTPIN }, /* Sun USB ctl. (PCIO2 func. 3) */ 863}; 864 865#define NDQUIRKS (sizeof(dquirks) / sizeof(dquirks[0])) 866 867static u_int32_t 868psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 869 int width) 870{ 871 struct psycho_softc *sc; 872 bus_space_handle_t bh; 873 u_long offset = 0; 874 u_int32_t r, devid; 875 int i; 876 877 /* 878 * The psycho bridge does not tolerate accesses to unconfigured PCI 879 * devices' or function's config space, so look up the device in the 880 * firmware device tree first, and if it is not present, return a value 881 * that will make the detection code think that there is no device here. 882 * This is ugly... 883 */ 884 if (reg == 0 && ofw_pci_find_node(bus, slot, func) == 0) 885 return (0xffffffff); 886 sc = (struct psycho_softc *)device_get_softc(dev); 887 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 888 bh = sc->sc_bh[PCI_CS_CONFIG]; 889 switch (width) { 890 case 1: 891 r = bus_space_read_1(sc->sc_cfgt, bh, offset); 892 break; 893 case 2: 894 r = bus_space_read_2(sc->sc_cfgt, bh, offset); 895 break; 896 case 4: 897 r = bus_space_read_4(sc->sc_cfgt, bh, offset); 898 break; 899 default: 900 panic("psycho_read_config: bad width"); 901 } 902 if (reg == PCIR_INTPIN && r == 0) { 903 /* Check for DQT_BAD_INTPIN quirk. */ 904 devid = psycho_read_config(dev, bus, slot, func, 905 PCIR_DEVVENDOR, 4); 906 for (i = 0; i < NDQUIRKS; i++) { 907 if (dquirks[i].dq_devid == devid) { 908 /* 909 * Need to set the intpin to a value != 0 so 910 * that the MI code will think that this device 911 * has an interrupt. 912 * Just use 1 (intpin a) for now. This is, of 913 * course, bogus, but since interrupts are 914 * routed in advance, this does not really 915 * matter. 916 */ 917 if ((dquirks[i].dq_quirk & DQT_BAD_INTPIN) != 0) 918 r = 1; 919 break; 920 } 921 } 922 } 923 return (r); 924} 925 926static void 927psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, 928 u_int reg, u_int32_t val, int width) 929{ 930 struct psycho_softc *sc; 931 bus_space_handle_t bh; 932 u_long offset = 0; 933 934 sc = (struct psycho_softc *)device_get_softc(dev); 935 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 936 bh = sc->sc_bh[PCI_CS_CONFIG]; 937 switch (width) { 938 case 1: 939 bus_space_write_1(sc->sc_cfgt, bh, offset, val); 940 break; 941 case 2: 942 bus_space_write_2(sc->sc_cfgt, bh, offset, val); 943 break; 944 case 4: 945 bus_space_write_4(sc->sc_cfgt, bh, offset, val); 946 break; 947 default: 948 panic("psycho_write_config: bad width"); 949 } 950} 951 952static int 953psycho_route_interrupt(device_t bus, device_t dev, int pin) 954{ 955 956 /* 957 * XXX: ugly loathsome hack: 958 * We can't use ofw_pci_route_intr() here; the device passed may be 959 * the one of a bridge, so the original device can't be recovered. 960 * 961 * We need to use the firmware to route interrupts, however it has 962 * no interface which could be used to interpret intpins; instead, 963 * all assignments are done by device. 964 * 965 * The MI pci code will try to reroute interrupts of 0, although they 966 * are correct; all other interrupts are preinitialized, so if we 967 * get here, the intline is either 0 (so return 0), or we hit a 968 * device which was not preinitialized (e.g. hotplugged stuff), in 969 * which case we are lost. 970 */ 971 return (0); 972} 973 974static int 975psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 976{ 977 struct psycho_softc *sc; 978 979 sc = (struct psycho_softc *)device_get_softc(dev); 980 switch (which) { 981 case PCIB_IVAR_BUS: 982 *result = sc->sc_busno; 983 return (0); 984 } 985 return (ENOENT); 986} 987 988/* Write to the correct clr register, and call the actual handler. */ 989static void 990psycho_intr_stub(void *arg) 991{ 992 struct psycho_clr *pc; 993 994 pc = (struct psycho_clr *)arg; 995 pc->pci_handler(pc->pci_arg); 996 PSYCHO_WRITE8(pc->pci_sc, pc->pci_clr, 0); 997} 998 999static int 1000psycho_setup_intr(device_t dev, device_t child, 1001 struct resource *ires, int flags, driver_intr_t *intr, void *arg, 1002 void **cookiep) 1003{ 1004 struct psycho_softc *sc; 1005 struct psycho_clr *pc; 1006 bus_addr_t intrmapptr, intrclrptr; 1007 long vec = rman_get_start(ires); 1008 u_int64_t mr; 1009 int ino, error; 1010 1011 sc = (struct psycho_softc *)device_get_softc(dev); 1012 pc = (struct psycho_clr *)malloc(sizeof(*pc), M_DEVBUF, M_NOWAIT); 1013 if (pc == NULL) 1014 return (NULL); 1015 1016 /* 1017 * Hunt through all the interrupt mapping regs to look for our 1018 * interrupt vector. 1019 * 1020 * XXX We only compare INOs rather than IGNs since the firmware may 1021 * not provide the IGN and the IGN is constant for all device on that 1022 * PCI controller. This could cause problems for the FFB/external 1023 * interrupt which has a full vector that can be set arbitrarily. 1024 */ 1025 ino = INTINO(vec); 1026 1027 if (!psycho_find_intrmap(sc, ino, &intrmapptr, &intrclrptr, NULL)) { 1028 printf("Cannot find interrupt vector %lx\n", vec); 1029 free(pc, M_DEVBUF); 1030 return (NULL); 1031 } 1032 1033#ifdef PSYCHO_DEBUG 1034 device_printf(dev, "psycho_setup_intr: INO %d, map %#lx, clr %#lx\n", 1035 ino, (u_long)intrmapptr, (u_long)intrclrptr); 1036#endif 1037 pc->pci_sc = sc; 1038 pc->pci_arg = arg; 1039 pc->pci_handler = intr; 1040 pc->pci_clr = intrclrptr; 1041 /* Disable the interrupt while we fiddle with it */ 1042 mr = PSYCHO_READ8(sc, intrmapptr); 1043 PSYCHO_WRITE8(sc, intrmapptr, mr & ~INTMAP_V); 1044 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 1045 psycho_intr_stub, pc, cookiep); 1046 if (error != 0) { 1047 free(pc, M_DEVBUF); 1048 return (error); 1049 } 1050 pc->pci_cookie = *cookiep; 1051 *cookiep = pc; 1052 1053 /* 1054 * Clear the interrupt, it might have been triggered before it was 1055 * set up. 1056 */ 1057 PSYCHO_WRITE8(sc, intrclrptr, 0); 1058 /* 1059 * Enable the interrupt and program the target module now we have the 1060 * handler installed. 1061 */ 1062 PSYCHO_WRITE8(sc, intrmapptr, INTMAP_ENABLE(mr, PCPU_GET(mid))); 1063 return (error); 1064} 1065 1066static int 1067psycho_teardown_intr(device_t dev, device_t child, 1068 struct resource *vec, void *cookie) 1069{ 1070 struct psycho_clr *pc; 1071 int error; 1072 1073 pc = (struct psycho_clr *)cookie; 1074 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 1075 pc->pci_cookie); 1076 /* 1077 * Don't disable the interrupt for now, so that stray interupts get 1078 * detected... 1079 */ 1080 if (error != 0) 1081 free(pc, M_DEVBUF); 1082 return (error); 1083} 1084 1085static struct resource * 1086psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1087 u_long start, u_long end, u_long count, u_int flags) 1088{ 1089 struct psycho_softc *sc; 1090 struct resource *rv; 1091 struct rman *rm; 1092 bus_space_tag_t bt; 1093 bus_space_handle_t bh; 1094 int needactivate = flags & RF_ACTIVE; 1095 1096 flags &= ~RF_ACTIVE; 1097 1098 sc = (struct psycho_softc *)device_get_softc(bus); 1099 if (type == SYS_RES_IRQ) { 1100 /* 1101 * XXX: Don't accept blank ranges for now, only single 1102 * interrupts. The other case should not happen with the MI pci 1103 * code... 1104 * XXX: This may return a resource that is out of the range 1105 * that was specified. Is this correct...? 1106 */ 1107 if (start != end) 1108 panic("psycho_alloc_resource: XXX: interrupt range"); 1109 start = end |= sc->sc_ign; 1110 return (bus_alloc_resource(bus, type, rid, start, end, 1111 count, flags)); 1112 } 1113 switch (type) { 1114 case SYS_RES_MEMORY: 1115 rm = &sc->sc_mem_rman; 1116 bt = sc->sc_memt; 1117 bh = sc->sc_bh[PCI_CS_MEM32]; 1118 break; 1119 case SYS_RES_IOPORT: 1120 rm = &sc->sc_io_rman; 1121 bt = sc->sc_iot; 1122 bh = sc->sc_bh[PCI_CS_IO]; 1123 break; 1124 default: 1125 return (NULL); 1126 } 1127 1128 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1129 if (rv == NULL) 1130 return (NULL); 1131 1132 bh += rman_get_start(rv); 1133 rman_set_bustag(rv, bt); 1134 rman_set_bushandle(rv, bh); 1135 1136 if (needactivate) { 1137 if (bus_activate_resource(child, type, *rid, rv)) { 1138 rman_release_resource(rv); 1139 return (NULL); 1140 } 1141 } 1142 1143 return (rv); 1144} 1145 1146static int 1147psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1148 struct resource *r) 1149{ 1150 void *p; 1151 int error; 1152 1153 if (type == SYS_RES_IRQ) 1154 return (bus_activate_resource(bus, type, rid, r)); 1155 if (type == SYS_RES_MEMORY) { 1156 /* 1157 * Need to memory-map the device space, as some drivers depend 1158 * on the virtual address being set and useable. 1159 */ 1160 error = sparc64_bus_mem_map(rman_get_bustag(r), 1161 rman_get_bushandle(r), rman_get_size(r), 0, NULL, &p); 1162 if (error != 0) 1163 return (error); 1164 rman_set_virtual(r, p); 1165 } 1166 return (rman_activate_resource(r)); 1167} 1168 1169static int 1170psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1171 struct resource *r) 1172{ 1173 1174 if (type == SYS_RES_IRQ) 1175 return (bus_deactivate_resource(bus, type, rid, r)); 1176 if (type == SYS_RES_MEMORY) { 1177 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1178 rman_set_virtual(r, NULL); 1179 } 1180 return (rman_deactivate_resource(r)); 1181} 1182 1183static int 1184psycho_release_resource(device_t bus, device_t child, int type, int rid, 1185 struct resource *r) 1186{ 1187 int error; 1188 1189 if (type == SYS_RES_IRQ) 1190 return (bus_release_resource(bus, type, rid, r)); 1191 if (rman_get_flags(r) & RF_ACTIVE) { 1192 error = bus_deactivate_resource(child, type, rid, r); 1193 if (error) 1194 return error; 1195 } 1196 return (rman_release_resource(r)); 1197} 1198 1199static int 1200psycho_intr_pending(device_t dev, int intr) 1201{ 1202 struct psycho_softc *sc; 1203 u_long diag; 1204 1205 sc = (struct psycho_softc *)device_get_softc(dev); 1206 if (!psycho_find_intrmap(sc, intr, NULL, NULL, &diag)) { 1207 printf("psycho_intr_pending: mapping not found for %d\n", intr); 1208 return (0); 1209 } 1210 return (diag != 0); 1211} 1212 1213static u_int32_t 1214psycho_guess_ino(device_t dev, phandle_t node, u_int slot, u_int pin) 1215{ 1216 struct psycho_softc *sc = (struct psycho_softc *)device_get_softc(dev); 1217 bus_addr_t intrmap; 1218 1219 /* 1220 * If this is not for one of our direct children (i.e. we are mapping 1221 * at our node), tell the interrupt mapper to go on - we need the 1222 * slot number of the device or it's topmost parent bridge to guess 1223 * the INO. 1224 */ 1225 if (node != sc->sc_node) 1226 return (255); 1227 /* 1228 * Actually guess the INO. We always assume that this is a non-OBIO 1229 * device, and use from the slot number to determine it. 1230 * We only need to do this on e450s, it seems; here, the slot numbers 1231 * for bus A are one-based, while those for bus B seemingly have an 1232 * offset of 2 (hence the factor of 3 below). 1233 */ 1234 intrmap = PSR_PCIA0_INT_MAP + 8 * (slot - 1 + 3 * sc->sc_half); 1235 return (INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1); 1236} 1237 1238static bus_space_handle_t 1239psycho_get_bus_handle(device_t dev, enum sbbt_id id, 1240 bus_space_handle_t childhdl, bus_space_tag_t *tag) 1241{ 1242 struct psycho_softc *sc; 1243 1244 sc = (struct psycho_softc *)device_get_softc(dev); 1245 switch(id) { 1246 case SBBT_IO: 1247 *tag = sc->sc_iot; 1248 return (sc->sc_bh[PCI_CS_IO] + childhdl); 1249 case SBBT_MEM: 1250 *tag = sc->sc_memt; 1251 return (sc->sc_bh[PCI_CS_MEM32] + childhdl); 1252 default: 1253 panic("psycho_get_bus_handle: illegal space\n"); 1254 } 1255} 1256 1257/* 1258 * below here is bus space and bus dma support 1259 */ 1260static bus_space_tag_t 1261psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1262{ 1263 bus_space_tag_t bt; 1264 1265 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1266 M_NOWAIT | M_ZERO); 1267 if (bt == NULL) 1268 panic("psycho_alloc_bus_tag: out of memory"); 1269 1270 bzero(bt, sizeof *bt); 1271 bt->bst_cookie = sc; 1272 bt->bst_parent = sc->sc_bustag; 1273 bt->bst_type = type; 1274 return (bt); 1275} 1276