psycho.c revision 116259
1/* 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * All rights reserved. 4 * Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 30 * 31 * $FreeBSD: head/sys/sparc64/pci/psycho.c 116259 2003-06-12 15:00:34Z tmm $ 32 */ 33 34/* 35 * Support for `psycho' and `psycho+' UPA to PCI bridge and 36 * UltraSPARC IIi and IIe `sabre' PCI controllers. 37 */ 38 39#include "opt_psycho.h" 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/kernel.h> 45#include <sys/malloc.h> 46#include <sys/pcpu.h> 47 48#include <ofw/openfirm.h> 49#include <ofw/ofw_pci.h> 50 51#include <machine/bus.h> 52#include <machine/iommureg.h> 53#include <machine/bus_common.h> 54#include <machine/frame.h> 55#include <machine/intr_machdep.h> 56#include <machine/nexusvar.h> 57#include <machine/ofw_upa.h> 58#include <machine/resource.h> 59 60#include <sys/rman.h> 61 62#include <machine/iommuvar.h> 63 64#include <pci/pcivar.h> 65#include <pci/pcireg.h> 66 67#include <sparc64/pci/ofw_pci.h> 68#include <sparc64/pci/psychoreg.h> 69#include <sparc64/pci/psychovar.h> 70 71#include "pcib_if.h" 72#include "sparcbus_if.h" 73 74static void psycho_get_ranges(phandle_t, struct upa_ranges **, int *); 75static void psycho_set_intr(struct psycho_softc *, int, device_t, bus_addr_t, 76 int, driver_intr_t); 77static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *, 78 bus_addr_t *, u_long *); 79static void psycho_intr_stub(void *); 80static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 81 82 83/* Interrupt handlers */ 84static void psycho_ue(void *); 85static void psycho_ce(void *); 86static void psycho_bus_a(void *); 87static void psycho_bus_b(void *); 88static void psycho_powerfail(void *); 89#ifdef PSYCHO_MAP_WAKEUP 90static void psycho_wakeup(void *); 91#endif 92 93/* IOMMU support */ 94static void psycho_iommu_init(struct psycho_softc *, int); 95static ofw_pci_binit_t psycho_binit; 96 97/* 98 * autoconfiguration 99 */ 100static int psycho_probe(device_t); 101static int psycho_attach(device_t); 102static int psycho_read_ivar(device_t, device_t, int, u_long *); 103static int psycho_setup_intr(device_t, device_t, struct resource *, int, 104 driver_intr_t *, void *, void **); 105static int psycho_teardown_intr(device_t, device_t, struct resource *, void *); 106static struct resource *psycho_alloc_resource(device_t, device_t, int, int *, 107 u_long, u_long, u_long, u_int); 108static int psycho_activate_resource(device_t, device_t, int, int, 109 struct resource *); 110static int psycho_deactivate_resource(device_t, device_t, int, int, 111 struct resource *); 112static int psycho_release_resource(device_t, device_t, int, int, 113 struct resource *); 114static int psycho_maxslots(device_t); 115static u_int32_t psycho_read_config(device_t, u_int, u_int, u_int, u_int, int); 116static void psycho_write_config(device_t, u_int, u_int, u_int, u_int, u_int32_t, 117 int); 118static int psycho_route_interrupt(device_t, device_t, int); 119static int psycho_intr_pending(device_t, int); 120static u_int32_t psycho_guess_ino(device_t, phandle_t, u_int, u_int); 121static bus_space_handle_t psycho_get_bus_handle(device_t dev, enum sbbt_id id, 122 bus_space_handle_t childhdl, bus_space_tag_t *tag); 123 124static device_method_t psycho_methods[] = { 125 /* Device interface */ 126 DEVMETHOD(device_probe, psycho_probe), 127 DEVMETHOD(device_attach, psycho_attach), 128 129 /* Bus interface */ 130 DEVMETHOD(bus_print_child, bus_generic_print_child), 131 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 132 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 133 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 134 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 135 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 136 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 137 DEVMETHOD(bus_release_resource, psycho_release_resource), 138 139 /* pcib interface */ 140 DEVMETHOD(pcib_maxslots, psycho_maxslots), 141 DEVMETHOD(pcib_read_config, psycho_read_config), 142 DEVMETHOD(pcib_write_config, psycho_write_config), 143 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 144 145 /* sparcbus interface */ 146 DEVMETHOD(sparcbus_intr_pending, psycho_intr_pending), 147 DEVMETHOD(sparcbus_guess_ino, psycho_guess_ino), 148 DEVMETHOD(sparcbus_get_bus_handle, psycho_get_bus_handle), 149 150 { 0, 0 } 151}; 152 153static driver_t psycho_driver = { 154 "pcib", 155 psycho_methods, 156 sizeof(struct psycho_softc), 157}; 158 159static devclass_t psycho_devclass; 160 161DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 162 163SLIST_HEAD(, psycho_softc) psycho_softcs = 164 SLIST_HEAD_INITIALIZER(psycho_softcs); 165 166struct psycho_clr { 167 struct psycho_softc *pci_sc; 168 bus_addr_t pci_clr; /* clear register */ 169 driver_intr_t *pci_handler; /* handler to call */ 170 void *pci_arg; /* argument for the handler */ 171 void *pci_cookie; /* interrupt cookie of parent bus */ 172}; 173 174struct psycho_strayclr { 175 struct psycho_softc *psc_sc; 176 bus_addr_t psc_clr; /* clear register */ 177}; 178 179#define PSYCHO_READ8(sc, off) \ 180 bus_space_read_8((sc)->sc_bustag, (sc)->sc_bushandle, (off)) 181#define PSYCHO_WRITE8(sc, off, v) \ 182 bus_space_write_8((sc)->sc_bustag, (sc)->sc_bushandle, (off), (v)) 183#define PCICTL_READ8(sc, off) \ 184 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 185#define PCICTL_WRITE8(sc, off, v) \ 186 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 187 188/* 189 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 190 * single PCI bus and does not have a streaming buffer. It often has an APB 191 * (advanced PCI bridge) connected to it, which was designed specifically for 192 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 193 * appears as two "simba"'s underneath the sabre. 194 * 195 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 196 * and manages two PCI buses. "psycho" has two 64-bit 33MHz buses, while 197 * "psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 198 * will usually find a "psycho+" since I don't think the original "psycho" 199 * ever shipped, and if it did it would be in the U30. 200 * 201 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 202 * both part of the same IC, they only have a single register space. As such, 203 * they need to be configured together, even though the autoconfiguration will 204 * attach them separately. 205 * 206 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 207 * as pci1 and pci2, although they have been implemented with other PCI bus 208 * numbers on some machines. 209 * 210 * On UltraII machines, there can be any number of "psycho+" ICs, each 211 * providing two PCI buses. 212 * 213 * 214 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 215 * the values of the following interrupts in this order: 216 * 217 * PCI Bus Error (30) 218 * DMA UE (2e) 219 * DMA CE (2f) 220 * Power Fail (25) 221 * 222 * We really should attach handlers for each. 223 */ 224#ifdef DEBUGGER_ON_POWERFAIL 225#define PSYCHO_PWRFAIL_INT_FLAGS INTR_FAST 226#else 227#define PSYCHO_PWRFAIL_INT_FLAGS 0 228#endif 229 230#define OFW_PCI_TYPE "pci" 231 232struct psycho_desc { 233 char *pd_string; 234 int pd_mode; 235 char *pd_name; 236}; 237 238static struct psycho_desc psycho_compats[] = { 239 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 240 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre (US-IIi) compatible" }, 241 { "pci108e,a001", PSYCHO_MODE_SABRE, "Sabre (US-IIe) compatible" }, 242 { NULL, 0, NULL } 243}; 244 245static struct psycho_desc psycho_models[] = { 246 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 247 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 248 { NULL, 0, NULL } 249}; 250 251static struct psycho_desc * 252psycho_find_desc(struct psycho_desc *table, char *string) 253{ 254 struct psycho_desc *desc; 255 256 for (desc = table; desc->pd_string != NULL; desc++) { 257 if (strcmp(desc->pd_string, string) == 0) 258 return (desc); 259 } 260 return (NULL); 261} 262 263static struct psycho_desc * 264psycho_get_desc(phandle_t node, char *model) 265{ 266 struct psycho_desc *rv; 267 char compat[32]; 268 269 rv = NULL; 270 if (model != NULL) 271 rv = psycho_find_desc(psycho_models, model); 272 if (rv == NULL && 273 OF_getprop(node, "compatible", compat, sizeof(compat)) != -1) 274 rv = psycho_find_desc(psycho_compats, compat); 275 return (rv); 276} 277 278static int 279psycho_probe(device_t dev) 280{ 281 phandle_t node; 282 char *dtype; 283 284 node = nexus_get_node(dev); 285 dtype = nexus_get_device_type(dev); 286 if (nexus_get_reg(dev) != NULL && dtype != NULL && 287 strcmp(dtype, OFW_PCI_TYPE) == 0 && 288 psycho_get_desc(node, nexus_get_model(dev)) != NULL) { 289 device_set_desc(dev, "U2P UPA-PCI bridge"); 290 return (0); 291 } 292 293 return (ENXIO); 294} 295 296/* 297 * SUNW,psycho initialisation .. 298 * - find the per-psycho registers 299 * - figure out the IGN. 300 * - find our partner psycho 301 * - configure ourselves 302 * - bus range, bus, 303 * - interrupt map, 304 * - setup the chipsets. 305 * - if we're the first of the pair, initialise the IOMMU, otherwise 306 * just copy it's tags and addresses. 307 */ 308static int 309psycho_attach(device_t dev) 310{ 311 struct psycho_softc *sc; 312 struct psycho_softc *osc = NULL; 313 struct psycho_softc *asc; 314 struct upa_regs *reg; 315 struct ofw_pci_bdesc obd; 316 struct psycho_desc *desc; 317 phandle_t node; 318 u_int64_t csr; 319 u_long mlen; 320 int psycho_br[2]; 321 int n, i, nreg, rid; 322#ifdef PSYCHO_DEBUG 323 bus_addr_t map, clr; 324 u_int64_t mr; 325#endif 326 327 node = nexus_get_node(dev); 328 sc = device_get_softc(dev); 329 desc = psycho_get_desc(node, nexus_get_model(dev)); 330 331 sc->sc_node = node; 332 sc->sc_dev = dev; 333 sc->sc_dmatag = nexus_get_dmatag(dev); 334 sc->sc_mode = desc->pd_mode; 335 336 /* 337 * The psycho gets three register banks: 338 * (0) per-PBM configuration and status registers 339 * (1) per-PBM PCI configuration space, containing only the 340 * PBM 256-byte PCI header 341 * (2) the shared psycho configuration registers (struct psychoreg) 342 */ 343 reg = nexus_get_reg(dev); 344 nreg = nexus_get_nreg(dev); 345 /* Register layouts are different. stuupid. */ 346 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 347 if (nreg <= 2) 348 panic("psycho_attach: %d not enough registers", nreg); 349 sc->sc_basepaddr = (vm_paddr_t)UPA_REG_PHYS(®[2]); 350 mlen = UPA_REG_SIZE(®[2]); 351 sc->sc_pcictl = UPA_REG_PHYS(®[0]) - sc->sc_basepaddr; 352 switch (sc->sc_pcictl) { 353 case PSR_PCICTL0: 354 sc->sc_half = 0; 355 break; 356 case PSR_PCICTL1: 357 sc->sc_half = 1; 358 break; 359 default: 360 panic("psycho_attach: bogus pci control register " 361 "location"); 362 } 363 } else { 364 if (nreg <= 0) 365 panic("psycho_attach: %d not enough registers", nreg); 366 sc->sc_basepaddr = (vm_paddr_t)UPA_REG_PHYS(®[0]); 367 mlen = UPA_REG_SIZE(reg); 368 sc->sc_pcictl = PSR_PCICTL0; 369 sc->sc_half = 0; 370 } 371 372 /* 373 * Match other psycho's that are already configured against 374 * the base physical address. This will be the same for a 375 * pair of devices that share register space. 376 */ 377 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 378 if (asc->sc_basepaddr == sc->sc_basepaddr) { 379 /* Found partner */ 380 osc = asc; 381 break; 382 } 383 } 384 385 if (osc == NULL) { 386 rid = 0; 387 sc->sc_mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 388 sc->sc_basepaddr, sc->sc_basepaddr + mlen - 1, mlen, 389 RF_ACTIVE); 390 if (sc->sc_mem_res == NULL || 391 rman_get_start(sc->sc_mem_res) != sc->sc_basepaddr) 392 panic("psycho_attach: can't allocate device memory"); 393 sc->sc_bustag = rman_get_bustag(sc->sc_mem_res); 394 sc->sc_bushandle = rman_get_bushandle(sc->sc_mem_res); 395 } else { 396 /* 397 * There's another psycho using the same register space. Copy the 398 * relevant stuff. 399 */ 400 sc->sc_mem_res = NULL; 401 sc->sc_bustag = osc->sc_bustag; 402 sc->sc_bushandle = osc->sc_bushandle; 403 } 404 csr = PSYCHO_READ8(sc, PSR_CS); 405 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 406 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 407 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 408 409 device_printf(dev, "%s, impl %d, version %d, ign %#x, bus %c\n", 410 desc->pd_name, (int)PSYCHO_GCSR_IMPL(csr), 411 (int)PSYCHO_GCSR_VERS(csr), sc->sc_ign, 'A' + sc->sc_half); 412 413 /* 414 * Setup the PCI control register 415 */ 416 csr = PCICTL_READ8(sc, PCR_CS); 417 csr |= PCICTL_MRLM | PCICTL_ARB_PARK | PCICTL_ERRINTEN | PCICTL_4ENABLE; 418 csr &= ~(PCICTL_SERR | PCICTL_CPU_PRIO | PCICTL_ARB_PRIO | 419 PCICTL_RTRYWAIT); 420 PCICTL_WRITE8(sc, PCR_CS, csr); 421 422 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 423 /* 424 * Use the PROM preset for now. 425 */ 426 csr = PCICTL_READ8(sc, PCR_TAS); 427 if (csr == 0) 428 panic("psycho_attach: sabre TAS not initialized."); 429 sc->sc_dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT; 430 } else 431 sc->sc_dvmabase = -1; 432 433 /* Grab the psycho ranges */ 434 psycho_get_ranges(sc->sc_node, &sc->sc_range, &sc->sc_nrange); 435 436 /* Initialize memory and i/o rmans */ 437 sc->sc_io_rman.rm_type = RMAN_ARRAY; 438 sc->sc_io_rman.rm_descr = "Psycho PCI I/O Ports"; 439 if (rman_init(&sc->sc_io_rman) != 0 || 440 rman_manage_region(&sc->sc_io_rman, 0, PSYCHO_IO_SIZE) != 0) 441 panic("psycho_probe: failed to set up i/o rman"); 442 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 443 sc->sc_mem_rman.rm_descr = "Psycho PCI Memory"; 444 if (rman_init(&sc->sc_mem_rman) != 0 || 445 rman_manage_region(&sc->sc_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 446 panic("psycho_probe: failed to set up memory rman"); 447 /* 448 * Find the addresses of the various bus spaces. 449 * There should not be multiple ones of one kind. 450 * The physical start addresses of the ranges are the configuration, 451 * memory and IO handles. 452 */ 453 for (n = 0; n < sc->sc_nrange; n++) { 454 i = UPA_RANGE_CS(&sc->sc_range[n]); 455 if (sc->sc_bh[i] != 0) 456 panic("psycho_attach: duplicate range for space %d", i); 457 sc->sc_bh[i] = UPA_RANGE_PHYS(&sc->sc_range[n]); 458 } 459 /* 460 * Check that all needed handles are present. The PCI_CS_MEM64 one is 461 * not currently used. 462 */ 463 for (n = 0; n < 3; n++) { 464 if (sc->sc_bh[n] == 0) 465 panic("psycho_attach: range %d missing", n); 466 } 467 468 /* Register the softc, this is needed for paired psychos. */ 469 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 470 471 /* 472 * If we're a sabre or the first of a pair of psycho's to arrive here, 473 * start up the IOMMU. 474 */ 475 if (osc == NULL) { 476 /* 477 * Establish handlers for interesting interrupts.... 478 * 479 * XXX We need to remember these and remove this to support 480 * hotplug on the UPA/FHC bus. 481 * 482 * XXX Not all controllers have these, but installing them 483 * is better than trying to sort through this mess. 484 */ 485 psycho_set_intr(sc, 0, dev, PSR_UE_INT_MAP, INTR_FAST, 486 psycho_ue); 487 psycho_set_intr(sc, 1, dev, PSR_CE_INT_MAP, 0, psycho_ce); 488 psycho_set_intr(sc, 2, dev, PSR_PCIAERR_INT_MAP, INTR_FAST, 489 psycho_bus_a); 490 psycho_set_intr(sc, 4, dev, PSR_POWER_INT_MAP, 491 PSYCHO_PWRFAIL_INT_FLAGS, psycho_powerfail); 492 /* Psycho-specific initialization. */ 493 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 494 /* 495 * Sabres do not have the following two interrupts. 496 */ 497 psycho_set_intr(sc, 3, dev, PSR_PCIBERR_INT_MAP, 498 INTR_FAST, psycho_bus_b); 499#ifdef PSYCHO_MAP_WAKEUP 500 /* 501 * psycho_wakeup() doesn't do anything useful right 502 * now. 503 */ 504 psycho_set_intr(sc, 5, dev, PSR_PWRMGT_INT_MAP, 0, 505 psycho_wakeup); 506#endif /* PSYCHO_MAP_WAKEUP */ 507 508 /* Initialize the counter-timer. */ 509 sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, 510 PSR_TC0); 511 } 512 513 /* 514 * Setup IOMMU and PCI configuration if we're the first 515 * of a pair of psycho's to arrive here. 516 * 517 * We should calculate a TSB size based on amount of RAM 518 * and number of bus controllers and number and type of 519 * child devices. 520 * 521 * For the moment, 32KB should be more than enough. 522 */ 523 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 524 M_NOWAIT); 525 if (sc->sc_is == NULL) 526 panic("psycho_attach: malloc iommu_state failed"); 527 sc->sc_is->is_sb[0] = 0; 528 sc->sc_is->is_sb[1] = 0; 529 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 530 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 531 psycho_iommu_init(sc, 3); 532 } else { 533 /* Just copy IOMMU state, config tag and address */ 534 sc->sc_is = osc->sc_is; 535 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 536 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 537 iommu_reset(sc->sc_is); 538 } 539 540 /* Allocate our tags. */ 541 sc->sc_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 542 sc->sc_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 543 sc->sc_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 544 if (bus_dma_tag_create(sc->sc_dmatag, 8, 1, 0, 0x3ffffffff, NULL, NULL, 545 0x3ffffffff, 0xff, 0xffffffff, 0, &sc->sc_dmat) != 0) 546 panic("psycho_attach: bus_dma_tag_create failed"); 547 /* Customize the tag. */ 548 sc->sc_dmat->dt_cookie = sc->sc_is; 549 sc->sc_dmat->dt_dmamap_create = iommu_dvmamap_create; 550 sc->sc_dmat->dt_dmamap_destroy = iommu_dvmamap_destroy; 551 sc->sc_dmat->dt_dmamap_load = iommu_dvmamap_load; 552 sc->sc_dmat->dt_dmamap_load_mbuf = iommu_dvmamap_load_mbuf; 553 sc->sc_dmat->dt_dmamap_load_uio = iommu_dvmamap_load_uio; 554 sc->sc_dmat->dt_dmamap_unload = iommu_dvmamap_unload; 555 sc->sc_dmat->dt_dmamap_sync = iommu_dvmamap_sync; 556 sc->sc_dmat->dt_dmamem_alloc = iommu_dvmamem_alloc; 557 sc->sc_dmat->dt_dmamem_free = iommu_dvmamem_free; 558 /* XXX: register as root dma tag (kludge). */ 559 sparc64_root_dma_tag = sc->sc_dmat; 560 561#ifdef PSYCHO_DEBUG 562 /* 563 * Enable all interrupts and clear all interrupt states. 564 * This aids the debugging of interrupt routing problems. 565 */ 566 for (map = PSR_PCIA0_INT_MAP, clr = PSR_PCIA0_INT_CLR, n = 0; 567 map <= PSR_PCIB3_INT_MAP; map += 8, clr += 32, n++) { 568 mr = PSYCHO_READ8(sc, map); 569 device_printf(dev, "intr map (pci) %d: %#lx\n", n, (u_long)mr); 570 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 571 for (i = 0; i < 4; i++) 572 PCICTL_WRITE8(sc, clr + i * 8, 0); 573 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 574 } 575 for (map = PSR_SCSI_INT_MAP, clr = PSR_SCSI_INT_CLR, n = 0; 576 map <= PSR_SERIAL_INT_MAP; map += 8, clr += 8, n++) { 577 mr = PSYCHO_READ8(sc, map); 578 device_printf(dev, "intr map (obio) %d: %#lx, clr: %#lx\n", n, 579 (u_long)mr, (u_long)clr); 580 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 581 PSYCHO_WRITE8(sc, clr, 0); 582 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 583 } 584#endif /* PSYCHO_DEBUG */ 585 586 /* 587 * Get the bus range from the firmware; it is used solely for obtaining 588 * the inital bus number, and cannot be trusted on all machines. 589 */ 590 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br)); 591 if (n == -1) 592 panic("could not get psycho bus-range"); 593 if (n != sizeof(psycho_br)) 594 panic("broken psycho bus-range (%d)", n); 595 596 sc->sc_busno = ofw_pci_alloc_busno(sc->sc_node); 597 obd.obd_bus = psycho_br[0]; 598 obd.obd_secbus = obd.obd_subbus = sc->sc_busno; 599 obd.obd_slot = PCS_DEVICE; 600 obd.obd_func = PCS_FUNC; 601 obd.obd_init = psycho_binit; 602 obd.obd_super = NULL; 603 /* Initial setup. */ 604 psycho_binit(dev, &obd); 605 /* Update the bus number to what was just programmed. */ 606 obd.obd_bus = obd.obd_secbus; 607 /* 608 * Initialize the interrupt registers of all devices hanging from 609 * the host bridge directly or indirectly via PCI-PCI bridges. 610 * The MI code (and the PCI spec) assume that this is done during 611 * system initialization, however the firmware does not do this 612 * at least on some models, and we probably shouldn't trust that 613 * the firmware uses the same model as this driver if it does. 614 * Additionally, set up the bus numbers and ranges. 615 */ 616 ofw_pci_init(dev, sc->sc_node, sc->sc_ign, &obd); 617 618 device_add_child(dev, "pci", device_get_unit(dev)); 619 return (bus_generic_attach(dev)); 620} 621 622static void 623psycho_set_intr(struct psycho_softc *sc, int index, 624 device_t dev, bus_addr_t map, int iflags, driver_intr_t handler) 625{ 626 int rid, vec; 627 u_int64_t mr; 628 629 mr = PSYCHO_READ8(sc, map); 630 vec = INTVEC(mr); 631 sc->sc_irq_res[index] = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 632 vec, vec, 1, RF_ACTIVE); 633 if (sc->sc_irq_res[index] == NULL) 634 panic("psycho_set_intr: failed to get interrupt"); 635 bus_setup_intr(dev, sc->sc_irq_res[index], INTR_TYPE_MISC | iflags, 636 handler, sc, &sc->sc_ihand[index]); 637 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 638} 639 640static int 641psycho_find_intrmap(struct psycho_softc *sc, int ino, bus_addr_t *intrmapptr, 642 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 643{ 644 bus_addr_t intrmap, intrclr; 645 u_int64_t im; 646 u_long diag; 647 int found; 648 649 found = 0; 650 /* Hunt thru obio first */ 651 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 652 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 653 intrmap <= PSR_SERIAL_INT_MAP; intrmap += 8, intrclr += 8, 654 diag >>= 2) { 655 im = PSYCHO_READ8(sc, intrmap); 656 if (INTINO(im) == ino) { 657 diag &= 2; 658 found = 1; 659 break; 660 } 661 } 662 663 if (!found) { 664 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 665 /* Now do PCI interrupts */ 666 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 667 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 668 diag >>= 8) { 669 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 670 (intrmap == PSR_PCIA2_INT_MAP || 671 intrmap == PSR_PCIA3_INT_MAP)) 672 continue; 673 im = PSYCHO_READ8(sc, intrmap); 674 if (((im ^ ino) & 0x3c) == 0) { 675 intrclr += 8 * (ino & 3); 676 diag = (diag >> ((ino & 3) * 2)) & 2; 677 found = 1; 678 break; 679 } 680 } 681 } 682 if (intrmapptr != NULL) 683 *intrmapptr = intrmap; 684 if (intrclrptr != NULL) 685 *intrclrptr = intrclr; 686 if (intrdiagptr != NULL) 687 *intrdiagptr = diag; 688 return (found); 689} 690 691/* grovel the OBP for various psycho properties */ 692static void 693psycho_get_ranges(phandle_t node, struct upa_ranges **rp, int *np) 694{ 695 696 *np = OF_getprop_alloc(node, "ranges", sizeof(**rp), (void **)rp); 697 if (*np == -1) 698 panic("could not get psycho ranges"); 699} 700 701/* 702 * Interrupt handlers. 703 */ 704static void 705psycho_ue(void *arg) 706{ 707 struct psycho_softc *sc = (struct psycho_softc *)arg; 708 u_int64_t afar, afsr; 709 710 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 711 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 712 /* 713 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 714 * the AFAR to be set to the physical address of the TTE entry that 715 * was invalid/write protected. Call into the iommu code to have 716 * them decoded to virtual IO addresses. 717 */ 718 if ((afsr & UEAFSR_P_DTE) != 0) 719 iommu_decode_fault(sc->sc_is, afar); 720 /* It's uncorrectable. Dump the regs and panic. */ 721 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx", 722 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 723} 724 725static void 726psycho_ce(void *arg) 727{ 728 struct psycho_softc *sc = (struct psycho_softc *)arg; 729 u_int64_t afar, afsr; 730 731 PSYCHO_WRITE8(sc, PSR_CE_INT_CLR, 0); 732 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 733 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 734 /* It's correctable. Dump the regs and continue. */ 735 printf("%s: correctable DMA error AFAR %#lx AFSR %#lx\n", 736 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 737} 738 739static void 740psycho_bus_a(void *arg) 741{ 742 struct psycho_softc *sc = (struct psycho_softc *)arg; 743 u_int64_t afar, afsr; 744 745 afar = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFA); 746 afsr = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFS); 747 /* It's uncorrectable. Dump the regs and panic. */ 748 panic("%s: PCI bus A error AFAR %#lx AFSR %#lx", 749 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 750} 751 752static void 753psycho_bus_b(void *arg) 754{ 755 struct psycho_softc *sc = (struct psycho_softc *)arg; 756 u_int64_t afar, afsr; 757 758 afar = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFA); 759 afsr = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFS); 760 /* It's uncorrectable. Dump the regs and panic. */ 761 panic("%s: PCI bus B error AFAR %#lx AFSR %#lx", 762 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 763} 764 765static void 766psycho_powerfail(void *arg) 767{ 768 769 /* We lost power. Try to shut down NOW. */ 770#ifdef DEBUGGER_ON_POWERFAIL 771 struct psycho_softc *sc = (struct psycho_softc *)arg; 772 773 Debugger("powerfail"); 774 PSYCHO_WRITE8(sc, PSR_POWER_INT_CLR, 0); 775#else 776 printf("Power Failure Detected: Shutting down NOW.\n"); 777 shutdown_nice(0); 778#endif 779} 780 781#ifdef PSYCHO_MAP_WAKEUP 782static void 783psycho_wakeup(void *arg) 784{ 785 struct psycho_softc *sc = (struct psycho_softc *)arg; 786 787 PSYCHO_WRITE8(sc, PSR_PWRMGT_INT_CLR, 0); 788 /* Gee, we don't really have a framework to deal with this properly. */ 789 printf("%s: power management wakeup\n", device_get_name(sc->sc_dev)); 790} 791#endif /* PSYCHO_MAP_WAKEUP */ 792 793/* initialise the IOMMU... */ 794void 795psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 796{ 797 char *name; 798 struct iommu_state *is = sc->sc_is; 799 800 /* punch in our copies */ 801 is->is_bustag = sc->sc_bustag; 802 is->is_bushandle = sc->sc_bushandle; 803 is->is_iommu = PSR_IOMMU; 804 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 805 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 806 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 807 is->is_dva = PSR_IOMMU_SVADIAG; 808 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 809 810 /* give us a nice name.. */ 811 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 812 if (name == 0) 813 panic("couldn't malloc iommu name"); 814 snprintf(name, 32, "%s dvma", device_get_name(sc->sc_dev)); 815 816 iommu_init(name, is, tsbsize, sc->sc_dvmabase, 0); 817} 818 819static void 820psycho_binit(device_t busdev, struct ofw_pci_bdesc *obd) 821{ 822 823#ifdef PSYCHO_DEBUG 824 printf("psycho at %u/%u/%u: setting bus #s to %u/%u/%u\n", 825 obd->obd_bus, obd->obd_slot, obd->obd_func, obd->obd_bus, 826 obd->obd_secbus, obd->obd_subbus); 827#endif /* PSYCHO_DEBUG */ 828 /* 829 * NOTE: this must be kept in this order, since the last write will 830 * change the config space address of the psycho. 831 */ 832 PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func, 833 PCSR_SUBBUS, obd->obd_subbus, 1); 834 PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func, 835 PCSR_SECBUS, obd->obd_secbus, 1); 836} 837 838static int 839psycho_maxslots(device_t dev) 840{ 841 842 /* 843 * XXX: is this correct? At any rate, a number that is too high 844 * shouldn't do any harm, if only because of the way things are 845 * handled in psycho_read_config. 846 */ 847 return (31); 848} 849 850/* 851 * Keep a table of quirky PCI devices that need fixups before the MI PCI code 852 * creates the resource lists. This needs to be moved around once other bus 853 * drivers are added. Moving it to the MI code should maybe be reconsidered 854 * if one of these devices appear in non-sparc64 boxen. It's likely that not 855 * all BIOSes/firmwares can deal with them. 856 */ 857struct psycho_dquirk { 858 u_int32_t dq_devid; 859 int dq_quirk; 860}; 861 862/* Quirk types. May be or'ed together. */ 863#define DQT_BAD_INTPIN 1 /* Intpin reg 0, but intpin used */ 864 865static struct psycho_dquirk dquirks[] = { 866 { 0x1001108e, DQT_BAD_INTPIN }, /* Sun HME (PCIO func. 1) */ 867 { 0x1101108e, DQT_BAD_INTPIN }, /* Sun GEM (PCIO2 func. 1) */ 868 { 0x1102108e, DQT_BAD_INTPIN }, /* Sun FireWire ctl. (PCIO2 func. 2) */ 869 { 0x1103108e, DQT_BAD_INTPIN }, /* Sun USB ctl. (PCIO2 func. 3) */ 870}; 871 872#define NDQUIRKS (sizeof(dquirks) / sizeof(dquirks[0])) 873 874static u_int32_t 875psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 876 int width) 877{ 878 struct psycho_softc *sc; 879 bus_space_handle_t bh; 880 u_long offset = 0; 881 u_int32_t r, devid; 882 int i; 883 884 /* 885 * The psycho bridge does not tolerate accesses to unconfigured PCI 886 * devices' or function's config space, so look up the device in the 887 * firmware device tree first, and if it is not present, return a value 888 * that will make the detection code think that there is no device here. 889 * This is ugly... 890 */ 891 if (reg == 0 && ofw_pci_find_node(bus, slot, func) == 0) 892 return (0xffffffff); 893 sc = (struct psycho_softc *)device_get_softc(dev); 894 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 895 bh = sc->sc_bh[PCI_CS_CONFIG]; 896 switch (width) { 897 case 1: 898 r = bus_space_read_1(sc->sc_cfgt, bh, offset); 899 break; 900 case 2: 901 r = bus_space_read_2(sc->sc_cfgt, bh, offset); 902 break; 903 case 4: 904 r = bus_space_read_4(sc->sc_cfgt, bh, offset); 905 break; 906 default: 907 panic("psycho_read_config: bad width"); 908 } 909 if (reg == PCIR_INTPIN && r == 0) { 910 /* Check for DQT_BAD_INTPIN quirk. */ 911 devid = psycho_read_config(dev, bus, slot, func, 912 PCIR_DEVVENDOR, 4); 913 for (i = 0; i < NDQUIRKS; i++) { 914 if (dquirks[i].dq_devid == devid) { 915 /* 916 * Need to set the intpin to a value != 0 so 917 * that the MI code will think that this device 918 * has an interrupt. 919 * Just use 1 (intpin a) for now. This is, of 920 * course, bogus, but since interrupts are 921 * routed in advance, this does not really 922 * matter. 923 */ 924 if ((dquirks[i].dq_quirk & DQT_BAD_INTPIN) != 0) 925 r = 1; 926 break; 927 } 928 } 929 } 930 return (r); 931} 932 933static void 934psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, 935 u_int reg, u_int32_t val, int width) 936{ 937 struct psycho_softc *sc; 938 bus_space_handle_t bh; 939 u_long offset = 0; 940 941 sc = (struct psycho_softc *)device_get_softc(dev); 942 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 943 bh = sc->sc_bh[PCI_CS_CONFIG]; 944 switch (width) { 945 case 1: 946 bus_space_write_1(sc->sc_cfgt, bh, offset, val); 947 break; 948 case 2: 949 bus_space_write_2(sc->sc_cfgt, bh, offset, val); 950 break; 951 case 4: 952 bus_space_write_4(sc->sc_cfgt, bh, offset, val); 953 break; 954 default: 955 panic("psycho_write_config: bad width"); 956 } 957} 958 959static int 960psycho_route_interrupt(device_t bus, device_t dev, int pin) 961{ 962 963 /* 964 * XXX: ugly loathsome hack: 965 * We can't use ofw_pci_route_intr() here; the device passed may be 966 * the one of a bridge, so the original device can't be recovered. 967 * 968 * We need to use the firmware to route interrupts, however it has 969 * no interface which could be used to interpret intpins; instead, 970 * all assignments are done by device. 971 * 972 * The MI pci code will try to reroute interrupts of 0, although they 973 * are correct; all other interrupts are preinitialized, so if we 974 * get here, the intline is either 0 (so return 0), or we hit a 975 * device which was not preinitialized (e.g. hotplugged stuff), in 976 * which case we are lost. 977 */ 978 return (0); 979} 980 981static int 982psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 983{ 984 struct psycho_softc *sc; 985 986 sc = (struct psycho_softc *)device_get_softc(dev); 987 switch (which) { 988 case PCIB_IVAR_BUS: 989 *result = sc->sc_busno; 990 return (0); 991 } 992 return (ENOENT); 993} 994 995/* Write to the correct clr register, and call the actual handler. */ 996static void 997psycho_intr_stub(void *arg) 998{ 999 struct psycho_clr *pc; 1000 1001 pc = (struct psycho_clr *)arg; 1002 pc->pci_handler(pc->pci_arg); 1003 PSYCHO_WRITE8(pc->pci_sc, pc->pci_clr, 0); 1004} 1005 1006static int 1007psycho_setup_intr(device_t dev, device_t child, 1008 struct resource *ires, int flags, driver_intr_t *intr, void *arg, 1009 void **cookiep) 1010{ 1011 struct psycho_softc *sc; 1012 struct psycho_clr *pc; 1013 bus_addr_t intrmapptr, intrclrptr; 1014 long vec = rman_get_start(ires); 1015 u_int64_t mr; 1016 int ino, error; 1017 1018 sc = (struct psycho_softc *)device_get_softc(dev); 1019 pc = (struct psycho_clr *)malloc(sizeof(*pc), M_DEVBUF, M_NOWAIT); 1020 if (pc == NULL) 1021 return (NULL); 1022 1023 /* 1024 * Hunt through all the interrupt mapping regs to look for our 1025 * interrupt vector. 1026 * 1027 * XXX We only compare INOs rather than IGNs since the firmware may 1028 * not provide the IGN and the IGN is constant for all device on that 1029 * PCI controller. This could cause problems for the FFB/external 1030 * interrupt which has a full vector that can be set arbitrarily. 1031 */ 1032 ino = INTINO(vec); 1033 1034 if (!psycho_find_intrmap(sc, ino, &intrmapptr, &intrclrptr, NULL)) { 1035 printf("Cannot find interrupt vector %lx\n", vec); 1036 free(pc, M_DEVBUF); 1037 return (NULL); 1038 } 1039 1040#ifdef PSYCHO_DEBUG 1041 device_printf(dev, "psycho_setup_intr: INO %d, map %#lx, clr %#lx\n", 1042 ino, (u_long)intrmapptr, (u_long)intrclrptr); 1043#endif 1044 pc->pci_sc = sc; 1045 pc->pci_arg = arg; 1046 pc->pci_handler = intr; 1047 pc->pci_clr = intrclrptr; 1048 /* Disable the interrupt while we fiddle with it */ 1049 mr = PSYCHO_READ8(sc, intrmapptr); 1050 PSYCHO_WRITE8(sc, intrmapptr, mr & ~INTMAP_V); 1051 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 1052 psycho_intr_stub, pc, cookiep); 1053 if (error != 0) { 1054 free(pc, M_DEVBUF); 1055 return (error); 1056 } 1057 pc->pci_cookie = *cookiep; 1058 *cookiep = pc; 1059 1060 /* 1061 * Clear the interrupt, it might have been triggered before it was 1062 * set up. 1063 */ 1064 PSYCHO_WRITE8(sc, intrclrptr, 0); 1065 /* 1066 * Enable the interrupt and program the target module now we have the 1067 * handler installed. 1068 */ 1069 PSYCHO_WRITE8(sc, intrmapptr, INTMAP_ENABLE(mr, PCPU_GET(mid))); 1070 return (error); 1071} 1072 1073static int 1074psycho_teardown_intr(device_t dev, device_t child, 1075 struct resource *vec, void *cookie) 1076{ 1077 struct psycho_clr *pc; 1078 int error; 1079 1080 pc = (struct psycho_clr *)cookie; 1081 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 1082 pc->pci_cookie); 1083 /* 1084 * Don't disable the interrupt for now, so that stray interupts get 1085 * detected... 1086 */ 1087 if (error != 0) 1088 free(pc, M_DEVBUF); 1089 return (error); 1090} 1091 1092static struct resource * 1093psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1094 u_long start, u_long end, u_long count, u_int flags) 1095{ 1096 struct psycho_softc *sc; 1097 struct resource *rv; 1098 struct rman *rm; 1099 bus_space_tag_t bt; 1100 bus_space_handle_t bh; 1101 int needactivate = flags & RF_ACTIVE; 1102 1103 flags &= ~RF_ACTIVE; 1104 1105 sc = (struct psycho_softc *)device_get_softc(bus); 1106 if (type == SYS_RES_IRQ) { 1107 /* 1108 * XXX: Don't accept blank ranges for now, only single 1109 * interrupts. The other case should not happen with the MI pci 1110 * code... 1111 * XXX: This may return a resource that is out of the range 1112 * that was specified. Is this correct...? 1113 */ 1114 if (start != end) 1115 panic("psycho_alloc_resource: XXX: interrupt range"); 1116 start = end |= sc->sc_ign; 1117 return (bus_alloc_resource(bus, type, rid, start, end, 1118 count, flags)); 1119 } 1120 switch (type) { 1121 case SYS_RES_MEMORY: 1122 rm = &sc->sc_mem_rman; 1123 bt = sc->sc_memt; 1124 bh = sc->sc_bh[PCI_CS_MEM32]; 1125 break; 1126 case SYS_RES_IOPORT: 1127 rm = &sc->sc_io_rman; 1128 bt = sc->sc_iot; 1129 bh = sc->sc_bh[PCI_CS_IO]; 1130 break; 1131 default: 1132 return (NULL); 1133 } 1134 1135 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1136 if (rv == NULL) 1137 return (NULL); 1138 1139 bh += rman_get_start(rv); 1140 rman_set_bustag(rv, bt); 1141 rman_set_bushandle(rv, bh); 1142 1143 if (needactivate) { 1144 if (bus_activate_resource(child, type, *rid, rv)) { 1145 rman_release_resource(rv); 1146 return (NULL); 1147 } 1148 } 1149 1150 return (rv); 1151} 1152 1153static int 1154psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1155 struct resource *r) 1156{ 1157 void *p; 1158 int error; 1159 1160 if (type == SYS_RES_IRQ) 1161 return (bus_activate_resource(bus, type, rid, r)); 1162 if (type == SYS_RES_MEMORY) { 1163 /* 1164 * Need to memory-map the device space, as some drivers depend 1165 * on the virtual address being set and useable. 1166 */ 1167 error = sparc64_bus_mem_map(rman_get_bustag(r), 1168 rman_get_bushandle(r), rman_get_size(r), 0, NULL, &p); 1169 if (error != 0) 1170 return (error); 1171 rman_set_virtual(r, p); 1172 } 1173 return (rman_activate_resource(r)); 1174} 1175 1176static int 1177psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1178 struct resource *r) 1179{ 1180 1181 if (type == SYS_RES_IRQ) 1182 return (bus_deactivate_resource(bus, type, rid, r)); 1183 if (type == SYS_RES_MEMORY) { 1184 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1185 rman_set_virtual(r, NULL); 1186 } 1187 return (rman_deactivate_resource(r)); 1188} 1189 1190static int 1191psycho_release_resource(device_t bus, device_t child, int type, int rid, 1192 struct resource *r) 1193{ 1194 int error; 1195 1196 if (type == SYS_RES_IRQ) 1197 return (bus_release_resource(bus, type, rid, r)); 1198 if (rman_get_flags(r) & RF_ACTIVE) { 1199 error = bus_deactivate_resource(child, type, rid, r); 1200 if (error) 1201 return error; 1202 } 1203 return (rman_release_resource(r)); 1204} 1205 1206static int 1207psycho_intr_pending(device_t dev, int intr) 1208{ 1209 struct psycho_softc *sc; 1210 u_long diag; 1211 1212 sc = (struct psycho_softc *)device_get_softc(dev); 1213 if (!psycho_find_intrmap(sc, intr, NULL, NULL, &diag)) { 1214 printf("psycho_intr_pending: mapping not found for %d\n", intr); 1215 return (0); 1216 } 1217 return (diag != 0); 1218} 1219 1220static u_int32_t 1221psycho_guess_ino(device_t dev, phandle_t node, u_int slot, u_int pin) 1222{ 1223 struct psycho_softc *sc = (struct psycho_softc *)device_get_softc(dev); 1224 bus_addr_t intrmap; 1225 1226 /* 1227 * If this is not for one of our direct children (i.e. we are mapping 1228 * at our node), tell the interrupt mapper to go on - we need the 1229 * slot number of the device or it's topmost parent bridge to guess 1230 * the INO. 1231 */ 1232 if (node != sc->sc_node) 1233 return (255); 1234 /* 1235 * Actually guess the INO. We always assume that this is a non-OBIO 1236 * device, and use from the slot number to determine it. 1237 * We only need to do this on e450s, it seems; here, the slot numbers 1238 * for bus A are one-based, while those for bus B seemingly have an 1239 * offset of 2 (hence the factor of 3 below). 1240 */ 1241 intrmap = PSR_PCIA0_INT_MAP + 8 * (slot - 1 + 3 * sc->sc_half); 1242 return (INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1); 1243} 1244 1245static bus_space_handle_t 1246psycho_get_bus_handle(device_t dev, enum sbbt_id id, 1247 bus_space_handle_t childhdl, bus_space_tag_t *tag) 1248{ 1249 struct psycho_softc *sc; 1250 1251 sc = (struct psycho_softc *)device_get_softc(dev); 1252 switch(id) { 1253 case SBBT_IO: 1254 *tag = sc->sc_iot; 1255 return (sc->sc_bh[PCI_CS_IO] + childhdl); 1256 case SBBT_MEM: 1257 *tag = sc->sc_memt; 1258 return (sc->sc_bh[PCI_CS_MEM32] + childhdl); 1259 default: 1260 panic("psycho_get_bus_handle: illegal space\n"); 1261 } 1262} 1263 1264/* 1265 * below here is bus space and bus dma support 1266 */ 1267static bus_space_tag_t 1268psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1269{ 1270 bus_space_tag_t bt; 1271 1272 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1273 M_NOWAIT | M_ZERO); 1274 if (bt == NULL) 1275 panic("psycho_alloc_bus_tag: out of memory"); 1276 1277 bzero(bt, sizeof *bt); 1278 bt->bst_cookie = sc; 1279 bt->bst_parent = sc->sc_bustag; 1280 bt->bst_type = type; 1281 return (bt); 1282} 1283