psycho.c revision 107658
116Salm/* 216Salm * Copyright (c) 1999, 2000 Matthew R. Green 316Salm * All rights reserved. 416Salm * Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 30 * 31 * $FreeBSD: head/sys/sparc64/pci/psycho.c 107658 2002-12-06 13:16:52Z tmm $ 32 */ 33 34/* 35 * Support for `psycho' and `psycho+' UPA to PCI bridge and 36 * UltraSPARC IIi and IIe `sabre' PCI controllers. 37 */ 38 39#include "opt_psycho.h" 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/kernel.h> 45#include <sys/malloc.h> 46#include <sys/pcpu.h> 47 48#include <ofw/openfirm.h> 49#include <ofw/ofw_pci.h> 50 51#include <machine/bus.h> 52#include <machine/iommureg.h> 53#include <machine/bus_common.h> 54#include <machine/frame.h> 55#include <machine/intr_machdep.h> 56#include <machine/nexusvar.h> 57#include <machine/ofw_upa.h> 58#include <machine/resource.h> 59 60#include <sys/rman.h> 61 62#include <machine/iommuvar.h> 63 64#include <pci/pcivar.h> 65#include <pci/pcireg.h> 66 67#include <sparc64/pci/ofw_pci.h> 68#include <sparc64/pci/psychoreg.h> 69#include <sparc64/pci/psychovar.h> 70 71#include "pcib_if.h" 72#include "sparcbus_if.h" 73 74static void psycho_get_ranges(phandle_t, struct upa_ranges **, int *); 75static void psycho_set_intr(struct psycho_softc *, int, device_t, bus_addr_t, 76 int, driver_intr_t); 77static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *, 78 bus_addr_t *, u_long *); 79static void psycho_intr_stub(void *); 80#ifdef PSYCHO_STRAY 81static void psycho_intr_stray(void *); 82#endif 83static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 84 85 86/* Interrupt handlers */ 87static void psycho_ue(void *); 88static void psycho_ce(void *); 89static void psycho_bus_a(void *); 90static void psycho_bus_b(void *); 91static void psycho_powerfail(void *); 92#ifdef PSYCHO_MAP_WAKEUP 93static void psycho_wakeup(void *); 94#endif 95 96/* IOMMU support */ 97static void psycho_iommu_init(struct psycho_softc *, int); 98static ofw_pci_binit_t psycho_binit; 99 100/* 101 * bus space and bus dma support for UltraSPARC `psycho'. note that most 102 * of the bus dma support is provided by the iommu dvma controller. 103 */ 104static int psycho_dmamap_create(bus_dma_tag_t, bus_dma_tag_t, int, 105 bus_dmamap_t *); 106static int psycho_dmamap_destroy(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 107static int psycho_dmamap_load(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 108 void *, bus_size_t, bus_dmamap_callback_t *, void *, int); 109static void psycho_dmamap_unload(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 110static void psycho_dmamap_sync(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 111 bus_dmasync_op_t); 112static int psycho_dmamem_alloc(bus_dma_tag_t, bus_dma_tag_t, void **, int, 113 bus_dmamap_t *); 114static void psycho_dmamem_free(bus_dma_tag_t, bus_dma_tag_t, void *, 115 bus_dmamap_t); 116 117/* 118 * autoconfiguration 119 */ 120static int psycho_probe(device_t); 121static int psycho_attach(device_t); 122static int psycho_read_ivar(device_t, device_t, int, u_long *); 123static int psycho_setup_intr(device_t, device_t, struct resource *, int, 124 driver_intr_t *, void *, void **); 125static int psycho_teardown_intr(device_t, device_t, struct resource *, void *); 126static struct resource *psycho_alloc_resource(device_t, device_t, int, int *, 127 u_long, u_long, u_long, u_int); 128static int psycho_activate_resource(device_t, device_t, int, int, 129 struct resource *); 130static int psycho_deactivate_resource(device_t, device_t, int, int, 131 struct resource *); 132static int psycho_release_resource(device_t, device_t, int, int, 133 struct resource *); 134static int psycho_maxslots(device_t); 135static u_int32_t psycho_read_config(device_t, u_int, u_int, u_int, u_int, int); 136static void psycho_write_config(device_t, u_int, u_int, u_int, u_int, u_int32_t, 137 int); 138static int psycho_route_interrupt(device_t, device_t, int); 139static int psycho_intr_pending(device_t, int); 140static bus_space_handle_t psycho_get_bus_handle(device_t dev, enum sbbt_id id, 141 bus_space_handle_t childhdl, bus_space_tag_t *tag); 142 143static device_method_t psycho_methods[] = { 144 /* Device interface */ 145 DEVMETHOD(device_probe, psycho_probe), 146 DEVMETHOD(device_attach, psycho_attach), 147 148 /* Bus interface */ 149 DEVMETHOD(bus_print_child, bus_generic_print_child), 150 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 151 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 152 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 153 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 154 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 155 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 156 DEVMETHOD(bus_release_resource, psycho_release_resource), 157 158 /* pcib interface */ 159 DEVMETHOD(pcib_maxslots, psycho_maxslots), 160 DEVMETHOD(pcib_read_config, psycho_read_config), 161 DEVMETHOD(pcib_write_config, psycho_write_config), 162 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 163 164 /* sparcbus interface */ 165 DEVMETHOD(sparcbus_intr_pending, psycho_intr_pending), 166 DEVMETHOD(sparcbus_get_bus_handle, psycho_get_bus_handle), 167 168 { 0, 0 } 169}; 170 171static driver_t psycho_driver = { 172 "pcib", 173 psycho_methods, 174 sizeof(struct psycho_softc), 175}; 176 177static devclass_t psycho_devclass; 178 179DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 180 181SLIST_HEAD(, psycho_softc) psycho_softcs = 182 SLIST_HEAD_INITIALIZER(psycho_softcs); 183 184struct psycho_clr { 185 struct psycho_softc *pci_sc; 186 bus_addr_t pci_clr; /* clear register */ 187 driver_intr_t *pci_handler; /* handler to call */ 188 void *pci_arg; /* argument for the handler */ 189 void *pci_cookie; /* interrupt cookie of parent bus */ 190}; 191 192struct psycho_strayclr { 193 struct psycho_softc *psc_sc; 194 bus_addr_t psc_clr; /* clear register */ 195}; 196 197#define PSYCHO_READ8(sc, off) \ 198 bus_space_read_8((sc)->sc_bustag, (sc)->sc_bushandle, (off)) 199#define PSYCHO_WRITE8(sc, off, v) \ 200 bus_space_write_8((sc)->sc_bustag, (sc)->sc_bushandle, (off), (v)) 201#define PCICTL_READ8(sc, off) \ 202 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 203#define PCICTL_WRITE8(sc, off, v) \ 204 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 205 206/* 207 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 208 * single PCI bus and does not have a streaming buffer. It often has an APB 209 * (advanced PCI bridge) connected to it, which was designed specifically for 210 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 211 * appears as two "simba"'s underneath the sabre. 212 * 213 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 214 * and manages two PCI buses. "psycho" has two 64-bit 33MHz buses, while 215 * "psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 216 * will usually find a "psycho+" since I don't think the original "psycho" 217 * ever shipped, and if it did it would be in the U30. 218 * 219 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 220 * both part of the same IC, they only have a single register space. As such, 221 * they need to be configured together, even though the autoconfiguration will 222 * attach them separately. 223 * 224 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 225 * as pci1 and pci2, although they have been implemented with other PCI bus 226 * numbers on some machines. 227 * 228 * On UltraII machines, there can be any number of "psycho+" ICs, each 229 * providing two PCI buses. 230 * 231 * 232 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 233 * the values of the following interrupts in this order: 234 * 235 * PCI Bus Error (30) 236 * DMA UE (2e) 237 * DMA CE (2f) 238 * Power Fail (25) 239 * 240 * We really should attach handlers for each. 241 */ 242#ifdef DEBUGGER_ON_POWERFAIL 243#define PSYCHO_PWRFAIL_INT_FLAGS INTR_FAST 244#else 245#define PSYCHO_PWRFAIL_INT_FLAGS 0 246#endif 247 248#define OFW_PCI_TYPE "pci" 249 250struct psycho_desc { 251 char *pd_string; 252 int pd_mode; 253 char *pd_name; 254}; 255 256static struct psycho_desc psycho_compats[] = { 257 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 258 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre (US-IIi) compatible" }, 259 { "pci108e,a001", PSYCHO_MODE_SABRE, "Sabre (US-IIe) compatible" }, 260 { NULL, 0, NULL } 261}; 262 263static struct psycho_desc psycho_models[] = { 264 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 265 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 266 { NULL, 0, NULL } 267}; 268 269static struct psycho_desc * 270psycho_find_desc(struct psycho_desc *table, char *string) 271{ 272 struct psycho_desc *desc; 273 274 for (desc = table; desc->pd_string != NULL; desc++) { 275 if (strcmp(desc->pd_string, string) == 0) 276 return (desc); 277 } 278 return (NULL); 279} 280 281static struct psycho_desc * 282psycho_get_desc(phandle_t node, char *model) 283{ 284 struct psycho_desc *rv; 285 char compat[32]; 286 287 rv = NULL; 288 if (model != NULL) 289 rv = psycho_find_desc(psycho_models, model); 290 if (rv == NULL && 291 OF_getprop(node, "compatible", compat, sizeof(compat)) != -1) 292 rv = psycho_find_desc(psycho_compats, compat); 293 return (rv); 294} 295 296static int 297psycho_probe(device_t dev) 298{ 299 phandle_t node; 300 char *dtype; 301 302 node = nexus_get_node(dev); 303 dtype = nexus_get_device_type(dev); 304 if (nexus_get_reg(dev) != NULL && dtype != NULL && 305 strcmp(dtype, OFW_PCI_TYPE) == 0 && 306 psycho_get_desc(node, nexus_get_model(dev)) != NULL) { 307 device_set_desc(dev, "U2P UPA-PCI bridge"); 308 return (0); 309 } 310 311 return (ENXIO); 312} 313 314/* 315 * SUNW,psycho initialisation .. 316 * - find the per-psycho registers 317 * - figure out the IGN. 318 * - find our partner psycho 319 * - configure ourselves 320 * - bus range, bus, 321 * - interrupt map, 322 * - setup the chipsets. 323 * - if we're the first of the pair, initialise the IOMMU, otherwise 324 * just copy it's tags and addresses. 325 */ 326static int 327psycho_attach(device_t dev) 328{ 329 struct psycho_softc *sc; 330 struct psycho_softc *osc = NULL; 331 struct psycho_softc *asc; 332 struct upa_regs *reg; 333 struct ofw_pci_bdesc obd; 334 struct psycho_desc *desc; 335 phandle_t node; 336 u_int64_t csr; 337 u_long pcictl_offs, mlen; 338 int psycho_br[2]; 339 int n, i, nreg, rid; 340#if defined(PSYCHO_DEBUG) || defined(PSYCHO_STRAY) 341 bus_addr_t map, clr; 342 u_int64_t mr; 343#endif 344#ifdef PSYCHO_STRAY 345 struct psycho_strayclr *sclr; 346#endif 347 348 node = nexus_get_node(dev); 349 sc = device_get_softc(dev); 350 desc = psycho_get_desc(node, nexus_get_model(dev)); 351 352 sc->sc_node = node; 353 sc->sc_dev = dev; 354 sc->sc_dmatag = nexus_get_dmatag(dev); 355 sc->sc_mode = desc->pd_mode; 356 357 /* 358 * The psycho gets three register banks: 359 * (0) per-PBM configuration and status registers 360 * (1) per-PBM PCI configuration space, containing only the 361 * PBM 256-byte PCI header 362 * (2) the shared psycho configuration registers (struct psychoreg) 363 * 364 * XXX use the prom address for the psycho registers? we do so far. 365 */ 366 reg = nexus_get_reg(dev); 367 nreg = nexus_get_nreg(dev); 368 /* Register layouts are different. stuupid. */ 369 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 370 if (nreg <= 2) 371 panic("psycho_attach: %d not enough registers", nreg); 372 sc->sc_basepaddr = (vm_offset_t)UPA_REG_PHYS(®[2]); 373 mlen = UPA_REG_SIZE(®[2]); 374 pcictl_offs = UPA_REG_PHYS(®[0]); 375 } else { 376 if (nreg <= 0) 377 panic("psycho_attach: %d not enough registers", nreg); 378 sc->sc_basepaddr = (vm_offset_t)UPA_REG_PHYS(®[0]); 379 mlen = UPA_REG_SIZE(reg); 380 pcictl_offs = sc->sc_basepaddr + PSR_PCICTL0; 381 } 382 383 /* 384 * Match other psycho's that are already configured against 385 * the base physical address. This will be the same for a 386 * pair of devices that share register space. 387 */ 388 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 389 if (asc->sc_basepaddr == sc->sc_basepaddr) { 390 /* Found partner */ 391 osc = asc; 392 break; 393 } 394 } 395 396 if (osc == NULL) { 397 rid = 0; 398 sc->sc_mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 399 sc->sc_basepaddr, sc->sc_basepaddr + mlen - 1, mlen, 400 RF_ACTIVE); 401 if (sc->sc_mem_res == NULL || 402 rman_get_start(sc->sc_mem_res) != sc->sc_basepaddr) 403 panic("psycho_attach: can't allocate device memory"); 404 sc->sc_bustag = rman_get_bustag(sc->sc_mem_res); 405 sc->sc_bushandle = rman_get_bushandle(sc->sc_mem_res); 406 } else { 407 /* 408 * There's another psycho using the same register space. Copy the 409 * relevant stuff. 410 */ 411 sc->sc_mem_res = NULL; 412 sc->sc_bustag = osc->sc_bustag; 413 sc->sc_bushandle = osc->sc_bushandle; 414 } 415 if (pcictl_offs < sc->sc_basepaddr) 416 panic("psycho_attach: bogus pci control register location"); 417 sc->sc_pcictl = pcictl_offs - sc->sc_basepaddr; 418 csr = PSYCHO_READ8(sc, PSR_CS); 419 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 420 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 421 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 422 423 device_printf(dev, "%s, impl %d, version %d, ign %x ", 424 desc->pd_name, (int)PSYCHO_GCSR_IMPL(csr), 425 (int)PSYCHO_GCSR_VERS(csr), sc->sc_ign); 426 427 /* 428 * Setup the PCI control register 429 */ 430 csr = PCICTL_READ8(sc, PCR_CS); 431 csr |= PCICTL_MRLM | PCICTL_ARB_PARK | PCICTL_ERRINTEN | PCICTL_4ENABLE; 432 csr &= ~(PCICTL_SERR | PCICTL_CPU_PRIO | PCICTL_ARB_PRIO | 433 PCICTL_RTRYWAIT); 434 PCICTL_WRITE8(sc, PCR_CS, csr); 435 436 /* Grab the psycho ranges */ 437 psycho_get_ranges(sc->sc_node, &sc->sc_range, &sc->sc_nrange); 438 439 /* Initialize memory and i/o rmans */ 440 sc->sc_io_rman.rm_type = RMAN_ARRAY; 441 sc->sc_io_rman.rm_descr = "Psycho PCI I/O Ports"; 442 if (rman_init(&sc->sc_io_rman) != 0 || 443 rman_manage_region(&sc->sc_io_rman, 0, PSYCHO_IO_SIZE) != 0) 444 panic("psycho_probe: failed to set up i/o rman"); 445 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 446 sc->sc_mem_rman.rm_descr = "Psycho PCI Memory"; 447 if (rman_init(&sc->sc_mem_rman) != 0 || 448 rman_manage_region(&sc->sc_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 449 panic("psycho_probe: failed to set up memory rman"); 450 /* 451 * Find the addresses of the various bus spaces. 452 * There should not be multiple ones of one kind. 453 * The physical start addresses of the ranges are the configuration, 454 * memory and IO handles. 455 */ 456 for (n = 0; n < sc->sc_nrange; n++) { 457 i = UPA_RANGE_CS(&sc->sc_range[n]); 458 if (sc->sc_bh[i] != 0) 459 panic("psycho_attach: duplicate range for space %d", i); 460 sc->sc_bh[i] = UPA_RANGE_PHYS(&sc->sc_range[n]); 461 } 462 /* 463 * Check that all needed handles are present. The PCI_CS_MEM64 one is 464 * not currently used. 465 */ 466 for (n = 0; n < 3; n++) { 467 if (sc->sc_bh[n] == 0) 468 panic("psycho_attach: range %d missing", n); 469 } 470 471 /* allocate our tags */ 472 sc->sc_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 473 sc->sc_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 474 sc->sc_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 475 if (bus_dma_tag_create(sc->sc_dmatag, 8, 1, 0, 0x3ffffffff, NULL, NULL, 476 0x3ffffffff, 0xff, 0xffffffff, 0, &sc->sc_dmat) != 0) 477 panic("psycho_attach: bus_dma_tag_create failed"); 478 /* Customize the tag */ 479 sc->sc_dmat->cookie = sc; 480 sc->sc_dmat->dmamap_create = psycho_dmamap_create; 481 sc->sc_dmat->dmamap_destroy = psycho_dmamap_destroy; 482 sc->sc_dmat->dmamap_load = psycho_dmamap_load; 483 sc->sc_dmat->dmamap_unload = psycho_dmamap_unload; 484 sc->sc_dmat->dmamap_sync = psycho_dmamap_sync; 485 sc->sc_dmat->dmamem_alloc = psycho_dmamem_alloc; 486 sc->sc_dmat->dmamem_free = psycho_dmamem_free; 487 /* XXX: register as root dma tag (kluge). */ 488 sparc64_root_dma_tag = sc->sc_dmat; 489 490 /* Register the softc, this is needed for paired psychos. */ 491 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 492 493 /* 494 * And finally, if we're a sabre or the first of a pair of psycho's to 495 * arrive here, start up the IOMMU and get a config space tag. 496 */ 497 if (osc == NULL) { 498 /* 499 * Establish handlers for interesting interrupts.... 500 * 501 * XXX We need to remember these and remove this to support 502 * hotplug on the UPA/FHC bus. 503 * 504 * XXX Not all controllers have these, but installing them 505 * is better than trying to sort through this mess. 506 */ 507 psycho_set_intr(sc, 0, dev, PSR_UE_INT_MAP, INTR_FAST, 508 psycho_ue); 509 psycho_set_intr(sc, 1, dev, PSR_CE_INT_MAP, 0, psycho_ce); 510 psycho_set_intr(sc, 2, dev, PSR_PCIAERR_INT_MAP, INTR_FAST, 511 psycho_bus_a); 512 psycho_set_intr(sc, 4, dev, PSR_POWER_INT_MAP, 513 PSYCHO_PWRFAIL_INT_FLAGS, psycho_powerfail); 514 /* Psycho-specific initialization. */ 515 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 516 /* 517 * Sabres do not have the following two interrupts. 518 */ 519 psycho_set_intr(sc, 3, dev, PSR_PCIBERR_INT_MAP, 520 INTR_FAST, psycho_bus_b); 521#ifdef PSYCHO_MAP_WAKEUP 522 /* 523 * psycho_wakeup() doesn't do anything useful right 524 * now. 525 */ 526 psycho_set_intr(sc, 5, dev, PSR_PWRMGT_INT_MAP, 0, 527 psycho_wakeup); 528#endif /* PSYCHO_MAP_WAKEUP */ 529 530 /* Initialize the counter-timer. */ 531 sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, 532 PSR_TC0); 533 } 534 535 /* 536 * Setup IOMMU and PCI configuration if we're the first 537 * of a pair of psycho's to arrive here. 538 * 539 * We should calculate a TSB size based on amount of RAM 540 * and number of bus controllers and number an type of 541 * child devices. 542 * 543 * For the moment, 32KB should be more than enough. 544 */ 545 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 546 M_NOWAIT); 547 if (sc->sc_is == NULL) 548 panic("psycho_attach: malloc iommu_state failed"); 549 sc->sc_is->is_sb[0] = 0; 550 sc->sc_is->is_sb[1] = 0; 551 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 552 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 553 psycho_iommu_init(sc, 2); 554 } else { 555 /* Just copy IOMMU state, config tag and address */ 556 sc->sc_is = osc->sc_is; 557 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 558 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 559 iommu_reset(sc->sc_is); 560 } 561 562 /* 563 * Enable all interrupts, clear all interrupt states, and install an 564 * interrupt handler for OBIO interrupts, which can be ISA ones 565 * (to frob the interrupt clear registers). 566 * This aids the debugging of interrupt routing problems, and is needed 567 * for isa drivers that use isa_irq_pending (otherwise the registers 568 * will never be cleared). 569 */ 570#if defined(PSYCHO_DEBUG) || defined(PSYCHO_STRAY) 571 for (map = PSR_PCIA0_INT_MAP, clr = PSR_PCIA0_INT_CLR, n = 0; 572 map <= PSR_PCIB3_INT_MAP; map += 8, clr += 32, n++) { 573 mr = PSYCHO_READ8(sc, map); 574#ifdef PSYCHO_DEBUG 575 device_printf(dev, "intr map (pci) %d: %#lx\n", n, (u_long)mr); 576#endif 577 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 578 for (i = 0; i < 4; i++) 579 PCICTL_WRITE8(sc, clr + i * 8, 0); 580 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 581 } 582 for (map = PSR_SCSI_INT_MAP, clr = PSR_SCSI_INT_CLR, n = 0; 583 map <= PSR_SERIAL_INT_MAP; map += 8, clr += 8, n++) { 584 mr = PSYCHO_READ8(sc, map); 585#ifdef PSYCHO_DEBUG 586 device_printf(dev, "intr map (obio) %d: %#lx, clr: %#lx\n", n, 587 (u_long)mr, (u_long)clr); 588#endif 589 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 590 PSYCHO_WRITE8(sc, clr, 0); 591#ifdef PSYCHO_STRAY 592 /* 593 * This can cause interrupt storms, and is therefore disabled 594 * by default. 595 * XXX: use intr_setup() to not confuse higher level code 596 */ 597 if (INTVEC(mr) != 0x7e6 && INTVEC(mr) != 0x7e7 && 598 INTVEC(mr) != 0) { 599 sclr = malloc(sizeof(*sclr), M_DEVBUF, M_WAITOK); 600 sclr->psc_sc = sc; 601 sclr->psc_clr = clr; 602 intr_setup(PIL_LOW, intr_fast, INTVEC(mr), 603 psycho_intr_stray, sclr); 604 } 605#endif 606 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 607 } 608#endif 609 610 /* 611 * Get the bus range from the firmware; it is used solely for obtaining 612 * the inital bus number, and cannot be trusted on all machines. 613 */ 614 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br)); 615 if (n == -1) 616 panic("could not get psycho bus-range"); 617 if (n != sizeof(psycho_br)) 618 panic("broken psycho bus-range (%d)", n); 619 620 sc->sc_busno = ofw_pci_alloc_busno(sc->sc_node); 621 obd.obd_bus = psycho_br[0]; 622 obd.obd_secbus = obd.obd_subbus = sc->sc_busno; 623 obd.obd_slot = PCS_DEVICE; 624 obd.obd_func = PCS_FUNC; 625 obd.obd_init = psycho_binit; 626 obd.obd_super = NULL; 627 /* Initial setup. */ 628 psycho_binit(dev, &obd); 629 /* Update the bus number to what was just programmed. */ 630 obd.obd_bus = obd.obd_secbus; 631 /* 632 * Initialize the interrupt registers of all devices hanging from 633 * the host bridge directly or indirectly via PCI-PCI bridges. 634 * The MI code (and the PCI spec) assume that this is done during 635 * system initialization, however the firmware does not do this 636 * at least on some models, and we probably shouldn't trust that 637 * the firmware uses the same model as this driver if it does. 638 * Additionally, set up the bus numbers and ranges. 639 */ 640 ofw_pci_init(dev, sc->sc_node, sc->sc_ign, &obd); 641 642 device_add_child(dev, "pci", device_get_unit(dev)); 643 return (bus_generic_attach(dev)); 644} 645 646static void 647psycho_set_intr(struct psycho_softc *sc, int index, 648 device_t dev, bus_addr_t map, int iflags, driver_intr_t handler) 649{ 650 int rid, vec; 651 u_int64_t mr; 652 653 mr = PSYCHO_READ8(sc, map); 654 vec = INTVEC(mr); 655 sc->sc_irq_res[index] = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 656 vec, vec, 1, RF_ACTIVE); 657 if (sc->sc_irq_res[index] == NULL) 658 panic("psycho_set_intr: failed to get interrupt"); 659 bus_setup_intr(dev, sc->sc_irq_res[index], INTR_TYPE_MISC | iflags, 660 handler, sc, &sc->sc_ihand[index]); 661 PSYCHO_WRITE8(sc, map, INTMAP_ENABLE(mr, PCPU_GET(mid))); 662} 663 664static int 665psycho_find_intrmap(struct psycho_softc *sc, int ino, bus_addr_t *intrmapptr, 666 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 667{ 668 bus_addr_t intrmap, intrclr; 669 u_int64_t im; 670 u_long diag; 671 int found; 672 673 found = 0; 674 /* Hunt thru obio first */ 675 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 676 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 677 intrmap <= PSR_SERIAL_INT_MAP; intrmap += 8, intrclr += 8, 678 diag >>= 2) { 679 im = PSYCHO_READ8(sc, intrmap); 680 if (INTINO(im) == ino) { 681 diag &= 2; 682 found = 1; 683 break; 684 } 685 } 686 687 if (!found) { 688 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 689 /* Now do PCI interrupts */ 690 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 691 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 692 diag >>= 8) { 693 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 694 (intrmap == PSR_PCIA2_INT_MAP || 695 intrmap == PSR_PCIA3_INT_MAP)) 696 continue; 697 im = PSYCHO_READ8(sc, intrmap); 698 if (((im ^ ino) & 0x3c) == 0) { 699 intrclr += 8 * (ino & 3); 700 diag = (diag >> ((ino & 3) * 2)) & 2; 701 found = 1; 702 break; 703 } 704 } 705 } 706 if (intrmapptr != NULL) 707 *intrmapptr = intrmap; 708 if (intrclrptr != NULL) 709 *intrclrptr = intrclr; 710 if (intrdiagptr != NULL) 711 *intrdiagptr = diag; 712 return (found); 713} 714 715/* grovel the OBP for various psycho properties */ 716static void 717psycho_get_ranges(phandle_t node, struct upa_ranges **rp, int *np) 718{ 719 720 *np = OF_getprop_alloc(node, "ranges", sizeof(**rp), (void **)rp); 721 if (*np == -1) 722 panic("could not get psycho ranges"); 723} 724 725/* 726 * Interrupt handlers. 727 */ 728static void 729psycho_ue(void *arg) 730{ 731 struct psycho_softc *sc = (struct psycho_softc *)arg; 732 u_int64_t afar, afsr; 733 734 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 735 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 736 /* 737 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 738 * the AFAR to be set to the physical address of the TTE entry that 739 * was invalid/write protected. Call into the iommu code to have 740 * them decoded to virtual IO addresses. 741 */ 742 if ((afsr & UEAFSR_P_DTE) != 0) 743 iommu_decode_fault(sc->sc_is, afar); 744 /* It's uncorrectable. Dump the regs and panic. */ 745 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx\n", 746 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 747} 748 749static void 750psycho_ce(void *arg) 751{ 752 struct psycho_softc *sc = (struct psycho_softc *)arg; 753 u_int64_t afar, afsr; 754 755 PSYCHO_WRITE8(sc, PSR_CE_INT_CLR, 0); 756 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 757 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 758 /* It's correctable. Dump the regs and continue. */ 759 printf("%s: correctable DMA error AFAR %#lx AFSR %#lx\n", 760 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 761} 762 763static void 764psycho_bus_a(void *arg) 765{ 766 struct psycho_softc *sc = (struct psycho_softc *)arg; 767 u_int64_t afar, afsr; 768 769 afar = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFA); 770 afsr = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFS); 771 /* It's uncorrectable. Dump the regs and panic. */ 772 panic("%s: PCI bus A error AFAR %#lx AFSR %#lx\n", 773 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 774} 775 776static void 777psycho_bus_b(void *arg) 778{ 779 struct psycho_softc *sc = (struct psycho_softc *)arg; 780 u_int64_t afar, afsr; 781 782 afar = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFA); 783 afsr = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFS); 784 /* It's uncorrectable. Dump the regs and panic. */ 785 panic("%s: PCI bus B error AFAR %#lx AFSR %#lx\n", 786 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 787} 788 789static void 790psycho_powerfail(void *arg) 791{ 792 793 /* We lost power. Try to shut down NOW. */ 794#ifdef DEBUGGER_ON_POWERFAIL 795 struct psycho_softc *sc = (struct psycho_softc *)arg; 796 797 Debugger("powerfail"); 798 PSYCHO_WRITE8(sc, PSR_POWER_INT_CLR, 0); 799#else 800 printf("Power Failure Detected: Shutting down NOW.\n"); 801 shutdown_nice(0); 802#endif 803} 804 805#ifdef PSYCHO_MAP_WAKEUP 806static void 807psycho_wakeup(void *arg) 808{ 809 struct psycho_softc *sc = (struct psycho_softc *)arg; 810 811 PSYCHO_WRITE8(sc, PSR_PWRMGT_INT_CLR, 0); 812 /* Gee, we don't really have a framework to deal with this properly. */ 813 printf("%s: power management wakeup\n", device_get_name(sc->sc_dev)); 814} 815#endif /* PSYCHO_MAP_WAKEUP */ 816 817/* initialise the IOMMU... */ 818void 819psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 820{ 821 char *name; 822 struct iommu_state *is = sc->sc_is; 823 u_int32_t iobase = -1; 824 int *vdma = NULL; 825 int nitem; 826 827 /* punch in our copies */ 828 is->is_bustag = sc->sc_bustag; 829 is->is_bushandle = sc->sc_bushandle; 830 is->is_iommu = PSR_IOMMU; 831 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 832 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 833 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 834 is->is_dva = PSR_IOMMU_SVADIAG; 835 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 836 837 /* 838 * Separate the men from the boys. Get the `virtual-dma' 839 * property for sabre and use that to make sure the damn 840 * iommu works. 841 * 842 * We could query the `#virtual-dma-size-cells' and 843 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 844 */ 845 nitem = OF_getprop_alloc(sc->sc_node, "virtual-dma", sizeof(vdma), 846 (void **)&vdma); 847 if (nitem > 0) { 848 iobase = vdma[0]; 849 tsbsize = ffs(vdma[1]); 850 if (tsbsize < 25 || tsbsize > 31 || 851 (vdma[1] & ~(1 << (tsbsize - 1))) != 0) { 852 printf("bogus tsb size %x, using 7\n", vdma[1]); 853 tsbsize = 31; 854 } 855 tsbsize -= 24; 856 free(vdma, M_OFWPROP); 857 } 858 859 /* give us a nice name.. */ 860 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 861 if (name == 0) 862 panic("couldn't malloc iommu name"); 863 snprintf(name, 32, "%s dvma", device_get_name(sc->sc_dev)); 864 865 iommu_init(name, is, tsbsize, iobase, 0); 866} 867 868static void 869psycho_binit(device_t busdev, struct ofw_pci_bdesc *obd) 870{ 871 872#ifdef PSYCHO_DEBUG 873 printf("psycho at %u/%u/%u: setting bus #s to %u/%u/%u\n", 874 obd->obd_bus, obd->obd_slot, obd->obd_func, obd->obd_bus, 875 obd->obd_secbus, obd->obd_subbus); 876#endif /* PSYCHO_DEBUG */ 877 /* 878 * NOTE: this must be kept in this order, since the last write will 879 * change the config space address of the psycho. 880 */ 881 PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func, 882 PCSR_SUBBUS, obd->obd_subbus, 1); 883 PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func, 884 PCSR_SECBUS, obd->obd_secbus, 1); 885} 886 887static int 888psycho_maxslots(device_t dev) 889{ 890 891 /* 892 * XXX: is this correct? At any rate, a number that is too high 893 * shouldn't do any harm, if only because of the way things are 894 * handled in psycho_read_config. 895 */ 896 return (31); 897} 898 899/* 900 * Keep a table of quirky PCI devices that need fixups before the MI PCI code 901 * creates the resource lists. This needs to be moved around once other bus 902 * drivers are added. Moving it to the MI code should maybe be reconsidered 903 * if one of these devices appear in non-sparc64 boxen. It's likely that not 904 * all BIOSes/firmwares can deal with them. 905 */ 906struct psycho_dquirk { 907 u_int32_t dq_devid; 908 int dq_quirk; 909}; 910 911/* Quirk types. May be or'ed together. */ 912#define DQT_BAD_INTPIN 1 /* Intpin reg 0, but intpin used */ 913 914static struct psycho_dquirk dquirks[] = { 915 { 0x1001108e, DQT_BAD_INTPIN }, /* Sun HME (PCIO func. 1) */ 916 { 0x1101108e, DQT_BAD_INTPIN }, /* Sun GEM (PCIO2 func. 1) */ 917 { 0x1102108e, DQT_BAD_INTPIN }, /* Sun FireWire ctl. (PCIO2 func. 2) */ 918 { 0x1103108e, DQT_BAD_INTPIN }, /* Sun USB ctl. (PCIO2 func. 3) */ 919}; 920 921#define NDQUIRKS (sizeof(dquirks) / sizeof(dquirks[0])) 922 923static u_int32_t 924psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 925 int width) 926{ 927 struct psycho_softc *sc; 928 bus_space_handle_t bh; 929 u_long offset = 0; 930 u_int32_t r, devid; 931 int i; 932 933 /* 934 * The psycho bridge does not tolerate accesses to unconfigured PCI 935 * devices' or function's config space, so look up the device in the 936 * firmware device tree first, and if it is not present, return a value 937 * that will make the detection code think that there is no device here. 938 * This is ugly... 939 */ 940 if (reg == 0 && ofw_pci_find_node(bus, slot, func) == 0) 941 return (0xffffffff); 942 sc = (struct psycho_softc *)device_get_softc(dev); 943 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 944 bh = sc->sc_bh[PCI_CS_CONFIG]; 945 switch (width) { 946 case 1: 947 r = bus_space_read_1(sc->sc_cfgt, bh, offset); 948 break; 949 case 2: 950 r = bus_space_read_2(sc->sc_cfgt, bh, offset); 951 break; 952 case 4: 953 r = bus_space_read_4(sc->sc_cfgt, bh, offset); 954 break; 955 default: 956 panic("psycho_read_config: bad width"); 957 } 958 if (reg == PCIR_INTPIN && r == 0) { 959 /* Check for DQT_BAD_INTPIN quirk. */ 960 devid = psycho_read_config(dev, bus, slot, func, 961 PCIR_DEVVENDOR, 4); 962 for (i = 0; i < NDQUIRKS; i++) { 963 if (dquirks[i].dq_devid == devid) { 964 /* 965 * Need to set the intpin to a value != 0 so 966 * that the MI code will think that this device 967 * has an interrupt. 968 * Just use 1 (intpin a) for now. This is, of 969 * course, bogus, but since interrupts are 970 * routed in advance, this does not really 971 * matter. 972 */ 973 if ((dquirks[i].dq_quirk & DQT_BAD_INTPIN) != 0) 974 r = 1; 975 break; 976 } 977 } 978 } 979 return (r); 980} 981 982static void 983psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, 984 u_int reg, u_int32_t val, int width) 985{ 986 struct psycho_softc *sc; 987 bus_space_handle_t bh; 988 u_long offset = 0; 989 990 sc = (struct psycho_softc *)device_get_softc(dev); 991 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 992 bh = sc->sc_bh[PCI_CS_CONFIG]; 993 switch (width) { 994 case 1: 995 bus_space_write_1(sc->sc_cfgt, bh, offset, val); 996 break; 997 case 2: 998 bus_space_write_2(sc->sc_cfgt, bh, offset, val); 999 break; 1000 case 4: 1001 bus_space_write_4(sc->sc_cfgt, bh, offset, val); 1002 break; 1003 default: 1004 panic("psycho_write_config: bad width"); 1005 } 1006} 1007 1008static int 1009psycho_route_interrupt(device_t bus, device_t dev, int pin) 1010{ 1011 1012 /* 1013 * XXX: ugly loathsome hack: 1014 * We can't use ofw_pci_route_intr() here; the device passed may be 1015 * the one of a bridge, so the original device can't be recovered. 1016 * 1017 * We need to use the firmware to route interrupts, however it has 1018 * no interface which could be used to interpret intpins; instead, 1019 * all assignments are done by device. 1020 * 1021 * The MI pci code will try to reroute interrupts of 0, although they 1022 * are correct; all other interrupts are preinitialized, so if we 1023 * get here, the intline is either 0 (so return 0), or we hit a 1024 * device which was not preinitialized (e.g. hotplugged stuff), in 1025 * which case we are lost. 1026 */ 1027 return (0); 1028} 1029 1030static int 1031psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1032{ 1033 struct psycho_softc *sc; 1034 1035 sc = (struct psycho_softc *)device_get_softc(dev); 1036 switch (which) { 1037 case PCIB_IVAR_BUS: 1038 *result = sc->sc_busno; 1039 return (0); 1040 } 1041 return (ENOENT); 1042} 1043 1044/* Write to the correct clr register, and call the actual handler. */ 1045static void 1046psycho_intr_stub(void *arg) 1047{ 1048 struct psycho_clr *pc; 1049 1050 pc = (struct psycho_clr *)arg; 1051 pc->pci_handler(pc->pci_arg); 1052 PSYCHO_WRITE8(pc->pci_sc, pc->pci_clr, 0); 1053} 1054 1055#ifdef PSYCHO_STRAY 1056/* 1057 * Write to the correct clr register and return. arg is the address of the clear 1058 * register to be used. 1059 * XXX: print a message? 1060 */ 1061static void 1062psycho_intr_stray(void *arg) 1063{ 1064 struct psycho_strayclr *sclr = arg; 1065 1066 PSYCHO_WRITE8(sclr->psc_sc, sclr->psc_clr, 0); 1067} 1068#endif 1069 1070static int 1071psycho_setup_intr(device_t dev, device_t child, 1072 struct resource *ires, int flags, driver_intr_t *intr, void *arg, 1073 void **cookiep) 1074{ 1075 struct psycho_softc *sc; 1076 struct psycho_clr *pc; 1077 bus_addr_t intrmapptr, intrclrptr; 1078 long vec = rman_get_start(ires); 1079 u_int64_t mr; 1080 int ino, error; 1081 1082 sc = (struct psycho_softc *)device_get_softc(dev); 1083 pc = (struct psycho_clr *)malloc(sizeof(*pc), M_DEVBUF, M_NOWAIT); 1084 if (pc == NULL) 1085 return (NULL); 1086 1087 /* 1088 * Hunt through all the interrupt mapping regs to look for our 1089 * interrupt vector. 1090 * 1091 * XXX We only compare INOs rather than IGNs since the firmware may 1092 * not provide the IGN and the IGN is constant for all device on that 1093 * PCI controller. This could cause problems for the FFB/external 1094 * interrupt which has a full vector that can be set arbitrarily. 1095 */ 1096 ino = INTINO(vec); 1097 1098 if (!psycho_find_intrmap(sc, ino, &intrmapptr, &intrclrptr, NULL)) { 1099 printf("Cannot find interrupt vector %lx\n", vec); 1100 free(pc, M_DEVBUF); 1101 return (NULL); 1102 } 1103 1104#ifdef PSYCHO_DEBUG 1105 device_printf(dev, "psycho_setup_intr: INO %d, map %#lx, clr %#lx\n", 1106 ino, (u_long)intrmapptr, (u_long)intrclrptr); 1107#endif 1108 pc->pci_sc = sc; 1109 pc->pci_arg = arg; 1110 pc->pci_handler = intr; 1111 pc->pci_clr = intrclrptr; 1112 /* Disable the interrupt while we fiddle with it */ 1113 mr = PSYCHO_READ8(sc, intrmapptr); 1114 PSYCHO_WRITE8(sc, intrmapptr, mr & ~INTMAP_V); 1115 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 1116 psycho_intr_stub, pc, cookiep); 1117 if (error != 0) { 1118 free(pc, M_DEVBUF); 1119 return (error); 1120 } 1121 pc->pci_cookie = *cookiep; 1122 *cookiep = pc; 1123 1124 /* 1125 * Clear the interrupt, it might have been triggered before it was 1126 * set up. 1127 */ 1128 PSYCHO_WRITE8(sc, intrclrptr, 0); 1129 /* 1130 * Enable the interrupt and program the target module now we have the 1131 * handler installed. 1132 */ 1133 PSYCHO_WRITE8(sc, intrmapptr, INTMAP_ENABLE(mr, PCPU_GET(mid))); 1134 return (error); 1135} 1136 1137static int 1138psycho_teardown_intr(device_t dev, device_t child, 1139 struct resource *vec, void *cookie) 1140{ 1141 struct psycho_clr *pc; 1142 int error; 1143 1144 pc = (struct psycho_clr *)cookie; 1145 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 1146 pc->pci_cookie); 1147 /* 1148 * Don't disable the interrupt for now, so that stray interupts get 1149 * detected... 1150 */ 1151 if (error != 0) 1152 free(pc, M_DEVBUF); 1153 return (error); 1154} 1155 1156static struct resource * 1157psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1158 u_long start, u_long end, u_long count, u_int flags) 1159{ 1160 struct psycho_softc *sc; 1161 struct resource *rv; 1162 struct rman *rm; 1163 bus_space_tag_t bt; 1164 bus_space_handle_t bh; 1165 int needactivate = flags & RF_ACTIVE; 1166 1167 flags &= ~RF_ACTIVE; 1168 1169 sc = (struct psycho_softc *)device_get_softc(bus); 1170 if (type == SYS_RES_IRQ) { 1171 /* 1172 * XXX: Don't accept blank ranges for now, only single 1173 * interrupts. The other case should not happen with the MI pci 1174 * code... 1175 * XXX: This may return a resource that is out of the range 1176 * that was specified. Is this correct...? 1177 */ 1178 if (start != end) 1179 panic("psycho_alloc_resource: XXX: interrupt range"); 1180 start = end |= sc->sc_ign; 1181 return (bus_alloc_resource(bus, type, rid, start, end, 1182 count, flags)); 1183 } 1184 switch (type) { 1185 case SYS_RES_MEMORY: 1186 rm = &sc->sc_mem_rman; 1187 bt = sc->sc_memt; 1188 bh = sc->sc_bh[PCI_CS_MEM32]; 1189 break; 1190 case SYS_RES_IOPORT: 1191 rm = &sc->sc_io_rman; 1192 bt = sc->sc_iot; 1193 /* XXX: probably should use ranges property here. */ 1194 bh = sc->sc_bh[PCI_CS_IO]; 1195 break; 1196 default: 1197 return (NULL); 1198 } 1199 1200 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1201 if (rv == NULL) 1202 return (NULL); 1203 1204 bh += rman_get_start(rv); 1205 rman_set_bustag(rv, bt); 1206 rman_set_bushandle(rv, bh); 1207 1208 if (needactivate) { 1209 if (bus_activate_resource(child, type, *rid, rv)) { 1210 rman_release_resource(rv); 1211 return (NULL); 1212 } 1213 } 1214 1215 return (rv); 1216} 1217 1218static int 1219psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1220 struct resource *r) 1221{ 1222 void *p; 1223 int error; 1224 1225 if (type == SYS_RES_IRQ) 1226 return (bus_activate_resource(bus, type, rid, r)); 1227 if (type == SYS_RES_MEMORY) { 1228 /* 1229 * Need to memory-map the device space, as some drivers depend 1230 * on the virtual address being set and useable. 1231 */ 1232 error = sparc64_bus_mem_map(rman_get_bustag(r), 1233 rman_get_bushandle(r), rman_get_size(r), 0, NULL, &p); 1234 if (error != 0) 1235 return (error); 1236 rman_set_virtual(r, p); 1237 } 1238 return (rman_activate_resource(r)); 1239} 1240 1241static int 1242psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1243 struct resource *r) 1244{ 1245 1246 if (type == SYS_RES_IRQ) 1247 return (bus_deactivate_resource(bus, type, rid, r)); 1248 if (type == SYS_RES_MEMORY) { 1249 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1250 rman_set_virtual(r, NULL); 1251 } 1252 return (rman_deactivate_resource(r)); 1253} 1254 1255static int 1256psycho_release_resource(device_t bus, device_t child, int type, int rid, 1257 struct resource *r) 1258{ 1259 int error; 1260 1261 if (type == SYS_RES_IRQ) 1262 return (bus_release_resource(bus, type, rid, r)); 1263 if (rman_get_flags(r) & RF_ACTIVE) { 1264 error = bus_deactivate_resource(child, type, rid, r); 1265 if (error) 1266 return error; 1267 } 1268 return (rman_release_resource(r)); 1269} 1270 1271static int 1272psycho_intr_pending(device_t dev, int intr) 1273{ 1274 struct psycho_softc *sc; 1275 u_long diag; 1276 1277 sc = (struct psycho_softc *)device_get_softc(dev); 1278 if (!psycho_find_intrmap(sc, intr, NULL, NULL, &diag)) { 1279 printf("psycho_intr_pending: mapping not found for %d\n", intr); 1280 return (0); 1281 } 1282 return (diag != 0); 1283} 1284 1285static bus_space_handle_t 1286psycho_get_bus_handle(device_t dev, enum sbbt_id id, 1287 bus_space_handle_t childhdl, bus_space_tag_t *tag) 1288{ 1289 struct psycho_softc *sc; 1290 1291 sc = (struct psycho_softc *)device_get_softc(dev); 1292 switch(id) { 1293 case SBBT_IO: 1294 *tag = sc->sc_iot; 1295 return (sc->sc_bh[PCI_CS_IO] + childhdl); 1296 case SBBT_MEM: 1297 *tag = sc->sc_memt; 1298 return (sc->sc_bh[PCI_CS_MEM32] + childhdl); 1299 default: 1300 panic("psycho_get_bus_handle: illegal space\n"); 1301 } 1302} 1303 1304/* 1305 * below here is bus space and bus dma support 1306 */ 1307static bus_space_tag_t 1308psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1309{ 1310 bus_space_tag_t bt; 1311 1312 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1313 M_NOWAIT | M_ZERO); 1314 if (bt == NULL) 1315 panic("psycho_alloc_bus_tag: out of memory"); 1316 1317 bzero(bt, sizeof *bt); 1318 bt->cookie = sc; 1319 bt->parent = sc->sc_bustag; 1320 bt->type = type; 1321 return (bt); 1322} 1323 1324/* 1325 * hooks into the iommu dvma calls. 1326 */ 1327static int 1328psycho_dmamem_alloc(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void **vaddr, 1329 int flags, bus_dmamap_t *mapp) 1330{ 1331 struct psycho_softc *sc; 1332 1333 sc = (struct psycho_softc *)pdmat->cookie; 1334 return (iommu_dvmamem_alloc(pdmat, ddmat, sc->sc_is, vaddr, flags, 1335 mapp)); 1336} 1337 1338static void 1339psycho_dmamem_free(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void *vaddr, 1340 bus_dmamap_t map) 1341{ 1342 struct psycho_softc *sc; 1343 1344 sc = (struct psycho_softc *)pdmat->cookie; 1345 iommu_dvmamem_free(pdmat, ddmat, sc->sc_is, vaddr, map); 1346} 1347 1348static int 1349psycho_dmamap_create(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, int flags, 1350 bus_dmamap_t *mapp) 1351{ 1352 struct psycho_softc *sc; 1353 1354 sc = (struct psycho_softc *)pdmat->cookie; 1355 return (iommu_dvmamap_create(pdmat, ddmat, sc->sc_is, flags, mapp)); 1356 1357} 1358 1359static int 1360psycho_dmamap_destroy(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, 1361 bus_dmamap_t map) 1362{ 1363 struct psycho_softc *sc; 1364 1365 sc = (struct psycho_softc *)pdmat->cookie; 1366 return (iommu_dvmamap_destroy(pdmat, ddmat, sc->sc_is, map)); 1367} 1368 1369static int 1370psycho_dmamap_load(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map, 1371 void *buf, bus_size_t buflen, bus_dmamap_callback_t *callback, 1372 void *callback_arg, int flags) 1373{ 1374 struct psycho_softc *sc; 1375 1376 sc = (struct psycho_softc *)pdmat->cookie; 1377 return (iommu_dvmamap_load(pdmat, ddmat, sc->sc_is, map, buf, buflen, 1378 callback, callback_arg, flags)); 1379} 1380 1381static void 1382psycho_dmamap_unload(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map) 1383{ 1384 struct psycho_softc *sc; 1385 1386 sc = (struct psycho_softc *)pdmat->cookie; 1387 iommu_dvmamap_unload(pdmat, ddmat, sc->sc_is, map); 1388} 1389 1390static void 1391psycho_dmamap_sync(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map, 1392 bus_dmasync_op_t op) 1393{ 1394 struct psycho_softc *sc; 1395 1396 sc = (struct psycho_softc *)pdmat->cookie; 1397 iommu_dvmamap_sync(pdmat, ddmat, sc->sc_is, map, op); 1398} 1399