psycho.c revision 107476
1/* 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * All rights reserved. 4 * Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 30 * 31 * $FreeBSD: head/sys/sparc64/pci/psycho.c 107476 2002-12-01 23:21:15Z tmm $ 32 */ 33 34/* 35 * Support for `psycho' and `psycho+' UPA to PCI bridge and 36 * UltraSPARC IIi and IIe `sabre' PCI controllers. 37 */ 38 39#include "opt_psycho.h" 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/kernel.h> 45#include <sys/malloc.h> 46 47#include <ofw/openfirm.h> 48#include <ofw/ofw_pci.h> 49 50#include <machine/bus.h> 51#include <machine/iommureg.h> 52#include <machine/bus_common.h> 53#include <machine/frame.h> 54#include <machine/intr_machdep.h> 55#include <machine/nexusvar.h> 56#include <machine/ofw_upa.h> 57#include <machine/resource.h> 58 59#include <sys/rman.h> 60 61#include <machine/iommuvar.h> 62 63#include <pci/pcivar.h> 64#include <pci/pcireg.h> 65 66#include <sparc64/pci/ofw_pci.h> 67#include <sparc64/pci/psychoreg.h> 68#include <sparc64/pci/psychovar.h> 69 70#include "pcib_if.h" 71#include "sparcbus_if.h" 72 73static void psycho_get_ranges(phandle_t, struct upa_ranges **, int *); 74static void psycho_set_intr(struct psycho_softc *, int, device_t, bus_addr_t, 75 int, driver_intr_t); 76static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *, 77 bus_addr_t *, u_long *); 78static void psycho_intr_stub(void *); 79#ifdef PSYCHO_STRAY 80static void psycho_intr_stray(void *); 81#endif 82static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 83 84 85/* Interrupt handlers */ 86static void psycho_ue(void *); 87static void psycho_ce(void *); 88static void psycho_bus_a(void *); 89static void psycho_bus_b(void *); 90static void psycho_powerfail(void *); 91#ifdef PSYCHO_MAP_WAKEUP 92static void psycho_wakeup(void *); 93#endif 94 95/* IOMMU support */ 96static void psycho_iommu_init(struct psycho_softc *, int); 97static ofw_pci_binit_t psycho_binit; 98 99/* 100 * bus space and bus dma support for UltraSPARC `psycho'. note that most 101 * of the bus dma support is provided by the iommu dvma controller. 102 */ 103static int psycho_dmamap_create(bus_dma_tag_t, bus_dma_tag_t, int, 104 bus_dmamap_t *); 105static int psycho_dmamap_destroy(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 106static int psycho_dmamap_load(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 107 void *, bus_size_t, bus_dmamap_callback_t *, void *, int); 108static void psycho_dmamap_unload(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 109static void psycho_dmamap_sync(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 110 bus_dmasync_op_t); 111static int psycho_dmamem_alloc(bus_dma_tag_t, bus_dma_tag_t, void **, int, 112 bus_dmamap_t *); 113static void psycho_dmamem_free(bus_dma_tag_t, bus_dma_tag_t, void *, 114 bus_dmamap_t); 115 116/* 117 * autoconfiguration 118 */ 119static int psycho_probe(device_t); 120static int psycho_attach(device_t); 121static int psycho_read_ivar(device_t, device_t, int, u_long *); 122static int psycho_setup_intr(device_t, device_t, struct resource *, int, 123 driver_intr_t *, void *, void **); 124static int psycho_teardown_intr(device_t, device_t, struct resource *, void *); 125static struct resource *psycho_alloc_resource(device_t, device_t, int, int *, 126 u_long, u_long, u_long, u_int); 127static int psycho_activate_resource(device_t, device_t, int, int, 128 struct resource *); 129static int psycho_deactivate_resource(device_t, device_t, int, int, 130 struct resource *); 131static int psycho_release_resource(device_t, device_t, int, int, 132 struct resource *); 133static int psycho_maxslots(device_t); 134static u_int32_t psycho_read_config(device_t, u_int, u_int, u_int, u_int, int); 135static void psycho_write_config(device_t, u_int, u_int, u_int, u_int, u_int32_t, 136 int); 137static int psycho_route_interrupt(device_t, device_t, int); 138static int psycho_intr_pending(device_t, int); 139static bus_space_handle_t psycho_get_bus_handle(device_t dev, enum sbbt_id id, 140 bus_space_handle_t childhdl, bus_space_tag_t *tag); 141 142static device_method_t psycho_methods[] = { 143 /* Device interface */ 144 DEVMETHOD(device_probe, psycho_probe), 145 DEVMETHOD(device_attach, psycho_attach), 146 147 /* Bus interface */ 148 DEVMETHOD(bus_print_child, bus_generic_print_child), 149 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 150 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 151 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 152 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 153 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 154 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 155 DEVMETHOD(bus_release_resource, psycho_release_resource), 156 157 /* pcib interface */ 158 DEVMETHOD(pcib_maxslots, psycho_maxslots), 159 DEVMETHOD(pcib_read_config, psycho_read_config), 160 DEVMETHOD(pcib_write_config, psycho_write_config), 161 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 162 163 /* sparcbus interface */ 164 DEVMETHOD(sparcbus_intr_pending, psycho_intr_pending), 165 DEVMETHOD(sparcbus_get_bus_handle, psycho_get_bus_handle), 166 167 { 0, 0 } 168}; 169 170static driver_t psycho_driver = { 171 "pcib", 172 psycho_methods, 173 sizeof(struct psycho_softc), 174}; 175 176static devclass_t psycho_devclass; 177 178DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 179 180SLIST_HEAD(, psycho_softc) psycho_softcs = 181 SLIST_HEAD_INITIALIZER(psycho_softcs); 182 183struct psycho_clr { 184 struct psycho_softc *pci_sc; 185 bus_addr_t pci_clr; /* clear register */ 186 driver_intr_t *pci_handler; /* handler to call */ 187 void *pci_arg; /* argument for the handler */ 188 void *pci_cookie; /* interrupt cookie of parent bus */ 189}; 190 191struct psycho_strayclr { 192 struct psycho_softc *psc_sc; 193 bus_addr_t psc_clr; /* clear register */ 194}; 195 196#define PSYCHO_READ8(sc, off) \ 197 bus_space_read_8((sc)->sc_bustag, (sc)->sc_bushandle, (off)) 198#define PSYCHO_WRITE8(sc, off, v) \ 199 bus_space_write_8((sc)->sc_bustag, (sc)->sc_bushandle, (off), (v)) 200#define PCICTL_READ8(sc, off) \ 201 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 202#define PCICTL_WRITE8(sc, off, v) \ 203 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 204 205/* 206 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 207 * single PCI bus and does not have a streaming buffer. It often has an APB 208 * (advanced PCI bridge) connected to it, which was designed specifically for 209 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 210 * appears as two "simba"'s underneath the sabre. 211 * 212 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 213 * and manages two PCI buses. "psycho" has two 64-bit 33MHz buses, while 214 * "psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 215 * will usually find a "psycho+" since I don't think the original "psycho" 216 * ever shipped, and if it did it would be in the U30. 217 * 218 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 219 * both part of the same IC, they only have a single register space. As such, 220 * they need to be configured together, even though the autoconfiguration will 221 * attach them separately. 222 * 223 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 224 * as pci1 and pci2, although they have been implemented with other PCI bus 225 * numbers on some machines. 226 * 227 * On UltraII machines, there can be any number of "psycho+" ICs, each 228 * providing two PCI buses. 229 * 230 * 231 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 232 * the values of the following interrupts in this order: 233 * 234 * PCI Bus Error (30) 235 * DMA UE (2e) 236 * DMA CE (2f) 237 * Power Fail (25) 238 * 239 * We really should attach handlers for each. 240 */ 241#ifdef DEBUGGER_ON_POWERFAIL 242#define PSYCHO_PWRFAIL_INT_FLAGS INTR_FAST 243#else 244#define PSYCHO_PWRFAIL_INT_FLAGS 0 245#endif 246 247#define OFW_PCI_TYPE "pci" 248 249struct psycho_desc { 250 char *pd_string; 251 int pd_mode; 252 char *pd_name; 253}; 254 255static struct psycho_desc psycho_compats[] = { 256 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 257 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre (US-IIi) compatible" }, 258 { "pci108e,a001", PSYCHO_MODE_SABRE, "Sabre (US-IIe) compatible" }, 259 { NULL, 0, NULL } 260}; 261 262static struct psycho_desc psycho_models[] = { 263 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 264 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 265 { NULL, 0, NULL } 266}; 267 268static struct psycho_desc * 269psycho_find_desc(struct psycho_desc *table, char *string) 270{ 271 struct psycho_desc *desc; 272 273 for (desc = table; desc->pd_string != NULL; desc++) { 274 if (strcmp(desc->pd_string, string) == 0) 275 return (desc); 276 } 277 return (NULL); 278} 279 280static struct psycho_desc * 281psycho_get_desc(phandle_t node, char *model) 282{ 283 struct psycho_desc *rv; 284 char compat[32]; 285 286 rv = NULL; 287 if (model != NULL) 288 rv = psycho_find_desc(psycho_models, model); 289 if (rv == NULL && 290 OF_getprop(node, "compatible", compat, sizeof(compat)) != -1) 291 rv = psycho_find_desc(psycho_compats, compat); 292 return (rv); 293} 294 295static int 296psycho_probe(device_t dev) 297{ 298 phandle_t node; 299 char *dtype; 300 301 node = nexus_get_node(dev); 302 dtype = nexus_get_device_type(dev); 303 if (nexus_get_reg(dev) != NULL && dtype != NULL && 304 strcmp(dtype, OFW_PCI_TYPE) == 0 && 305 psycho_get_desc(node, nexus_get_model(dev)) != NULL) { 306 device_set_desc(dev, "U2P UPA-PCI bridge"); 307 return (0); 308 } 309 310 return (ENXIO); 311} 312 313/* 314 * SUNW,psycho initialisation .. 315 * - find the per-psycho registers 316 * - figure out the IGN. 317 * - find our partner psycho 318 * - configure ourselves 319 * - bus range, bus, 320 * - interrupt map, 321 * - setup the chipsets. 322 * - if we're the first of the pair, initialise the IOMMU, otherwise 323 * just copy it's tags and addresses. 324 */ 325static int 326psycho_attach(device_t dev) 327{ 328 struct psycho_softc *sc; 329 struct psycho_softc *osc = NULL; 330 struct psycho_softc *asc; 331 struct upa_regs *reg; 332 struct ofw_pci_bdesc obd; 333 struct psycho_desc *desc; 334 phandle_t node; 335 u_int64_t csr; 336 u_long pcictl_offs, mlen; 337 int psycho_br[2]; 338 int n, i, nreg, rid; 339#if defined(PSYCHO_DEBUG) || defined(PSYCHO_STRAY) 340 bus_addr_t map, clr; 341 u_int64_t mr; 342#endif 343#ifdef PSYCHO_STRAY 344 struct psycho_strayclr *sclr; 345#endif 346 347 node = nexus_get_node(dev); 348 sc = device_get_softc(dev); 349 desc = psycho_get_desc(node, nexus_get_model(dev)); 350 351 sc->sc_node = node; 352 sc->sc_dev = dev; 353 sc->sc_dmatag = nexus_get_dmatag(dev); 354 sc->sc_mode = desc->pd_mode; 355 356 /* 357 * The psycho gets three register banks: 358 * (0) per-PBM configuration and status registers 359 * (1) per-PBM PCI configuration space, containing only the 360 * PBM 256-byte PCI header 361 * (2) the shared psycho configuration registers (struct psychoreg) 362 * 363 * XXX use the prom address for the psycho registers? we do so far. 364 */ 365 reg = nexus_get_reg(dev); 366 nreg = nexus_get_nreg(dev); 367 /* Register layouts are different. stuupid. */ 368 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 369 if (nreg <= 2) 370 panic("psycho_attach: %d not enough registers", nreg); 371 sc->sc_basepaddr = (vm_offset_t)UPA_REG_PHYS(®[2]); 372 mlen = UPA_REG_SIZE(®[2]); 373 pcictl_offs = UPA_REG_PHYS(®[0]); 374 } else { 375 if (nreg <= 0) 376 panic("psycho_attach: %d not enough registers", nreg); 377 sc->sc_basepaddr = (vm_offset_t)UPA_REG_PHYS(®[0]); 378 mlen = UPA_REG_SIZE(reg); 379 pcictl_offs = sc->sc_basepaddr + PSR_PCICTL0; 380 } 381 382 /* 383 * Match other psycho's that are already configured against 384 * the base physical address. This will be the same for a 385 * pair of devices that share register space. 386 */ 387 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 388 if (asc->sc_basepaddr == sc->sc_basepaddr) { 389 /* Found partner */ 390 osc = asc; 391 break; 392 } 393 } 394 395 if (osc == NULL) { 396 rid = 0; 397 sc->sc_mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 398 sc->sc_basepaddr, sc->sc_basepaddr + mlen - 1, mlen, 399 RF_ACTIVE); 400 if (sc->sc_mem_res == NULL || 401 rman_get_start(sc->sc_mem_res) != sc->sc_basepaddr) 402 panic("psycho_attach: can't allocate device memory"); 403 sc->sc_bustag = rman_get_bustag(sc->sc_mem_res); 404 sc->sc_bushandle = rman_get_bushandle(sc->sc_mem_res); 405 } else { 406 /* 407 * There's another psycho using the same register space. Copy the 408 * relevant stuff. 409 */ 410 sc->sc_mem_res = NULL; 411 sc->sc_bustag = osc->sc_bustag; 412 sc->sc_bushandle = osc->sc_bushandle; 413 } 414 if (pcictl_offs < sc->sc_basepaddr) 415 panic("psycho_attach: bogus pci control register location"); 416 sc->sc_pcictl = pcictl_offs - sc->sc_basepaddr; 417 csr = PSYCHO_READ8(sc, PSR_CS); 418 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 419 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 420 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 421 422 device_printf(dev, "%s, impl %d, version %d, ign %x ", 423 desc->pd_name, (int)PSYCHO_GCSR_IMPL(csr), 424 (int)PSYCHO_GCSR_VERS(csr), sc->sc_ign); 425 426 /* 427 * Setup the PCI control register 428 */ 429 csr = PCICTL_READ8(sc, PCR_CS); 430 csr |= PCICTL_MRLM | PCICTL_ARB_PARK | PCICTL_ERRINTEN | PCICTL_4ENABLE; 431 csr &= ~(PCICTL_SERR | PCICTL_CPU_PRIO | PCICTL_ARB_PRIO | 432 PCICTL_RTRYWAIT); 433 PCICTL_WRITE8(sc, PCR_CS, csr); 434 435 /* Grab the psycho ranges */ 436 psycho_get_ranges(sc->sc_node, &sc->sc_range, &sc->sc_nrange); 437 438 /* Initialize memory and i/o rmans */ 439 sc->sc_io_rman.rm_type = RMAN_ARRAY; 440 sc->sc_io_rman.rm_descr = "Psycho PCI I/O Ports"; 441 if (rman_init(&sc->sc_io_rman) != 0 || 442 rman_manage_region(&sc->sc_io_rman, 0, PSYCHO_IO_SIZE) != 0) 443 panic("psycho_probe: failed to set up i/o rman"); 444 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 445 sc->sc_mem_rman.rm_descr = "Psycho PCI Memory"; 446 if (rman_init(&sc->sc_mem_rman) != 0 || 447 rman_manage_region(&sc->sc_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 448 panic("psycho_probe: failed to set up memory rman"); 449 /* 450 * Find the addresses of the various bus spaces. 451 * There should not be multiple ones of one kind. 452 * The physical start addresses of the ranges are the configuration, 453 * memory and IO handles. 454 */ 455 for (n = 0; n < sc->sc_nrange; n++) { 456 i = UPA_RANGE_CS(&sc->sc_range[n]); 457 if (sc->sc_bh[i] != 0) 458 panic("psycho_attach: duplicate range for space %d", i); 459 sc->sc_bh[i] = UPA_RANGE_PHYS(&sc->sc_range[n]); 460 } 461 /* 462 * Check that all needed handles are present. The PCI_CS_MEM64 one is 463 * not currently used. 464 */ 465 for (n = 0; n < 3; n++) { 466 if (sc->sc_bh[n] == 0) 467 panic("psycho_attach: range %d missing", n); 468 } 469 470 /* allocate our tags */ 471 sc->sc_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 472 sc->sc_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 473 sc->sc_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 474 if (bus_dma_tag_create(sc->sc_dmatag, 8, 1, 0, 0x3ffffffff, NULL, NULL, 475 0x3ffffffff, 0xff, 0xffffffff, 0, &sc->sc_dmat) != 0) 476 panic("psycho_attach: bus_dma_tag_create failed"); 477 /* Customize the tag */ 478 sc->sc_dmat->cookie = sc; 479 sc->sc_dmat->dmamap_create = psycho_dmamap_create; 480 sc->sc_dmat->dmamap_destroy = psycho_dmamap_destroy; 481 sc->sc_dmat->dmamap_load = psycho_dmamap_load; 482 sc->sc_dmat->dmamap_unload = psycho_dmamap_unload; 483 sc->sc_dmat->dmamap_sync = psycho_dmamap_sync; 484 sc->sc_dmat->dmamem_alloc = psycho_dmamem_alloc; 485 sc->sc_dmat->dmamem_free = psycho_dmamem_free; 486 /* XXX: register as root dma tag (kluge). */ 487 sparc64_root_dma_tag = sc->sc_dmat; 488 489 /* Register the softc, this is needed for paired psychos. */ 490 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 491 492 /* 493 * And finally, if we're a sabre or the first of a pair of psycho's to 494 * arrive here, start up the IOMMU and get a config space tag. 495 */ 496 if (osc == NULL) { 497 /* 498 * Establish handlers for interesting interrupts.... 499 * 500 * XXX We need to remember these and remove this to support 501 * hotplug on the UPA/FHC bus. 502 * 503 * XXX Not all controllers have these, but installing them 504 * is better than trying to sort through this mess. 505 */ 506 psycho_set_intr(sc, 0, dev, PSR_UE_INT_MAP, INTR_FAST, 507 psycho_ue); 508 psycho_set_intr(sc, 1, dev, PSR_CE_INT_MAP, 0, psycho_ce); 509 psycho_set_intr(sc, 2, dev, PSR_PCIAERR_INT_MAP, INTR_FAST, 510 psycho_bus_a); 511 psycho_set_intr(sc, 4, dev, PSR_POWER_INT_MAP, 512 PSYCHO_PWRFAIL_INT_FLAGS, psycho_powerfail); 513 /* Psycho-specific initialization. */ 514 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 515 /* 516 * Sabres do not have the following two interrupts. 517 */ 518 psycho_set_intr(sc, 3, dev, PSR_PCIBERR_INT_MAP, 519 INTR_FAST, psycho_bus_b); 520#ifdef PSYCHO_MAP_WAKEUP 521 /* 522 * psycho_wakeup() doesn't do anything useful right 523 * now. 524 */ 525 psycho_set_intr(sc, 5, dev, PSR_PWRMGT_INT_MAP, 0, 526 psycho_wakeup); 527#endif /* PSYCHO_MAP_WAKEUP */ 528 529 /* Initialize the counter-timer. */ 530 sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, 531 PSR_TC0); 532 } 533 534 /* 535 * Setup IOMMU and PCI configuration if we're the first 536 * of a pair of psycho's to arrive here. 537 * 538 * We should calculate a TSB size based on amount of RAM 539 * and number of bus controllers and number an type of 540 * child devices. 541 * 542 * For the moment, 32KB should be more than enough. 543 */ 544 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 545 M_NOWAIT); 546 if (sc->sc_is == NULL) 547 panic("psycho_attach: malloc iommu_state failed"); 548 sc->sc_is->is_sb[0] = 0; 549 sc->sc_is->is_sb[1] = 0; 550 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 551 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 552 psycho_iommu_init(sc, 2); 553 } else { 554 /* Just copy IOMMU state, config tag and address */ 555 sc->sc_is = osc->sc_is; 556 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 557 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 558 iommu_reset(sc->sc_is); 559 } 560 561 /* 562 * Enable all interrupts, clear all interrupt states, and install an 563 * interrupt handler for OBIO interrupts, which can be ISA ones 564 * (to frob the interrupt clear registers). 565 * This aids the debugging of interrupt routing problems, and is needed 566 * for isa drivers that use isa_irq_pending (otherwise the registers 567 * will never be cleared). 568 */ 569#if defined(PSYCHO_DEBUG) || defined(PSYCHO_STRAY) 570 for (map = PSR_PCIA0_INT_MAP, clr = PSR_PCIA0_INT_CLR, n = 0; 571 map <= PSR_PCIB3_INT_MAP; map += 8, clr += 32, n++) { 572 mr = PSYCHO_READ8(sc, map); 573#ifdef PSYCHO_DEBUG 574 device_printf(dev, "intr map (pci) %d: %#lx\n", n, (u_long)mr); 575#endif 576 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 577 for (i = 0; i < 4; i++) 578 PCICTL_WRITE8(sc, clr + i * 8, 0); 579 PSYCHO_WRITE8(sc, map, mr | INTMAP_V); 580 } 581 for (map = PSR_SCSI_INT_MAP, clr = PSR_SCSI_INT_CLR, n = 0; 582 map < PSR_FFB0_INT_MAP; map += 8, clr += 8, n++) { 583 mr = PSYCHO_READ8(sc, map); 584#ifdef PSYCHO_DEBUG 585 device_printf(dev, "intr map (obio) %d: %#lx, clr: %#lx\n", n, 586 (u_long)mr, (u_long)clr); 587#endif 588 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 589 PSYCHO_WRITE8(sc, clr, 0); 590#ifdef PSYCHO_STRAY 591 /* 592 * This can cause interrupt storms, and is therefore disabled 593 * by default. 594 * XXX: use intr_setup() to not confuse higher level code 595 */ 596 if (INTVEC(mr) != 0x7e6 && INTVEC(mr) != 0x7e7 && 597 INTVEC(mr) != 0) { 598 sclr = malloc(sizeof(*sclr), M_DEVBUF, M_WAITOK); 599 sclr->psc_sc = sc; 600 sclr->psc_clr = clr; 601 intr_setup(PIL_LOW, intr_fast, INTVEC(mr), 602 psycho_intr_stray, sclr); 603 } 604#endif 605 PSYCHO_WRITE8(sc, map, mr | INTMAP_V); 606 } 607#endif 608 609 /* 610 * Get the bus range from the firmware; it is used solely for obtaining 611 * the inital bus number, and cannot be trusted on all machines. 612 */ 613 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br)); 614 if (n == -1) 615 panic("could not get psycho bus-range"); 616 if (n != sizeof(psycho_br)) 617 panic("broken psycho bus-range (%d)", n); 618 619 sc->sc_busno = ofw_pci_alloc_busno(sc->sc_node); 620 obd.obd_bus = psycho_br[0]; 621 obd.obd_secbus = obd.obd_subbus = sc->sc_busno; 622 obd.obd_slot = PCS_DEVICE; 623 obd.obd_func = PCS_FUNC; 624 obd.obd_init = psycho_binit; 625 obd.obd_super = NULL; 626 /* Initial setup. */ 627 psycho_binit(dev, &obd); 628 /* Update the bus number to what was just programmed. */ 629 obd.obd_bus = obd.obd_secbus; 630 /* 631 * Initialize the interrupt registers of all devices hanging from 632 * the host bridge directly or indirectly via PCI-PCI bridges. 633 * The MI code (and the PCI spec) assume that this is done during 634 * system initialization, however the firmware does not do this 635 * at least on some models, and we probably shouldn't trust that 636 * the firmware uses the same model as this driver if it does. 637 * Additionally, set up the bus numbers and ranges. 638 */ 639 ofw_pci_init(dev, sc->sc_node, sc->sc_ign, &obd); 640 641 device_add_child(dev, "pci", device_get_unit(dev)); 642 return (bus_generic_attach(dev)); 643} 644 645static void 646psycho_set_intr(struct psycho_softc *sc, int index, 647 device_t dev, bus_addr_t map, int iflags, driver_intr_t handler) 648{ 649 int rid, vec; 650 u_int64_t mr; 651 652 mr = PSYCHO_READ8(sc, map); 653 vec = INTVEC(mr); 654 sc->sc_irq_res[index] = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 655 vec, vec, 1, RF_ACTIVE); 656 if (sc->sc_irq_res[index] == NULL) 657 panic("psycho_set_intr: failed to get interrupt"); 658 bus_setup_intr(dev, sc->sc_irq_res[index], INTR_TYPE_MISC | iflags, 659 handler, sc, &sc->sc_ihand[index]); 660 PSYCHO_WRITE8(sc, map, mr | INTMAP_V); 661} 662 663static int 664psycho_find_intrmap(struct psycho_softc *sc, int ino, bus_addr_t *intrmapptr, 665 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 666{ 667 bus_addr_t intrmap, intrclr; 668 u_int64_t im; 669 u_long diag; 670 int found; 671 672 found = 0; 673 /* Hunt thru obio first */ 674 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 675 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 676 intrmap < PSR_FFB0_INT_MAP; intrmap += 8, intrclr += 8, 677 diag >>= 2) { 678 im = PSYCHO_READ8(sc, intrmap); 679 if (INTINO(im) == ino) { 680 diag &= 2; 681 found = 1; 682 break; 683 } 684 } 685 686 if (!found) { 687 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 688 /* Now do PCI interrupts */ 689 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 690 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 691 diag >>= 8) { 692 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 693 (intrmap == PSR_PCIA2_INT_MAP || 694 intrmap == PSR_PCIA3_INT_MAP)) 695 continue; 696 im = PSYCHO_READ8(sc, intrmap); 697 if (((im ^ ino) & 0x3c) == 0) { 698 intrclr += 8 * (ino & 3); 699 diag = (diag >> ((ino & 3) * 2)) & 2; 700 found = 1; 701 break; 702 } 703 } 704 } 705 if (intrmapptr != NULL) 706 *intrmapptr = intrmap; 707 if (intrclrptr != NULL) 708 *intrclrptr = intrclr; 709 if (intrdiagptr != NULL) 710 *intrdiagptr = diag; 711 return (found); 712} 713 714/* grovel the OBP for various psycho properties */ 715static void 716psycho_get_ranges(phandle_t node, struct upa_ranges **rp, int *np) 717{ 718 719 *np = OF_getprop_alloc(node, "ranges", sizeof(**rp), (void **)rp); 720 if (*np == -1) 721 panic("could not get psycho ranges"); 722} 723 724/* 725 * Interrupt handlers. 726 */ 727static void 728psycho_ue(void *arg) 729{ 730 struct psycho_softc *sc = (struct psycho_softc *)arg; 731 u_int64_t afar, afsr; 732 733 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 734 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 735 /* 736 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 737 * the AFAR to be set to the physical address of the TTE entry that 738 * was invalid/write protected. Call into the iommu code to have 739 * them decoded to virtual IO addresses. 740 */ 741 if ((afsr & UEAFSR_P_DTE) != 0) 742 iommu_decode_fault(sc->sc_is, afar); 743 /* It's uncorrectable. Dump the regs and panic. */ 744 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx\n", 745 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 746} 747 748static void 749psycho_ce(void *arg) 750{ 751 struct psycho_softc *sc = (struct psycho_softc *)arg; 752 u_int64_t afar, afsr; 753 754 PSYCHO_WRITE8(sc, PSR_CE_INT_CLR, 0); 755 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 756 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 757 /* It's correctable. Dump the regs and continue. */ 758 printf("%s: correctable DMA error AFAR %#lx AFSR %#lx\n", 759 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 760} 761 762static void 763psycho_bus_a(void *arg) 764{ 765 struct psycho_softc *sc = (struct psycho_softc *)arg; 766 u_int64_t afar, afsr; 767 768 afar = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFA); 769 afsr = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFS); 770 /* It's uncorrectable. Dump the regs and panic. */ 771 panic("%s: PCI bus A error AFAR %#lx AFSR %#lx\n", 772 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 773} 774 775static void 776psycho_bus_b(void *arg) 777{ 778 struct psycho_softc *sc = (struct psycho_softc *)arg; 779 u_int64_t afar, afsr; 780 781 afar = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFA); 782 afsr = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFS); 783 /* It's uncorrectable. Dump the regs and panic. */ 784 panic("%s: PCI bus B error AFAR %#lx AFSR %#lx\n", 785 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 786} 787 788static void 789psycho_powerfail(void *arg) 790{ 791 792 /* We lost power. Try to shut down NOW. */ 793#ifdef DEBUGGER_ON_POWERFAIL 794 struct psycho_softc *sc = (struct psycho_softc *)arg; 795 796 Debugger("powerfail"); 797 PSYCHO_WRITE8(sc, PSR_POWER_INT_CLR, 0); 798#else 799 printf("Power Failure Detected: Shutting down NOW.\n"); 800 shutdown_nice(0); 801#endif 802} 803 804#ifdef PSYCHO_MAP_WAKEUP 805static void 806psycho_wakeup(void *arg) 807{ 808 struct psycho_softc *sc = (struct psycho_softc *)arg; 809 810 PSYCHO_WRITE8(sc, PSR_PWRMGT_INT_CLR, 0); 811 /* Gee, we don't really have a framework to deal with this properly. */ 812 printf("%s: power management wakeup\n", device_get_name(sc->sc_dev)); 813} 814#endif /* PSYCHO_MAP_WAKEUP */ 815 816/* initialise the IOMMU... */ 817void 818psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 819{ 820 char *name; 821 struct iommu_state *is = sc->sc_is; 822 u_int32_t iobase = -1; 823 int *vdma = NULL; 824 int nitem; 825 826 /* punch in our copies */ 827 is->is_bustag = sc->sc_bustag; 828 is->is_bushandle = sc->sc_bushandle; 829 is->is_iommu = PSR_IOMMU; 830 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 831 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 832 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 833 is->is_dva = PSR_IOMMU_SVADIAG; 834 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 835 836 /* 837 * Separate the men from the boys. Get the `virtual-dma' 838 * property for sabre and use that to make sure the damn 839 * iommu works. 840 * 841 * We could query the `#virtual-dma-size-cells' and 842 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 843 */ 844 nitem = OF_getprop_alloc(sc->sc_node, "virtual-dma", sizeof(vdma), 845 (void **)&vdma); 846 if (nitem > 0) { 847 iobase = vdma[0]; 848 tsbsize = ffs(vdma[1]); 849 if (tsbsize < 25 || tsbsize > 31 || 850 (vdma[1] & ~(1 << (tsbsize - 1))) != 0) { 851 printf("bogus tsb size %x, using 7\n", vdma[1]); 852 tsbsize = 31; 853 } 854 tsbsize -= 24; 855 free(vdma, M_OFWPROP); 856 } 857 858 /* give us a nice name.. */ 859 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 860 if (name == 0) 861 panic("couldn't malloc iommu name"); 862 snprintf(name, 32, "%s dvma", device_get_name(sc->sc_dev)); 863 864 iommu_init(name, is, tsbsize, iobase, 0); 865} 866 867static void 868psycho_binit(device_t busdev, struct ofw_pci_bdesc *obd) 869{ 870 871#ifdef PSYCHO_DEBUG 872 printf("psycho at %u/%u/%u: setting bus #s to %u/%u/%u\n", 873 obd->obd_bus, obd->obd_slot, obd->obd_func, obd->obd_bus, 874 obd->obd_secbus, obd->obd_subbus); 875#endif /* PSYCHO_DEBUG */ 876 /* 877 * NOTE: this must be kept in this order, since the last write will 878 * change the config space address of the psycho. 879 */ 880 PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func, 881 PCSR_SUBBUS, obd->obd_subbus, 1); 882 PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func, 883 PCSR_SECBUS, obd->obd_secbus, 1); 884} 885 886static int 887psycho_maxslots(device_t dev) 888{ 889 890 /* 891 * XXX: is this correct? At any rate, a number that is too high 892 * shouldn't do any harm, if only because of the way things are 893 * handled in psycho_read_config. 894 */ 895 return (31); 896} 897 898/* 899 * Keep a table of quirky PCI devices that need fixups before the MI PCI code 900 * creates the resource lists. This needs to be moved around once other bus 901 * drivers are added. Moving it to the MI code should maybe be reconsidered 902 * if one of these devices appear in non-sparc64 boxen. It's likely that not 903 * all BIOSes/firmwares can deal with them. 904 */ 905struct psycho_dquirk { 906 u_int32_t dq_devid; 907 int dq_quirk; 908}; 909 910/* Quirk types. May be or'ed together. */ 911#define DQT_BAD_INTPIN 1 /* Intpin reg 0, but intpin used */ 912 913static struct psycho_dquirk dquirks[] = { 914 { 0x1001108e, DQT_BAD_INTPIN }, /* Sun HME (PCIO func. 1) */ 915 { 0x1101108e, DQT_BAD_INTPIN }, /* Sun GEM (PCIO2 func. 1) */ 916 { 0x1102108e, DQT_BAD_INTPIN }, /* Sun FireWire ctl. (PCIO2 func. 2) */ 917 { 0x1103108e, DQT_BAD_INTPIN }, /* Sun USB ctl. (PCIO2 func. 3) */ 918}; 919 920#define NDQUIRKS (sizeof(dquirks) / sizeof(dquirks[0])) 921 922static u_int32_t 923psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 924 int width) 925{ 926 struct psycho_softc *sc; 927 bus_space_handle_t bh; 928 u_long offset = 0; 929 u_int32_t r, devid; 930 int i; 931 932 /* 933 * The psycho bridge does not tolerate accesses to unconfigured PCI 934 * devices' or function's config space, so look up the device in the 935 * firmware device tree first, and if it is not present, return a value 936 * that will make the detection code think that there is no device here. 937 * This is ugly... 938 */ 939 if (reg == 0 && ofw_pci_find_node(bus, slot, func) == 0) 940 return (0xffffffff); 941 sc = (struct psycho_softc *)device_get_softc(dev); 942 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 943 bh = sc->sc_bh[PCI_CS_CONFIG]; 944 switch (width) { 945 case 1: 946 r = bus_space_read_1(sc->sc_cfgt, bh, offset); 947 break; 948 case 2: 949 r = bus_space_read_2(sc->sc_cfgt, bh, offset); 950 break; 951 case 4: 952 r = bus_space_read_4(sc->sc_cfgt, bh, offset); 953 break; 954 default: 955 panic("psycho_read_config: bad width"); 956 } 957 if (reg == PCIR_INTPIN && r == 0) { 958 /* Check for DQT_BAD_INTPIN quirk. */ 959 devid = psycho_read_config(dev, bus, slot, func, 960 PCIR_DEVVENDOR, 4); 961 for (i = 0; i < NDQUIRKS; i++) { 962 if (dquirks[i].dq_devid == devid) { 963 /* 964 * Need to set the intpin to a value != 0 so 965 * that the MI code will think that this device 966 * has an interrupt. 967 * Just use 1 (intpin a) for now. This is, of 968 * course, bogus, but since interrupts are 969 * routed in advance, this does not really 970 * matter. 971 */ 972 if ((dquirks[i].dq_quirk & DQT_BAD_INTPIN) != 0) 973 r = 1; 974 break; 975 } 976 } 977 } 978 return (r); 979} 980 981static void 982psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, 983 u_int reg, u_int32_t val, int width) 984{ 985 struct psycho_softc *sc; 986 bus_space_handle_t bh; 987 u_long offset = 0; 988 989 sc = (struct psycho_softc *)device_get_softc(dev); 990 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 991 bh = sc->sc_bh[PCI_CS_CONFIG]; 992 switch (width) { 993 case 1: 994 bus_space_write_1(sc->sc_cfgt, bh, offset, val); 995 break; 996 case 2: 997 bus_space_write_2(sc->sc_cfgt, bh, offset, val); 998 break; 999 case 4: 1000 bus_space_write_4(sc->sc_cfgt, bh, offset, val); 1001 break; 1002 default: 1003 panic("psycho_write_config: bad width"); 1004 } 1005} 1006 1007static int 1008psycho_route_interrupt(device_t bus, device_t dev, int pin) 1009{ 1010 1011 /* 1012 * XXX: ugly loathsome hack: 1013 * We can't use ofw_pci_route_intr() here; the device passed may be 1014 * the one of a bridge, so the original device can't be recovered. 1015 * 1016 * We need to use the firmware to route interrupts, however it has 1017 * no interface which could be used to interpret intpins; instead, 1018 * all assignments are done by device. 1019 * 1020 * The MI pci code will try to reroute interrupts of 0, although they 1021 * are correct; all other interrupts are preinitialized, so if we 1022 * get here, the intline is either 0 (so return 0), or we hit a 1023 * device which was not preinitialized (e.g. hotplugged stuff), in 1024 * which case we are lost. 1025 */ 1026 return (0); 1027} 1028 1029static int 1030psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1031{ 1032 struct psycho_softc *sc; 1033 1034 sc = (struct psycho_softc *)device_get_softc(dev); 1035 switch (which) { 1036 case PCIB_IVAR_BUS: 1037 *result = sc->sc_busno; 1038 return (0); 1039 } 1040 return (ENOENT); 1041} 1042 1043/* Write to the correct clr register, and call the actual handler. */ 1044static void 1045psycho_intr_stub(void *arg) 1046{ 1047 struct psycho_clr *pc; 1048 1049 pc = (struct psycho_clr *)arg; 1050 pc->pci_handler(pc->pci_arg); 1051 PSYCHO_WRITE8(pc->pci_sc, pc->pci_clr, 0); 1052} 1053 1054#ifdef PSYCHO_STRAY 1055/* 1056 * Write to the correct clr register and return. arg is the address of the clear 1057 * register to be used. 1058 * XXX: print a message? 1059 */ 1060static void 1061psycho_intr_stray(void *arg) 1062{ 1063 struct psycho_strayclr *sclr = arg; 1064 1065 PSYCHO_WRITE8(sclr->psc_sc, sclr->psc_clr, 0); 1066} 1067#endif 1068 1069static int 1070psycho_setup_intr(device_t dev, device_t child, 1071 struct resource *ires, int flags, driver_intr_t *intr, void *arg, 1072 void **cookiep) 1073{ 1074 struct psycho_softc *sc; 1075 struct psycho_clr *pc; 1076 bus_addr_t intrmapptr, intrclrptr; 1077 long vec = rman_get_start(ires); 1078 u_int64_t mr; 1079 int ino, error; 1080 1081 sc = (struct psycho_softc *)device_get_softc(dev); 1082 pc = (struct psycho_clr *)malloc(sizeof(*pc), M_DEVBUF, M_NOWAIT); 1083 if (pc == NULL) 1084 return (NULL); 1085 1086 /* 1087 * Hunt through all the interrupt mapping regs to look for our 1088 * interrupt vector. 1089 * 1090 * XXX We only compare INOs rather than IGNs since the firmware may 1091 * not provide the IGN and the IGN is constant for all device on that 1092 * PCI controller. This could cause problems for the FFB/external 1093 * interrupt which has a full vector that can be set arbitrarily. 1094 */ 1095 ino = INTINO(vec); 1096 1097 if (!psycho_find_intrmap(sc, ino, &intrmapptr, &intrclrptr, NULL)) { 1098 printf("Cannot find interrupt vector %lx\n", vec); 1099 free(pc, M_DEVBUF); 1100 return (NULL); 1101 } 1102 1103#ifdef PSYCHO_DEBUG 1104 device_printf(dev, "psycho_setup_intr: INO %d, map %#lx, clr %#lx\n", 1105 ino, (u_long)intrmapptr, (u_long)intrclrptr); 1106#endif 1107 pc->pci_sc = sc; 1108 pc->pci_arg = arg; 1109 pc->pci_handler = intr; 1110 pc->pci_clr = intrclrptr; 1111 /* Disable the interrupt while we fiddle with it */ 1112 mr = PSYCHO_READ8(sc, intrmapptr); 1113 PSYCHO_WRITE8(sc, intrmapptr, mr & ~INTMAP_V); 1114 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 1115 psycho_intr_stub, pc, cookiep); 1116 if (error != 0) { 1117 free(pc, M_DEVBUF); 1118 return (error); 1119 } 1120 pc->pci_cookie = *cookiep; 1121 *cookiep = pc; 1122 1123 /* 1124 * Clear the interrupt, it might have been triggered before it was 1125 * set up. 1126 */ 1127 PSYCHO_WRITE8(sc, intrclrptr, 0); 1128 /* 1129 * Enable the interrupt now we have the handler installed. 1130 * Read the current value as we can't change it besides the 1131 * valid bit so so make sure only this bit is changed. 1132 */ 1133 PSYCHO_WRITE8(sc, intrmapptr, mr | INTMAP_V); 1134 return (error); 1135} 1136 1137static int 1138psycho_teardown_intr(device_t dev, device_t child, 1139 struct resource *vec, void *cookie) 1140{ 1141 struct psycho_clr *pc; 1142 int error; 1143 1144 pc = (struct psycho_clr *)cookie; 1145 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 1146 pc->pci_cookie); 1147 /* 1148 * Don't disable the interrupt for now, so that stray interupts get 1149 * detected... 1150 */ 1151 if (error != 0) 1152 free(pc, M_DEVBUF); 1153 return (error); 1154} 1155 1156static struct resource * 1157psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1158 u_long start, u_long end, u_long count, u_int flags) 1159{ 1160 struct psycho_softc *sc; 1161 struct resource *rv; 1162 struct rman *rm; 1163 bus_space_tag_t bt; 1164 bus_space_handle_t bh; 1165 int needactivate = flags & RF_ACTIVE; 1166 1167 flags &= ~RF_ACTIVE; 1168 1169 sc = (struct psycho_softc *)device_get_softc(bus); 1170 if (type == SYS_RES_IRQ) { 1171 /* 1172 * XXX: Don't accept blank ranges for now, only single 1173 * interrupts. The other case should not happen with the MI pci 1174 * code... 1175 * XXX: This may return a resource that is out of the range 1176 * that was specified. Is this correct...? 1177 */ 1178 if (start != end) 1179 panic("psycho_alloc_resource: XXX: interrupt range"); 1180 start = end |= sc->sc_ign; 1181 return (bus_alloc_resource(bus, type, rid, start, end, 1182 count, flags)); 1183 } 1184 switch (type) { 1185 case SYS_RES_MEMORY: 1186 rm = &sc->sc_mem_rman; 1187 bt = sc->sc_memt; 1188 bh = sc->sc_bh[PCI_CS_MEM32]; 1189 break; 1190 case SYS_RES_IOPORT: 1191 rm = &sc->sc_io_rman; 1192 bt = sc->sc_iot; 1193 /* XXX: probably should use ranges property here. */ 1194 bh = sc->sc_bh[PCI_CS_IO]; 1195 break; 1196 default: 1197 return (NULL); 1198 } 1199 1200 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1201 if (rv == NULL) 1202 return (NULL); 1203 1204 bh += rman_get_start(rv); 1205 rman_set_bustag(rv, bt); 1206 rman_set_bushandle(rv, bh); 1207 1208 if (needactivate) { 1209 if (bus_activate_resource(child, type, *rid, rv)) { 1210 rman_release_resource(rv); 1211 return (NULL); 1212 } 1213 } 1214 1215 return (rv); 1216} 1217 1218static int 1219psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1220 struct resource *r) 1221{ 1222 void *p; 1223 int error; 1224 1225 if (type == SYS_RES_IRQ) 1226 return (bus_activate_resource(bus, type, rid, r)); 1227 if (type == SYS_RES_MEMORY) { 1228 /* 1229 * Need to memory-map the device space, as some drivers depend 1230 * on the virtual address being set and useable. 1231 */ 1232 error = sparc64_bus_mem_map(rman_get_bustag(r), 1233 rman_get_bushandle(r), rman_get_size(r), 0, NULL, &p); 1234 if (error != 0) 1235 return (error); 1236 rman_set_virtual(r, p); 1237 } 1238 return (rman_activate_resource(r)); 1239} 1240 1241static int 1242psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1243 struct resource *r) 1244{ 1245 1246 if (type == SYS_RES_IRQ) 1247 return (bus_deactivate_resource(bus, type, rid, r)); 1248 if (type == SYS_RES_MEMORY) { 1249 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1250 rman_set_virtual(r, NULL); 1251 } 1252 return (rman_deactivate_resource(r)); 1253} 1254 1255static int 1256psycho_release_resource(device_t bus, device_t child, int type, int rid, 1257 struct resource *r) 1258{ 1259 int error; 1260 1261 if (type == SYS_RES_IRQ) 1262 return (bus_release_resource(bus, type, rid, r)); 1263 if (rman_get_flags(r) & RF_ACTIVE) { 1264 error = bus_deactivate_resource(child, type, rid, r); 1265 if (error) 1266 return error; 1267 } 1268 return (rman_release_resource(r)); 1269} 1270 1271static int 1272psycho_intr_pending(device_t dev, int intr) 1273{ 1274 struct psycho_softc *sc; 1275 u_long diag; 1276 1277 sc = (struct psycho_softc *)device_get_softc(dev); 1278 if (!psycho_find_intrmap(sc, intr, NULL, NULL, &diag)) { 1279 printf("psycho_intr_pending: mapping not found for %d\n", intr); 1280 return (0); 1281 } 1282 return (diag != 0); 1283} 1284 1285static bus_space_handle_t 1286psycho_get_bus_handle(device_t dev, enum sbbt_id id, 1287 bus_space_handle_t childhdl, bus_space_tag_t *tag) 1288{ 1289 struct psycho_softc *sc; 1290 1291 sc = (struct psycho_softc *)device_get_softc(dev); 1292 switch(id) { 1293 case SBBT_IO: 1294 *tag = sc->sc_iot; 1295 return (sc->sc_bh[PCI_CS_IO] + childhdl); 1296 case SBBT_MEM: 1297 *tag = sc->sc_memt; 1298 return (sc->sc_bh[PCI_CS_MEM32] + childhdl); 1299 default: 1300 panic("psycho_get_bus_handle: illegal space\n"); 1301 } 1302} 1303 1304/* 1305 * below here is bus space and bus dma support 1306 */ 1307static bus_space_tag_t 1308psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1309{ 1310 bus_space_tag_t bt; 1311 1312 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1313 M_NOWAIT | M_ZERO); 1314 if (bt == NULL) 1315 panic("psycho_alloc_bus_tag: out of memory"); 1316 1317 bzero(bt, sizeof *bt); 1318 bt->cookie = sc; 1319 bt->parent = sc->sc_bustag; 1320 bt->type = type; 1321 return (bt); 1322} 1323 1324/* 1325 * hooks into the iommu dvma calls. 1326 */ 1327static int 1328psycho_dmamem_alloc(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void **vaddr, 1329 int flags, bus_dmamap_t *mapp) 1330{ 1331 struct psycho_softc *sc; 1332 1333 sc = (struct psycho_softc *)pdmat->cookie; 1334 return (iommu_dvmamem_alloc(pdmat, ddmat, sc->sc_is, vaddr, flags, 1335 mapp)); 1336} 1337 1338static void 1339psycho_dmamem_free(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void *vaddr, 1340 bus_dmamap_t map) 1341{ 1342 struct psycho_softc *sc; 1343 1344 sc = (struct psycho_softc *)pdmat->cookie; 1345 iommu_dvmamem_free(pdmat, ddmat, sc->sc_is, vaddr, map); 1346} 1347 1348static int 1349psycho_dmamap_create(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, int flags, 1350 bus_dmamap_t *mapp) 1351{ 1352 struct psycho_softc *sc; 1353 1354 sc = (struct psycho_softc *)pdmat->cookie; 1355 return (iommu_dvmamap_create(pdmat, ddmat, sc->sc_is, flags, mapp)); 1356 1357} 1358 1359static int 1360psycho_dmamap_destroy(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, 1361 bus_dmamap_t map) 1362{ 1363 struct psycho_softc *sc; 1364 1365 sc = (struct psycho_softc *)pdmat->cookie; 1366 return (iommu_dvmamap_destroy(pdmat, ddmat, sc->sc_is, map)); 1367} 1368 1369static int 1370psycho_dmamap_load(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map, 1371 void *buf, bus_size_t buflen, bus_dmamap_callback_t *callback, 1372 void *callback_arg, int flags) 1373{ 1374 struct psycho_softc *sc; 1375 1376 sc = (struct psycho_softc *)pdmat->cookie; 1377 return (iommu_dvmamap_load(pdmat, ddmat, sc->sc_is, map, buf, buflen, 1378 callback, callback_arg, flags)); 1379} 1380 1381static void 1382psycho_dmamap_unload(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map) 1383{ 1384 struct psycho_softc *sc; 1385 1386 sc = (struct psycho_softc *)pdmat->cookie; 1387 iommu_dvmamap_unload(pdmat, ddmat, sc->sc_is, map); 1388} 1389 1390static void 1391psycho_dmamap_sync(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map, 1392 bus_dmasync_op_t op) 1393{ 1394 struct psycho_softc *sc; 1395 1396 sc = (struct psycho_softc *)pdmat->cookie; 1397 iommu_dvmamap_sync(pdmat, ddmat, sc->sc_is, map, op); 1398} 1399