psycho.c revision 106555
1/* 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * All rights reserved. 4 * Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 30 * 31 * $FreeBSD: head/sys/sparc64/pci/psycho.c 106555 2002-11-07 16:07:46Z tmm $ 32 */ 33 34/* 35 * Support for `psycho' and `psycho+' UPA to PCI bridge and 36 * UltraSPARC IIi and IIe `sabre' PCI controllers. 37 */ 38 39#include "opt_psycho.h" 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/kernel.h> 45#include <sys/malloc.h> 46 47#include <ofw/openfirm.h> 48#include <ofw/ofw_pci.h> 49 50#include <machine/bus.h> 51#include <machine/iommureg.h> 52#include <machine/bus_common.h> 53#include <machine/frame.h> 54#include <machine/intr_machdep.h> 55#include <machine/nexusvar.h> 56#include <machine/ofw_upa.h> 57#include <machine/resource.h> 58 59#include <sys/rman.h> 60 61#include <machine/iommuvar.h> 62 63#include <pci/pcivar.h> 64#include <pci/pcireg.h> 65 66#include <sparc64/pci/ofw_pci.h> 67#include <sparc64/pci/psychoreg.h> 68#include <sparc64/pci/psychovar.h> 69 70#include "pcib_if.h" 71#include "sparcbus_if.h" 72 73static void psycho_get_ranges(phandle_t, struct upa_ranges **, int *); 74static void psycho_set_intr(struct psycho_softc *, int, device_t, bus_addr_t, 75 int, driver_intr_t); 76static int psycho_find_intrmap(struct psycho_softc *, int, bus_addr_t *, 77 bus_addr_t *, u_long *); 78static void psycho_intr_stub(void *); 79#ifdef PSYCHO_STRAY 80static void psycho_intr_stray(void *); 81#endif 82static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 83 84 85/* Interrupt handlers */ 86static void psycho_ue(void *); 87static void psycho_ce(void *); 88static void psycho_bus_a(void *); 89static void psycho_bus_b(void *); 90static void psycho_powerfail(void *); 91#ifdef PSYCHO_MAP_WAKEUP 92static void psycho_wakeup(void *); 93#endif 94 95/* IOMMU support */ 96static void psycho_iommu_init(struct psycho_softc *, int); 97static ofw_pci_binit_t psycho_binit; 98 99/* 100 * bus space and bus dma support for UltraSPARC `psycho'. note that most 101 * of the bus dma support is provided by the iommu dvma controller. 102 */ 103static int psycho_dmamap_create(bus_dma_tag_t, bus_dma_tag_t, int, 104 bus_dmamap_t *); 105static int psycho_dmamap_destroy(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 106static int psycho_dmamap_load(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 107 void *, bus_size_t, bus_dmamap_callback_t *, void *, int); 108static void psycho_dmamap_unload(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 109static void psycho_dmamap_sync(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 110 bus_dmasync_op_t); 111static int psycho_dmamem_alloc(bus_dma_tag_t, bus_dma_tag_t, void **, int, 112 bus_dmamap_t *); 113static void psycho_dmamem_free(bus_dma_tag_t, bus_dma_tag_t, void *, 114 bus_dmamap_t); 115 116/* 117 * autoconfiguration 118 */ 119static int psycho_probe(device_t); 120static int psycho_attach(device_t); 121static int psycho_read_ivar(device_t, device_t, int, u_long *); 122static int psycho_setup_intr(device_t, device_t, struct resource *, int, 123 driver_intr_t *, void *, void **); 124static int psycho_teardown_intr(device_t, device_t, struct resource *, void *); 125static struct resource *psycho_alloc_resource(device_t, device_t, int, int *, 126 u_long, u_long, u_long, u_int); 127static int psycho_activate_resource(device_t, device_t, int, int, 128 struct resource *); 129static int psycho_deactivate_resource(device_t, device_t, int, int, 130 struct resource *); 131static int psycho_release_resource(device_t, device_t, int, int, 132 struct resource *); 133static int psycho_maxslots(device_t); 134static u_int32_t psycho_read_config(device_t, u_int, u_int, u_int, u_int, int); 135static void psycho_write_config(device_t, u_int, u_int, u_int, u_int, u_int32_t, 136 int); 137static int psycho_route_interrupt(device_t, device_t, int); 138static int psycho_intr_pending(device_t, int); 139static bus_space_handle_t psycho_get_bus_handle(device_t dev, enum sbbt_id id, 140 bus_space_handle_t childhdl, bus_space_tag_t *tag); 141 142static device_method_t psycho_methods[] = { 143 /* Device interface */ 144 DEVMETHOD(device_probe, psycho_probe), 145 DEVMETHOD(device_attach, psycho_attach), 146 147 /* Bus interface */ 148 DEVMETHOD(bus_print_child, bus_generic_print_child), 149 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 150 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 151 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 152 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 153 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 154 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 155 DEVMETHOD(bus_release_resource, psycho_release_resource), 156 157 /* pcib interface */ 158 DEVMETHOD(pcib_maxslots, psycho_maxslots), 159 DEVMETHOD(pcib_read_config, psycho_read_config), 160 DEVMETHOD(pcib_write_config, psycho_write_config), 161 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 162 163 /* sparcbus interface */ 164 DEVMETHOD(sparcbus_intr_pending, psycho_intr_pending), 165 DEVMETHOD(sparcbus_get_bus_handle, psycho_get_bus_handle), 166 167 { 0, 0 } 168}; 169 170static driver_t psycho_driver = { 171 "pcib", 172 psycho_methods, 173 sizeof(struct psycho_softc), 174}; 175 176static devclass_t psycho_devclass; 177 178DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 179 180SLIST_HEAD(, psycho_softc) psycho_softcs = 181 SLIST_HEAD_INITIALIZER(psycho_softcs); 182 183struct psycho_clr { 184 struct psycho_softc *pci_sc; 185 bus_addr_t pci_clr; /* clear register */ 186 driver_intr_t *pci_handler; /* handler to call */ 187 void *pci_arg; /* argument for the handler */ 188 void *pci_cookie; /* interrupt cookie of parent bus */ 189}; 190 191struct psycho_strayclr { 192 struct psycho_softc *psc_sc; 193 bus_addr_t psc_clr; /* clear register */ 194}; 195 196#define PSYCHO_READ8(sc, off) \ 197 bus_space_read_8((sc)->sc_bustag, (sc)->sc_bushandle, (off)) 198#define PSYCHO_WRITE8(sc, off, v) \ 199 bus_space_write_8((sc)->sc_bustag, (sc)->sc_bushandle, (off), (v)) 200#define PCICTL_READ8(sc, off) \ 201 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 202#define PCICTL_WRITE8(sc, off, v) \ 203 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 204 205/* 206 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 207 * single PCI bus and does not have a streaming buffer. It often has an APB 208 * (advanced PCI bridge) connected to it, which was designed specifically for 209 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 210 * appears as two "simba"'s underneath the sabre. 211 * 212 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 213 * and manages two PCI buses. "psycho" has two 64-bit 33MHz buses, while 214 * "psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 215 * will usually find a "psycho+" since I don't think the original "psycho" 216 * ever shipped, and if it did it would be in the U30. 217 * 218 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 219 * both part of the same IC, they only have a single register space. As such, 220 * they need to be configured together, even though the autoconfiguration will 221 * attach them separately. 222 * 223 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 224 * as pci1 and pci2, although they have been implemented with other PCI bus 225 * numbers on some machines. 226 * 227 * On UltraII machines, there can be any number of "psycho+" ICs, each 228 * providing two PCI buses. 229 * 230 * 231 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 232 * the values of the following interrupts in this order: 233 * 234 * PCI Bus Error (30) 235 * DMA UE (2e) 236 * DMA CE (2f) 237 * Power Fail (25) 238 * 239 * We really should attach handlers for each. 240 */ 241#define OFW_PCI_TYPE "pci" 242 243struct psycho_desc { 244 char *pd_string; 245 int pd_mode; 246 char *pd_name; 247}; 248 249static struct psycho_desc psycho_compats[] = { 250 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 251 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre (US-IIi) compatible" }, 252 { "pci108e,a001", PSYCHO_MODE_SABRE, "Sabre (US-IIe) compatible" }, 253 { NULL, 0, NULL } 254}; 255 256static struct psycho_desc psycho_models[] = { 257 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 258 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 259 { NULL, 0, NULL } 260}; 261 262static struct psycho_desc * 263psycho_find_desc(struct psycho_desc *table, char *string) 264{ 265 struct psycho_desc *desc; 266 267 for (desc = table; desc->pd_string != NULL; desc++) { 268 if (strcmp(desc->pd_string, string) == 0) 269 return (desc); 270 } 271 return (NULL); 272} 273 274static struct psycho_desc * 275psycho_get_desc(phandle_t node, char *model) 276{ 277 struct psycho_desc *rv; 278 char compat[32]; 279 280 rv = NULL; 281 if (model != NULL) 282 rv = psycho_find_desc(psycho_models, model); 283 if (rv == NULL && 284 OF_getprop(node, "compatible", compat, sizeof(compat)) != -1) 285 rv = psycho_find_desc(psycho_compats, compat); 286 return (rv); 287} 288 289static int 290psycho_probe(device_t dev) 291{ 292 phandle_t node; 293 char *dtype; 294 295 node = nexus_get_node(dev); 296 dtype = nexus_get_device_type(dev); 297 if (nexus_get_reg(dev) != NULL && dtype != NULL && 298 strcmp(dtype, OFW_PCI_TYPE) == 0 && 299 psycho_get_desc(node, nexus_get_model(dev)) != NULL) { 300 device_set_desc(dev, "U2P UPA-PCI bridge"); 301 return (0); 302 } 303 304 return (ENXIO); 305} 306 307/* 308 * SUNW,psycho initialisation .. 309 * - find the per-psycho registers 310 * - figure out the IGN. 311 * - find our partner psycho 312 * - configure ourselves 313 * - bus range, bus, 314 * - interrupt map, 315 * - setup the chipsets. 316 * - if we're the first of the pair, initialise the IOMMU, otherwise 317 * just copy it's tags and addresses. 318 */ 319static int 320psycho_attach(device_t dev) 321{ 322 struct psycho_softc *sc; 323 struct psycho_softc *osc = NULL; 324 struct psycho_softc *asc; 325 struct upa_regs *reg; 326 struct ofw_pci_bdesc obd; 327 struct psycho_desc *desc; 328 phandle_t node; 329 u_int64_t csr; 330 u_long pcictl_offs, mlen; 331 int psycho_br[2]; 332 int n, i, nreg, rid; 333#if defined(PSYCHO_DEBUG) || defined(PSYCHO_STRAY) 334 bus_addr_t map, clr; 335 u_int64_t mr; 336#endif 337#ifdef PSYCHO_STRAY 338 struct psycho_strayclr *sclr; 339#endif 340 341 node = nexus_get_node(dev); 342 sc = device_get_softc(dev); 343 desc = psycho_get_desc(node, nexus_get_model(dev)); 344 345 sc->sc_node = node; 346 sc->sc_dev = dev; 347 sc->sc_dmatag = nexus_get_dmatag(dev); 348 sc->sc_mode = desc->pd_mode; 349 350 /* 351 * The psycho gets three register banks: 352 * (0) per-PBM configuration and status registers 353 * (1) per-PBM PCI configuration space, containing only the 354 * PBM 256-byte PCI header 355 * (2) the shared psycho configuration registers (struct psychoreg) 356 * 357 * XXX use the prom address for the psycho registers? we do so far. 358 */ 359 reg = nexus_get_reg(dev); 360 nreg = nexus_get_nreg(dev); 361 /* Register layouts are different. stuupid. */ 362 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 363 if (nreg <= 2) 364 panic("psycho_attach: %d not enough registers", nreg); 365 sc->sc_basepaddr = (vm_offset_t)UPA_REG_PHYS(®[2]); 366 mlen = UPA_REG_SIZE(®[2]); 367 pcictl_offs = UPA_REG_PHYS(®[0]); 368 } else { 369 if (nreg <= 0) 370 panic("psycho_attach: %d not enough registers", nreg); 371 sc->sc_basepaddr = (vm_offset_t)UPA_REG_PHYS(®[0]); 372 mlen = UPA_REG_SIZE(reg); 373 pcictl_offs = sc->sc_basepaddr + PSR_PCICTL0; 374 } 375 376 /* 377 * Match other psycho's that are already configured against 378 * the base physical address. This will be the same for a 379 * pair of devices that share register space. 380 */ 381 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 382 if (asc->sc_basepaddr == sc->sc_basepaddr) { 383 /* Found partner */ 384 osc = asc; 385 break; 386 } 387 } 388 389 if (osc == NULL) { 390 rid = 0; 391 sc->sc_mem_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 392 sc->sc_basepaddr, sc->sc_basepaddr + mlen - 1, mlen, 393 RF_ACTIVE); 394 if (sc->sc_mem_res == NULL || 395 rman_get_start(sc->sc_mem_res) != sc->sc_basepaddr) 396 panic("psycho_attach: can't allocate device memory"); 397 sc->sc_bustag = rman_get_bustag(sc->sc_mem_res); 398 sc->sc_bushandle = rman_get_bushandle(sc->sc_mem_res); 399 } else { 400 /* 401 * There's another psycho using the same register space. Copy the 402 * relevant stuff. 403 */ 404 sc->sc_mem_res = NULL; 405 sc->sc_bustag = osc->sc_bustag; 406 sc->sc_bushandle = osc->sc_bushandle; 407 } 408 if (pcictl_offs < sc->sc_basepaddr) 409 panic("psycho_attach: bogus pci control register location"); 410 sc->sc_pcictl = pcictl_offs - sc->sc_basepaddr; 411 csr = PSYCHO_READ8(sc, PSR_CS); 412 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 413 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 414 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 415 416 device_printf(dev, "%s, impl %d, version %d, ign %x ", 417 desc->pd_name, (int)PSYCHO_GCSR_IMPL(csr), 418 (int)PSYCHO_GCSR_VERS(csr), sc->sc_ign); 419 420 /* 421 * Setup the PCI control register 422 */ 423 csr = PCICTL_READ8(sc, PCR_CS); 424 csr |= PCICTL_MRLM | PCICTL_ARB_PARK | PCICTL_ERRINTEN | PCICTL_4ENABLE; 425 csr &= ~(PCICTL_SERR | PCICTL_CPU_PRIO | PCICTL_ARB_PRIO | 426 PCICTL_RTRYWAIT); 427 PCICTL_WRITE8(sc, PCR_CS, csr); 428 429 /* Grab the psycho ranges */ 430 psycho_get_ranges(sc->sc_node, &sc->sc_range, &sc->sc_nrange); 431 432 /* Initialize memory and i/o rmans */ 433 sc->sc_io_rman.rm_type = RMAN_ARRAY; 434 sc->sc_io_rman.rm_descr = "Psycho PCI I/O Ports"; 435 if (rman_init(&sc->sc_io_rman) != 0 || 436 rman_manage_region(&sc->sc_io_rman, 0, PSYCHO_IO_SIZE) != 0) 437 panic("psycho_probe: failed to set up i/o rman"); 438 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 439 sc->sc_mem_rman.rm_descr = "Psycho PCI Memory"; 440 if (rman_init(&sc->sc_mem_rman) != 0 || 441 rman_manage_region(&sc->sc_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 442 panic("psycho_probe: failed to set up memory rman"); 443 /* 444 * Find the addresses of the various bus spaces. 445 * There should not be multiple ones of one kind. 446 * The physical start addresses of the ranges are the configuration, 447 * memory and IO handles. 448 */ 449 for (n = 0; n < sc->sc_nrange; n++) { 450 i = UPA_RANGE_CS(&sc->sc_range[n]); 451 if (sc->sc_bh[i] != 0) 452 panic("psycho_attach: duplicate range for space %d", i); 453 sc->sc_bh[i] = UPA_RANGE_PHYS(&sc->sc_range[n]); 454 } 455 /* 456 * Check that all needed handles are present. The PCI_CS_MEM64 one is 457 * not currently used. 458 */ 459 for (n = 0; n < 3; n++) { 460 if (sc->sc_bh[n] == 0) 461 panic("psycho_attach: range %d missing", n); 462 } 463 464 /* allocate our tags */ 465 sc->sc_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 466 sc->sc_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 467 sc->sc_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 468 if (bus_dma_tag_create(sc->sc_dmatag, 8, 1, 0, 0x3ffffffff, NULL, NULL, 469 0x3ffffffff, 0xff, 0xffffffff, 0, &sc->sc_dmat) != 0) 470 panic("psycho_attach: bus_dma_tag_create failed"); 471 /* Customize the tag */ 472 sc->sc_dmat->cookie = sc; 473 sc->sc_dmat->dmamap_create = psycho_dmamap_create; 474 sc->sc_dmat->dmamap_destroy = psycho_dmamap_destroy; 475 sc->sc_dmat->dmamap_load = psycho_dmamap_load; 476 sc->sc_dmat->dmamap_unload = psycho_dmamap_unload; 477 sc->sc_dmat->dmamap_sync = psycho_dmamap_sync; 478 sc->sc_dmat->dmamem_alloc = psycho_dmamem_alloc; 479 sc->sc_dmat->dmamem_free = psycho_dmamem_free; 480 /* XXX: register as root dma tag (kluge). */ 481 sparc64_root_dma_tag = sc->sc_dmat; 482 483 /* Register the softc, this is needed for paired psychos. */ 484 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 485 486 /* 487 * And finally, if we're a sabre or the first of a pair of psycho's to 488 * arrive here, start up the IOMMU and get a config space tag. 489 */ 490 if (osc == NULL) { 491 /* 492 * Establish handlers for interesting interrupts.... 493 * 494 * XXX We need to remember these and remove this to support 495 * hotplug on the UPA/FHC bus. 496 * 497 * XXX Not all controllers have these, but installing them 498 * is better than trying to sort through this mess. 499 */ 500 psycho_set_intr(sc, 0, dev, PSR_UE_INT_MAP, INTR_FAST, 501 psycho_ue); 502 psycho_set_intr(sc, 1, dev, PSR_CE_INT_MAP, 0, psycho_ce); 503 psycho_set_intr(sc, 2, dev, PSR_PCIAERR_INT_MAP, INTR_FAST, 504 psycho_bus_a); 505 psycho_set_intr(sc, 4, dev, PSR_POWER_INT_MAP, INTR_FAST, 506 psycho_powerfail); 507 /* Psycho-specific initialization. */ 508 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 509 /* 510 * Sabres do not have the following two interrupts. 511 */ 512 psycho_set_intr(sc, 3, dev, PSR_PCIBERR_INT_MAP, 513 INTR_FAST, psycho_bus_b); 514#ifdef PSYCHO_MAP_WAKEUP 515 /* 516 * psycho_wakeup() doesn't do anything useful right 517 * now. 518 */ 519 psycho_set_intr(sc, 5, dev, PSR_PWRMGT_INT_MAP, 0, 520 psycho_wakeup); 521#endif /* PSYCHO_MAP_WAKEUP */ 522 523 /* Initialize the counter-timer. */ 524 sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, 525 PSR_TC0); 526 } 527 528 /* 529 * Setup IOMMU and PCI configuration if we're the first 530 * of a pair of psycho's to arrive here. 531 * 532 * We should calculate a TSB size based on amount of RAM 533 * and number of bus controllers and number an type of 534 * child devices. 535 * 536 * For the moment, 32KB should be more than enough. 537 */ 538 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 539 M_NOWAIT); 540 if (sc->sc_is == NULL) 541 panic("psycho_attach: malloc iommu_state failed"); 542 sc->sc_is->is_sb[0] = 0; 543 sc->sc_is->is_sb[1] = 0; 544 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 545 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 546 psycho_iommu_init(sc, 2); 547 } else { 548 /* Just copy IOMMU state, config tag and address */ 549 sc->sc_is = osc->sc_is; 550 if (OF_getproplen(sc->sc_node, "no-streaming-cache") < 0) 551 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 552 iommu_reset(sc->sc_is); 553 } 554 555 /* 556 * Enable all interrupts, clear all interrupt states, and install an 557 * interrupt handler for OBIO interrupts, which can be ISA ones 558 * (to frob the interrupt clear registers). 559 * This aids the debugging of interrupt routing problems, and is needed 560 * for isa drivers that use isa_irq_pending (otherwise the registers 561 * will never be cleared). 562 */ 563#if defined(PSYCHO_DEBUG) || defined(PSYCHO_STRAY) 564 for (map = PSR_PCIA0_INT_MAP, clr = PSR_PCIA0_INT_CLR, n = 0; 565 map <= PSR_PCIB3_INT_MAP; map += 8, clr += 32, n++) { 566 mr = PSYCHO_READ8(sc, map); 567#ifdef PSYCHO_DEBUG 568 device_printf(dev, "intr map (pci) %d: %#lx\n", n, (u_long)mr); 569#endif 570 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 571 for (i = 0; i < 4; i++) 572 PCICTL_WRITE8(sc, clr + i * 8, 0); 573 PSYCHO_WRITE8(sc, map, mr | INTMAP_V); 574 } 575 for (map = PSR_SCSI_INT_MAP, clr = PSR_SCSI_INT_CLR, n = 0; 576 map <= PSR_FFB1_INT_MAP; map += 8, clr += 8, n++) { 577 mr = PSYCHO_READ8(sc, map); 578#ifdef PSYCHO_DEBUG 579 device_printf(dev, "intr map (obio) %d: %#lx, clr: %#lx\n", n, 580 (u_long)mr, (u_long)clr); 581#endif 582 PSYCHO_WRITE8(sc, map, mr & ~INTMAP_V); 583 PSYCHO_WRITE8(sc, clr, 0); 584#ifdef PSYCHO_STRAY 585 /* 586 * This can cause interrupt storms, and is therefore disabled 587 * by default. 588 * XXX: use intr_setup() to not confuse higher level code 589 */ 590 if (INTVEC(mr) != 0x7e6 && INTVEC(mr) != 0x7e7 && 591 INTVEC(mr) != 0) { 592 sclr = malloc(sizeof(*sclr), M_DEVBUF, M_WAITOK); 593 sclr->psc_sc = sc; 594 sclr->psc_clr = clr; 595 intr_setup(PIL_LOW, intr_fast, INTVEC(mr), 596 psycho_intr_stray, sclr); 597 } 598#endif 599 PSYCHO_WRITE8(sc, map, mr | INTMAP_V); 600 } 601#endif 602 603 /* 604 * Get the bus range from the firmware; it is used solely for obtaining 605 * the inital bus number, and cannot be trusted on all machines. 606 */ 607 n = OF_getprop(node, "bus-range", (void *)psycho_br, sizeof(psycho_br)); 608 if (n == -1) 609 panic("could not get psycho bus-range"); 610 if (n != sizeof(psycho_br)) 611 panic("broken psycho bus-range (%d)", n); 612 613 sc->sc_busno = ofw_pci_alloc_busno(sc->sc_node); 614 obd.obd_bus = psycho_br[0]; 615 obd.obd_secbus = obd.obd_subbus = sc->sc_busno; 616 obd.obd_slot = PCS_DEVICE; 617 obd.obd_func = PCS_FUNC; 618 obd.obd_init = psycho_binit; 619 obd.obd_super = NULL; 620 /* Initial setup. */ 621 psycho_binit(dev, &obd); 622 /* Update the bus number to what was just programmed. */ 623 obd.obd_bus = obd.obd_secbus; 624 /* 625 * Initialize the interrupt registers of all devices hanging from 626 * the host bridge directly or indirectly via PCI-PCI bridges. 627 * The MI code (and the PCI spec) assume that this is done during 628 * system initialization, however the firmware does not do this 629 * at least on some models, and we probably shouldn't trust that 630 * the firmware uses the same model as this driver if it does. 631 * Additionally, set up the bus numbers and ranges. 632 */ 633 ofw_pci_init(dev, sc->sc_node, sc->sc_ign, &obd); 634 635 device_add_child(dev, "pci", device_get_unit(dev)); 636 return (bus_generic_attach(dev)); 637} 638 639static void 640psycho_set_intr(struct psycho_softc *sc, int index, 641 device_t dev, bus_addr_t map, int iflags, driver_intr_t handler) 642{ 643 int rid, vec; 644 u_int64_t mr; 645 646 mr = PSYCHO_READ8(sc, map); 647 vec = INTVEC(mr); 648 sc->sc_irq_res[index] = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 649 vec, vec, 1, RF_ACTIVE); 650 if (sc->sc_irq_res[index] == NULL) 651 panic("psycho_set_intr: failed to get interrupt"); 652 bus_setup_intr(dev, sc->sc_irq_res[index], INTR_TYPE_MISC | iflags, 653 handler, sc, &sc->sc_ihand[index]); 654 PSYCHO_WRITE8(sc, map, mr | INTMAP_V); 655} 656 657static int 658psycho_find_intrmap(struct psycho_softc *sc, int ino, bus_addr_t *intrmapptr, 659 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 660{ 661 bus_addr_t intrmap, intrclr; 662 u_int64_t im; 663 u_long diag; 664 int found; 665 666 found = 0; 667 /* Hunt thru obio first */ 668 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 669 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 670 intrmap <= PSR_FFB1_INT_MAP; intrmap += 8, intrclr += 8, 671 diag >>= 2) { 672 im = PSYCHO_READ8(sc, intrmap); 673 if (INTINO(im) == ino) { 674 diag &= 2; 675 found = 1; 676 break; 677 } 678 } 679 680 if (!found) { 681 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 682 /* Now do PCI interrupts */ 683 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 684 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 685 diag >>= 8) { 686 im = PSYCHO_READ8(sc, intrmap); 687 if (((im ^ ino) & 0x3c) == 0) { 688 intrclr += 8 * (ino & 3); 689 diag = (diag >> ((ino & 3) * 2)) & 2; 690 found = 1; 691 break; 692 } 693 } 694 } 695 if (intrmapptr != NULL) 696 *intrmapptr = intrmap; 697 if (intrclrptr != NULL) 698 *intrclrptr = intrclr; 699 if (intrdiagptr != NULL) 700 *intrdiagptr = diag; 701 return (found); 702} 703 704/* grovel the OBP for various psycho properties */ 705static void 706psycho_get_ranges(phandle_t node, struct upa_ranges **rp, int *np) 707{ 708 709 *np = OF_getprop_alloc(node, "ranges", sizeof(**rp), (void **)rp); 710 if (*np == -1) 711 panic("could not get psycho ranges"); 712} 713 714/* 715 * Interrupt handlers. 716 */ 717static void 718psycho_ue(void *arg) 719{ 720 struct psycho_softc *sc = (struct psycho_softc *)arg; 721 u_int64_t afar, afsr; 722 723 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 724 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 725 /* 726 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 727 * the AFAR to be set to the physical address of the TTE entry that 728 * was invalid/write protected. Call into the iommu code to have 729 * them decoded to virtual IO addresses. 730 */ 731 if ((afsr & UEAFSR_P_DTE) != 0) 732 iommu_decode_fault(sc->sc_is, afar); 733 /* It's uncorrectable. Dump the regs and panic. */ 734 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx\n", 735 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 736} 737 738static void 739psycho_ce(void *arg) 740{ 741 struct psycho_softc *sc = (struct psycho_softc *)arg; 742 u_int64_t afar, afsr; 743 744 PSYCHO_WRITE8(sc, PSR_CE_INT_CLR, 0); 745 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 746 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 747 /* It's correctable. Dump the regs and continue. */ 748 printf("%s: correctable DMA error AFAR %#lx AFSR %#lx\n", 749 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 750} 751 752static void 753psycho_bus_a(void *arg) 754{ 755 struct psycho_softc *sc = (struct psycho_softc *)arg; 756 u_int64_t afar, afsr; 757 758 afar = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFA); 759 afsr = PSYCHO_READ8(sc, PSR_PCICTL0 + PCR_AFS); 760 /* It's uncorrectable. Dump the regs and panic. */ 761 panic("%s: PCI bus A error AFAR %#lx AFSR %#lx\n", 762 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 763} 764 765static void 766psycho_bus_b(void *arg) 767{ 768 struct psycho_softc *sc = (struct psycho_softc *)arg; 769 u_int64_t afar, afsr; 770 771 afar = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFA); 772 afsr = PSYCHO_READ8(sc, PSR_PCICTL1 + PCR_AFS); 773 /* It's uncorrectable. Dump the regs and panic. */ 774 panic("%s: PCI bus B error AFAR %#lx AFSR %#lx\n", 775 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 776} 777 778static void 779psycho_powerfail(void *arg) 780{ 781 782 /* We lost power. Try to shut down NOW. */ 783#ifdef DEBUGGER_ON_POWERFAIL 784 struct psycho_softc *sc = (struct psycho_softc *)arg; 785 786 Debugger("powerfail"); 787 PSYCHO_WRITE8(sc, PSR_POWER_INT_CLR, 0); 788#else 789 printf("Power Failure Detected: Shutting down NOW.\n"); 790 shutdown_nice(0); 791#endif 792} 793 794#ifdef PSYCHO_MAP_WAKEUP 795static void 796psycho_wakeup(void *arg) 797{ 798 struct psycho_softc *sc = (struct psycho_softc *)arg; 799 800 PSYCHO_WRITE8(sc, PSR_PWRMGT_INT_CLR, 0); 801 /* Gee, we don't really have a framework to deal with this properly. */ 802 printf("%s: power management wakeup\n", device_get_name(sc->sc_dev)); 803} 804#endif /* PSYCHO_MAP_WAKEUP */ 805 806/* initialise the IOMMU... */ 807void 808psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 809{ 810 char *name; 811 struct iommu_state *is = sc->sc_is; 812 u_int32_t iobase = -1; 813 int *vdma = NULL; 814 int nitem; 815 816 /* punch in our copies */ 817 is->is_bustag = sc->sc_bustag; 818 is->is_bushandle = sc->sc_bushandle; 819 is->is_iommu = PSR_IOMMU; 820 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 821 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 822 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 823 is->is_dva = PSR_IOMMU_SVADIAG; 824 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 825 826 /* 827 * Separate the men from the boys. Get the `virtual-dma' 828 * property for sabre and use that to make sure the damn 829 * iommu works. 830 * 831 * We could query the `#virtual-dma-size-cells' and 832 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 833 */ 834 nitem = OF_getprop_alloc(sc->sc_node, "virtual-dma", sizeof(vdma), 835 (void **)&vdma); 836 if (nitem > 0) { 837 iobase = vdma[0]; 838 tsbsize = ffs(vdma[1]); 839 if (tsbsize < 25 || tsbsize > 31 || 840 (vdma[1] & ~(1 << (tsbsize - 1))) != 0) { 841 printf("bogus tsb size %x, using 7\n", vdma[1]); 842 tsbsize = 31; 843 } 844 tsbsize -= 24; 845 free(vdma, M_OFWPROP); 846 } 847 848 /* give us a nice name.. */ 849 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 850 if (name == 0) 851 panic("couldn't malloc iommu name"); 852 snprintf(name, 32, "%s dvma", device_get_name(sc->sc_dev)); 853 854 iommu_init(name, is, tsbsize, iobase, 0); 855} 856 857static void 858psycho_binit(device_t busdev, struct ofw_pci_bdesc *obd) 859{ 860 861#ifdef PSYCHO_DEBUG 862 printf("psycho at %u/%u/%u: setting bus #s to %u/%u/%u\n", 863 obd->obd_bus, obd->obd_slot, obd->obd_func, obd->obd_bus, 864 obd->obd_secbus, obd->obd_subbus); 865#endif /* PSYCHO_DEBUG */ 866 /* 867 * NOTE: this must be kept in this order, since the last write will 868 * change the config space address of the psycho. 869 */ 870 PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func, 871 PCSR_SUBBUS, obd->obd_subbus, 1); 872 PCIB_WRITE_CONFIG(busdev, obd->obd_bus, obd->obd_slot, obd->obd_func, 873 PCSR_SECBUS, obd->obd_secbus, 1); 874} 875 876static int 877psycho_maxslots(device_t dev) 878{ 879 880 /* 881 * XXX: is this correct? At any rate, a number that is too high 882 * shouldn't do any harm, if only because of the way things are 883 * handled in psycho_read_config. 884 */ 885 return (31); 886} 887 888/* 889 * Keep a table of quirky PCI devices that need fixups before the MI PCI code 890 * creates the resource lists. This needs to be moved around once other bus 891 * drivers are added. Moving it to the MI code should maybe be reconsidered 892 * if one of these devices appear in non-sparc64 boxen. It's likely that not 893 * all BIOSes/firmwares can deal with them. 894 */ 895struct psycho_dquirk { 896 u_int32_t dq_devid; 897 int dq_quirk; 898}; 899 900/* Quirk types. May be or'ed together. */ 901#define DQT_BAD_INTPIN 1 /* Intpin reg 0, but intpin used */ 902 903static struct psycho_dquirk dquirks[] = { 904 { 0x1001108e, DQT_BAD_INTPIN }, /* Sun HME (PCIO func. 1) */ 905 { 0x1101108e, DQT_BAD_INTPIN }, /* Sun GEM (PCIO2 func. 1) */ 906 { 0x1102108e, DQT_BAD_INTPIN }, /* Sun FireWire ctl. (PCIO2 func. 2) */ 907 { 0x1103108e, DQT_BAD_INTPIN }, /* Sun USB ctl. (PCIO2 func. 3) */ 908}; 909 910#define NDQUIRKS (sizeof(dquirks) / sizeof(dquirks[0])) 911 912static u_int32_t 913psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 914 int width) 915{ 916 struct psycho_softc *sc; 917 bus_space_handle_t bh; 918 u_long offset = 0; 919 u_int32_t r, devid; 920 int i; 921 922 /* 923 * The psycho bridge does not tolerate accesses to unconfigured PCI 924 * devices' or function's config space, so look up the device in the 925 * firmware device tree first, and if it is not present, return a value 926 * that will make the detection code think that there is no device here. 927 * This is ugly... 928 */ 929 if (reg == 0 && ofw_pci_find_node(bus, slot, func) == 0) 930 return (0xffffffff); 931 sc = (struct psycho_softc *)device_get_softc(dev); 932 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 933 bh = sc->sc_bh[PCI_CS_CONFIG]; 934 switch (width) { 935 case 1: 936 r = bus_space_read_1(sc->sc_cfgt, bh, offset); 937 break; 938 case 2: 939 r = bus_space_read_2(sc->sc_cfgt, bh, offset); 940 break; 941 case 4: 942 r = bus_space_read_4(sc->sc_cfgt, bh, offset); 943 break; 944 default: 945 panic("psycho_read_config: bad width"); 946 } 947 if (reg == PCIR_INTPIN && r == 0) { 948 /* Check for DQT_BAD_INTPIN quirk. */ 949 devid = psycho_read_config(dev, bus, slot, func, 950 PCIR_DEVVENDOR, 4); 951 for (i = 0; i < NDQUIRKS; i++) { 952 if (dquirks[i].dq_devid == devid) { 953 /* 954 * Need to set the intpin to a value != 0 so 955 * that the MI code will think that this device 956 * has an interrupt. 957 * Just use 1 (intpin a) for now. This is, of 958 * course, bogus, but since interrupts are 959 * routed in advance, this does not really 960 * matter. 961 */ 962 if ((dquirks[i].dq_quirk & DQT_BAD_INTPIN) != 0) 963 r = 1; 964 break; 965 } 966 } 967 } 968 return (r); 969} 970 971static void 972psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, 973 u_int reg, u_int32_t val, int width) 974{ 975 struct psycho_softc *sc; 976 bus_space_handle_t bh; 977 u_long offset = 0; 978 979 sc = (struct psycho_softc *)device_get_softc(dev); 980 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 981 bh = sc->sc_bh[PCI_CS_CONFIG]; 982 switch (width) { 983 case 1: 984 bus_space_write_1(sc->sc_cfgt, bh, offset, val); 985 break; 986 case 2: 987 bus_space_write_2(sc->sc_cfgt, bh, offset, val); 988 break; 989 case 4: 990 bus_space_write_4(sc->sc_cfgt, bh, offset, val); 991 break; 992 default: 993 panic("psycho_write_config: bad width"); 994 } 995} 996 997static int 998psycho_route_interrupt(device_t bus, device_t dev, int pin) 999{ 1000 1001 /* 1002 * XXX: ugly loathsome hack: 1003 * We can't use ofw_pci_route_intr() here; the device passed may be 1004 * the one of a bridge, so the original device can't be recovered. 1005 * 1006 * We need to use the firmware to route interrupts, however it has 1007 * no interface which could be used to interpret intpins; instead, 1008 * all assignments are done by device. 1009 * 1010 * The MI pci code will try to reroute interrupts of 0, although they 1011 * are correct; all other interrupts are preinitialized, so if we 1012 * get here, the intline is either 0 (so return 0), or we hit a 1013 * device which was not preinitialized (e.g. hotplugged stuff), in 1014 * which case we are lost. 1015 */ 1016 return (0); 1017} 1018 1019static int 1020psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1021{ 1022 struct psycho_softc *sc; 1023 1024 sc = (struct psycho_softc *)device_get_softc(dev); 1025 switch (which) { 1026 case PCIB_IVAR_BUS: 1027 *result = sc->sc_busno; 1028 return (0); 1029 } 1030 return (ENOENT); 1031} 1032 1033/* Write to the correct clr register, and call the actual handler. */ 1034static void 1035psycho_intr_stub(void *arg) 1036{ 1037 struct psycho_clr *pc; 1038 1039 pc = (struct psycho_clr *)arg; 1040 pc->pci_handler(pc->pci_arg); 1041 PSYCHO_WRITE8(pc->pci_sc, pc->pci_clr, 0); 1042} 1043 1044#ifdef PSYCHO_STRAY 1045/* 1046 * Write to the correct clr register and return. arg is the address of the clear 1047 * register to be used. 1048 * XXX: print a message? 1049 */ 1050static void 1051psycho_intr_stray(void *arg) 1052{ 1053 struct psycho_strayclr *sclr = arg; 1054 1055 PSYCHO_WRITE8(sclr->psc_sc, sclr->psc_clr, 0); 1056} 1057#endif 1058 1059static int 1060psycho_setup_intr(device_t dev, device_t child, 1061 struct resource *ires, int flags, driver_intr_t *intr, void *arg, 1062 void **cookiep) 1063{ 1064 struct psycho_softc *sc; 1065 struct psycho_clr *pc; 1066 bus_addr_t intrmapptr, intrclrptr; 1067 long vec = rman_get_start(ires); 1068 u_int64_t mr; 1069 int ino, error; 1070 1071 sc = (struct psycho_softc *)device_get_softc(dev); 1072 pc = (struct psycho_clr *)malloc(sizeof(*pc), M_DEVBUF, M_NOWAIT); 1073 if (pc == NULL) 1074 return (NULL); 1075 1076 /* 1077 * Hunt through all the interrupt mapping regs to look for our 1078 * interrupt vector. 1079 * 1080 * XXX We only compare INOs rather than IGNs since the firmware may 1081 * not provide the IGN and the IGN is constant for all device on that 1082 * PCI controller. This could cause problems for the FFB/external 1083 * interrupt which has a full vector that can be set arbitrarily. 1084 */ 1085 ino = INTINO(vec); 1086 1087 if (!psycho_find_intrmap(sc, ino, &intrmapptr, &intrclrptr, NULL)) { 1088 printf("Cannot find interrupt vector %lx\n", vec); 1089 free(pc, M_DEVBUF); 1090 return (NULL); 1091 } 1092 1093#ifdef PSYCHO_DEBUG 1094 device_printf(dev, "psycho_setup_intr: INO %d, map %#lx, clr %#lx\n", 1095 ino, (u_long)intrmapptr, (u_long)intrclrptr); 1096#endif 1097 pc->pci_sc = sc; 1098 pc->pci_arg = arg; 1099 pc->pci_handler = intr; 1100 pc->pci_clr = intrclrptr; 1101 /* Disable the interrupt while we fiddle with it */ 1102 mr = PSYCHO_READ8(sc, intrmapptr); 1103 PSYCHO_WRITE8(sc, intrmapptr, mr & ~INTMAP_V); 1104 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 1105 psycho_intr_stub, pc, cookiep); 1106 if (error != 0) { 1107 free(pc, M_DEVBUF); 1108 return (error); 1109 } 1110 pc->pci_cookie = *cookiep; 1111 *cookiep = pc; 1112 1113 /* 1114 * Clear the interrupt, it might have been triggered before it was 1115 * set up. 1116 */ 1117 PSYCHO_WRITE8(sc, intrclrptr, 0); 1118 /* 1119 * Enable the interrupt now we have the handler installed. 1120 * Read the current value as we can't change it besides the 1121 * valid bit so so make sure only this bit is changed. 1122 */ 1123 PSYCHO_WRITE8(sc, intrmapptr, mr | INTMAP_V); 1124 return (error); 1125} 1126 1127static int 1128psycho_teardown_intr(device_t dev, device_t child, 1129 struct resource *vec, void *cookie) 1130{ 1131 struct psycho_clr *pc; 1132 int error; 1133 1134 pc = (struct psycho_clr *)cookie; 1135 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 1136 pc->pci_cookie); 1137 /* 1138 * Don't disable the interrupt for now, so that stray interupts get 1139 * detected... 1140 */ 1141 if (error != 0) 1142 free(pc, M_DEVBUF); 1143 return (error); 1144} 1145 1146static struct resource * 1147psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1148 u_long start, u_long end, u_long count, u_int flags) 1149{ 1150 struct psycho_softc *sc; 1151 struct resource *rv; 1152 struct rman *rm; 1153 bus_space_tag_t bt; 1154 bus_space_handle_t bh; 1155 int needactivate = flags & RF_ACTIVE; 1156 1157 flags &= ~RF_ACTIVE; 1158 1159 sc = (struct psycho_softc *)device_get_softc(bus); 1160 if (type == SYS_RES_IRQ) { 1161 /* 1162 * XXX: Don't accept blank ranges for now, only single 1163 * interrupts. The other case should not happen with the MI pci 1164 * code... 1165 * XXX: This may return a resource that is out of the range 1166 * that was specified. Is this correct...? 1167 */ 1168 if (start != end) 1169 panic("psycho_alloc_resource: XXX: interrupt range"); 1170 start = end |= sc->sc_ign; 1171 return (bus_alloc_resource(bus, type, rid, start, end, 1172 count, flags)); 1173 } 1174 switch (type) { 1175 case SYS_RES_MEMORY: 1176 rm = &sc->sc_mem_rman; 1177 bt = sc->sc_memt; 1178 bh = sc->sc_bh[PCI_CS_MEM32]; 1179 break; 1180 case SYS_RES_IOPORT: 1181 rm = &sc->sc_io_rman; 1182 bt = sc->sc_iot; 1183 /* XXX: probably should use ranges property here. */ 1184 bh = sc->sc_bh[PCI_CS_IO]; 1185 break; 1186 default: 1187 return (NULL); 1188 } 1189 1190 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1191 if (rv == NULL) 1192 return (NULL); 1193 1194 bh += rman_get_start(rv); 1195 rman_set_bustag(rv, bt); 1196 rman_set_bushandle(rv, bh); 1197 1198 if (needactivate) { 1199 if (bus_activate_resource(child, type, *rid, rv)) { 1200 rman_release_resource(rv); 1201 return (NULL); 1202 } 1203 } 1204 1205 return (rv); 1206} 1207 1208static int 1209psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1210 struct resource *r) 1211{ 1212 void *p; 1213 int error; 1214 1215 if (type == SYS_RES_IRQ) 1216 return (bus_activate_resource(bus, type, rid, r)); 1217 if (type == SYS_RES_MEMORY) { 1218 /* 1219 * Need to memory-map the device space, as some drivers depend 1220 * on the virtual address being set and useable. 1221 */ 1222 error = sparc64_bus_mem_map(rman_get_bustag(r), 1223 rman_get_bushandle(r), rman_get_size(r), 0, NULL, &p); 1224 if (error != 0) 1225 return (error); 1226 rman_set_virtual(r, p); 1227 } 1228 return (rman_activate_resource(r)); 1229} 1230 1231static int 1232psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1233 struct resource *r) 1234{ 1235 1236 if (type == SYS_RES_IRQ) 1237 return (bus_deactivate_resource(bus, type, rid, r)); 1238 if (type == SYS_RES_MEMORY) { 1239 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1240 rman_set_virtual(r, NULL); 1241 } 1242 return (rman_deactivate_resource(r)); 1243} 1244 1245static int 1246psycho_release_resource(device_t bus, device_t child, int type, int rid, 1247 struct resource *r) 1248{ 1249 int error; 1250 1251 if (type == SYS_RES_IRQ) 1252 return (bus_release_resource(bus, type, rid, r)); 1253 if (rman_get_flags(r) & RF_ACTIVE) { 1254 error = bus_deactivate_resource(child, type, rid, r); 1255 if (error) 1256 return error; 1257 } 1258 return (rman_release_resource(r)); 1259} 1260 1261static int 1262psycho_intr_pending(device_t dev, int intr) 1263{ 1264 struct psycho_softc *sc; 1265 u_long diag; 1266 1267 sc = (struct psycho_softc *)device_get_softc(dev); 1268 if (!psycho_find_intrmap(sc, intr, NULL, NULL, &diag)) { 1269 printf("psycho_intr_pending: mapping not found for %d\n", intr); 1270 return (0); 1271 } 1272 return (diag != 0); 1273} 1274 1275static bus_space_handle_t 1276psycho_get_bus_handle(device_t dev, enum sbbt_id id, 1277 bus_space_handle_t childhdl, bus_space_tag_t *tag) 1278{ 1279 struct psycho_softc *sc; 1280 1281 sc = (struct psycho_softc *)device_get_softc(dev); 1282 switch(id) { 1283 case SBBT_IO: 1284 *tag = sc->sc_iot; 1285 return (sc->sc_bh[PCI_CS_IO] + childhdl); 1286 case SBBT_MEM: 1287 *tag = sc->sc_memt; 1288 return (sc->sc_bh[PCI_CS_MEM32] + childhdl); 1289 default: 1290 panic("psycho_get_bus_handle: illegal space\n"); 1291 } 1292} 1293 1294/* 1295 * below here is bus space and bus dma support 1296 */ 1297static bus_space_tag_t 1298psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1299{ 1300 bus_space_tag_t bt; 1301 1302 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1303 M_NOWAIT | M_ZERO); 1304 if (bt == NULL) 1305 panic("psycho_alloc_bus_tag: out of memory"); 1306 1307 bzero(bt, sizeof *bt); 1308 bt->cookie = sc; 1309 bt->parent = sc->sc_bustag; 1310 bt->type = type; 1311 return (bt); 1312} 1313 1314/* 1315 * hooks into the iommu dvma calls. 1316 */ 1317static int 1318psycho_dmamem_alloc(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void **vaddr, 1319 int flags, bus_dmamap_t *mapp) 1320{ 1321 struct psycho_softc *sc; 1322 1323 sc = (struct psycho_softc *)pdmat->cookie; 1324 return (iommu_dvmamem_alloc(pdmat, ddmat, sc->sc_is, vaddr, flags, 1325 mapp)); 1326} 1327 1328static void 1329psycho_dmamem_free(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void *vaddr, 1330 bus_dmamap_t map) 1331{ 1332 struct psycho_softc *sc; 1333 1334 sc = (struct psycho_softc *)pdmat->cookie; 1335 iommu_dvmamem_free(pdmat, ddmat, sc->sc_is, vaddr, map); 1336} 1337 1338static int 1339psycho_dmamap_create(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, int flags, 1340 bus_dmamap_t *mapp) 1341{ 1342 struct psycho_softc *sc; 1343 1344 sc = (struct psycho_softc *)pdmat->cookie; 1345 return (iommu_dvmamap_create(pdmat, ddmat, sc->sc_is, flags, mapp)); 1346 1347} 1348 1349static int 1350psycho_dmamap_destroy(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, 1351 bus_dmamap_t map) 1352{ 1353 struct psycho_softc *sc; 1354 1355 sc = (struct psycho_softc *)pdmat->cookie; 1356 return (iommu_dvmamap_destroy(pdmat, ddmat, sc->sc_is, map)); 1357} 1358 1359static int 1360psycho_dmamap_load(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map, 1361 void *buf, bus_size_t buflen, bus_dmamap_callback_t *callback, 1362 void *callback_arg, int flags) 1363{ 1364 struct psycho_softc *sc; 1365 1366 sc = (struct psycho_softc *)pdmat->cookie; 1367 return (iommu_dvmamap_load(pdmat, ddmat, sc->sc_is, map, buf, buflen, 1368 callback, callback_arg, flags)); 1369} 1370 1371static void 1372psycho_dmamap_unload(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map) 1373{ 1374 struct psycho_softc *sc; 1375 1376 sc = (struct psycho_softc *)pdmat->cookie; 1377 iommu_dvmamap_unload(pdmat, ddmat, sc->sc_is, map); 1378} 1379 1380static void 1381psycho_dmamap_sync(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map, 1382 bus_dmasync_op_t op) 1383{ 1384 struct psycho_softc *sc; 1385 1386 sc = (struct psycho_softc *)pdmat->cookie; 1387 iommu_dvmamap_sync(pdmat, ddmat, sc->sc_is, map, op); 1388} 1389