1201052Smarius/*- 2201052Smarius * Copyright (c) 2009 Marius Strobl <marius@FreeBSD.org> 3201052Smarius * All rights reserved. 4201052Smarius * 5201052Smarius * Redistribution and use in source and binary forms, with or without 6201052Smarius * modification, are permitted provided that the following conditions 7201052Smarius * are met: 8201052Smarius * 1. Redistributions of source code must retain the above copyright 9201052Smarius * notice, this list of conditions and the following disclaimer. 10201052Smarius * 2. Redistributions in binary form must reproduce the above copyright 11201052Smarius * notice, this list of conditions and the following disclaimer in the 12201052Smarius * documentation and/or other materials provided with the distribution. 13201052Smarius * 14201052Smarius * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15201052Smarius * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16201052Smarius * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17201052Smarius * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18201052Smarius * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19201052Smarius * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20201052Smarius * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21201052Smarius * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22201052Smarius * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23201052Smarius * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24201052Smarius * SUCH DAMAGE. 25201052Smarius * 26201052Smarius * $FreeBSD$ 27201052Smarius */ 28201052Smarius 29201052Smarius#ifndef _SPARC64_PCI_FIREREG_H_ 30201052Smarius#define _SPARC64_PCI_FIREREG_H_ 31201052Smarius 32201052Smarius#define FIRE_NINTR 3 /* 2 OFW + 1 MSIq */ 33201052Smarius#define FIRE_NREG 2 34201052Smarius 35201052Smarius#define FIRE_PCI 0 36201052Smarius#define FIRE_CTRL 1 37201052Smarius 38201052Smarius/* PCI configuration and status registers */ 39201052Smarius#define FO_PCI_INT_MAP_BASE 0x01000 40201052Smarius#define FO_PCI_INT_CLR_BASE 0x01400 41201052Smarius#define FO_PCI_EQ_BASE_ADDR 0x10000 42201052Smarius#define FO_PCI_EQ_CTRL_SET_BASE 0x11000 43201052Smarius#define FO_PCI_EQ_CTRL_CLR_BASE 0x11200 44201052Smarius#define FO_PCI_EQ_TL_BASE 0x11600 45201052Smarius#define FO_PCI_EQ_HD_BASE 0x11800 46201052Smarius#define FO_PCI_MSI_MAP_BASE 0x20000 47201052Smarius#define FO_PCI_MSI_CLR_BASE 0x28000 48201052Smarius#define FO_PCI_ERR_COR 0x30000 49201052Smarius#define FO_PCI_ERR_NONFATAL 0x30008 50201052Smarius#define FO_PCI_ERR_FATAL 0x30010 51201052Smarius#define FO_PCI_PM_PME 0x30018 52201052Smarius#define FO_PCI_PME_TO_ACK 0x30020 53201052Smarius#define FO_PCI_IMU_INT_EN 0x31008 54201052Smarius#define FO_PCI_IMU_INT_STAT 0x31010 55201052Smarius#define FO_PCI_IMU_ERR_STAT_CLR 0x31018 56201052Smarius#define FO_PCI_IMU_RDS_ERR_LOG 0x31028 57201052Smarius#define FO_PCI_IMU_SCS_ERR_LOG 0x31030 58201052Smarius#define FO_PCI_IMU_EQS_ERR_LOG 0x31038 59201052Smarius#define FO_PCI_DMC_CORE_BLOCK_INT_EN 0x31800 60201052Smarius#define FO_PCI_DMC_CORE_BLOCK_ERR_STAT 0x31808 61201052Smarius#define FO_PCI_MULTI_CORE_ERR_STAT 0x31810 62201052Smarius#define FO_PCI_MSI_32_BIT_ADDR 0x34000 63201052Smarius#define FO_PCI_MSI_64_BIT_ADDR 0x34008 64201052Smarius#define FO_PCI_MMU 0x40000 65201052Smarius#define FO_PCI_MMU_INT_EN 0x41008 66201052Smarius#define FO_PCI_MMU_INT_STAT 0x41010 67201052Smarius#define FO_PCI_MMU_ERR_STAT_CLR 0x41018 68201052Smarius#define FO_PCI_MMU_TRANS_FAULT_ADDR 0x41028 69201052Smarius#define FO_PCI_MMU_TRANS_FAULT_STAT 0x41030 70201052Smarius#define FO_PCI_ILU_INT_EN 0x51008 71201052Smarius#define FO_PCI_ILU_INT_STAT 0x51010 72201052Smarius#define FO_PCI_ILU_ERR_STAT_CLR 0x51018 73201052Smarius#define FO_PCI_DMC_DBG_SEL_PORTA 0x53000 74201052Smarius#define FO_PCI_DMC_DBG_SEL_PORTB 0x53008 75201052Smarius#define FO_PCI_PEC_CORE_BLOCK_INT_EN 0x51800 76201052Smarius#define FO_PCI_PEC_CORE_BLOCK_INT_STAT 0x51808 77201052Smarius#define FO_PCI_TLU_CTRL 0x80000 78201052Smarius#define FO_PCI_TLU_OEVENT_INT_EN 0x81008 79201052Smarius#define FO_PCI_TLU_OEVENT_INT_STAT 0x81010 80201052Smarius#define FO_PCI_TLU_OEVENT_STAT_CLR 0x81018 81201052Smarius#define FO_PCI_TLU_RX_OEVENT_HDR1_LOG 0x81028 82201052Smarius#define FO_PCI_TLU_RX_OEVENT_HDR2_LOG 0x81030 83201052Smarius#define FO_PCI_TLU_TX_OEVENT_HDR1_LOG 0x81038 84201052Smarius#define FO_PCI_TLU_TX_OEVENT_HDR2_LOG 0x81040 85201052Smarius#define FO_PCI_TLU_DEV_CTRL 0x90008 86201052Smarius#define FO_PCI_TLU_LNK_CTRL 0x90020 87201052Smarius#define FO_PCI_TLU_LNK_STAT 0x90028 88201052Smarius#define FO_PCI_TLU_UERR_INT_EN 0x91008 89201052Smarius#define FO_PCI_TLU_UERR_INT_STAT 0x91010 90201052Smarius#define FO_PCI_TLU_UERR_STAT_CLR 0x91018 91201052Smarius#define FO_PCI_TLU_RX_UERR_HDR1_LOG 0x91028 92201052Smarius#define FO_PCI_TLU_RX_UERR_HDR2_LOG 0x91030 93201052Smarius#define FO_PCI_TLU_TX_UERR_HDR1_LOG 0x91038 94201052Smarius#define FO_PCI_TLU_TX_UERR_HDR2_LOG 0x91040 95201052Smarius#define FO_PCI_TLU_CERR_INT_EN 0xa1008 96201052Smarius#define FO_PCI_TLU_CERR_INT_STAT 0xa1010 97201052Smarius#define FO_PCI_TLU_CERR_STAT_CLR 0xa1018 98201052Smarius#define FO_PCI_LPU_RST 0xe2008 99201052Smarius#define FO_PCI_LPU_INT_STAT 0xe2040 100201052Smarius#define FO_PCI_LPU_INT_MASK 0xe0248 101201052Smarius#define FO_PCI_LPU_LNK_LYR_CFG 0xe2200 102201052Smarius#define FO_PCI_LPU_LNK_LYR_INT_STAT 0xe2210 103201052Smarius#define FO_PCI_LPU_FLW_CTRL_UPDT_CTRL 0xe2240 104201052Smarius#define FO_PCI_LPU_TXLNK_FREQ_LAT_TMR_THRS 0xe2400 105201052Smarius#define FO_PCI_LPU_TXLNK_RPLY_TMR_THRS 0xe2410 106201052Smarius#define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR 0xe2430 107201052Smarius#define FO_PCI_LPU_PHY_LYR_INT_STAT 0xe2610 108201052Smarius#define FO_PCI_LPU_LTSSM_CFG2 0xe2788 109201052Smarius#define FO_PCI_LPU_LTSSM_CFG3 0xe2790 110201052Smarius#define FO_PCI_LPU_LTSSM_CFG4 0xe2798 111201052Smarius#define FO_PCI_LPU_LTSSM_CFG5 0xe27a0 112201052Smarius 113201052Smarius/* PCI interrupt mapping registers */ 114201052Smarius#define FO_PCI_IMAP_MDO_MODE 0x8000000000000000ULL 115201052Smarius#define FO_PCI_IMAP_V 0x0000000080000000ULL 116201052Smarius#define FIRE_PCI_IMAP_T_JPID_MASK 0x000000007c000000ULL 117201052Smarius#define FIRE_PCI_IMAP_T_JPID_SHFT 26 118201052Smarius#define OBERON_PCI_IMAP_T_DESTID_MASK 0x000000007fe00000ULL 119201052Smarius#define OBERON_PCI_IMAP_T_DESTID_SHFT 21 120201052Smarius#define FO_PCI_IMAP_INT_CTRL_NUM_MASK 0x00000000000003c0ULL 121201052Smarius#define FO_PCI_IMAP_INT_CTRL_NUM_SHFT 6 122201052Smarius 123201052Smarius/* PCI interrupt clear registers - use INTCLR_* from <machine/bus_common.h> */ 124201052Smarius 125201052Smarius/* PCI event queue base address register */ 126201052Smarius#define FO_PCI_EQ_BASE_ADDR_BYPASS 0xfffc000000000000ULL 127201052Smarius#define FO_PCI_EQ_BASE_ADDR_MASK 0xfffffffffff80000ULL 128201052Smarius#define FO_PCI_EQ_BASE_ADDR_SHFT 19 129201052Smarius 130201052Smarius/* PCI event queue control set registers */ 131201052Smarius#define FO_PCI_EQ_CTRL_SET_ENOVERR 0x0200000000000000ULL 132201052Smarius#define FO_PCI_EQ_CTRL_SET_EN 0x0000100000000000ULL 133201052Smarius 134201052Smarius/* PCI event queue control clear registers */ 135201052Smarius#define FO_PCI_EQ_CTRL_CLR_COVERR 0x0200000000000000ULL 136201052Smarius#define FO_PCI_EQ_CTRL_CLR_E2I 0x0000800000000000ULL 137201052Smarius#define FO_PCI_EQ_CTRL_CLR_DIS 0x0000100000000000ULL 138201052Smarius 139201052Smarius/* PCI event queue tail registers */ 140201052Smarius#define FO_PCI_EQ_TL_OVERR 0x0200000000000000ULL 141201052Smarius#define FO_PCI_EQ_TL_MASK 0x000000000000007fULL 142201052Smarius#define FO_PCI_EQ_TL_SHFT 0 143201052Smarius 144201052Smarius/* PCI event queue head registers */ 145201052Smarius#define FO_PCI_EQ_HD_MASK 0x000000000000007fULL 146201052Smarius#define FO_PCI_EQ_HD_SHFT 0 147201052Smarius 148201052Smarius/* PCI MSI mapping registers */ 149201052Smarius#define FO_PCI_MSI_MAP_V 0x8000000000000000ULL 150201052Smarius#define FO_PCI_MSI_MAP_EQWR_N 0x4000000000000000ULL 151201052Smarius#define FO_PCI_MSI_MAP_EQNUM_MASK 0x000000000000003fULL 152201052Smarius#define FO_PCI_MSI_MAP_EQNUM_SHFT 0 153201052Smarius 154201052Smarius/* PCI MSI clear registers */ 155201052Smarius#define FO_PCI_MSI_CLR_EQWR_N 0x4000000000000000ULL 156201052Smarius 157201052Smarius/* 158201052Smarius * PCI IMU interrupt enable, interrupt status and error status clear 159201052Smarius * registers 160201052Smarius */ 161201052Smarius#define FO_PCI_IMU_ERR_INT_SPARE_S_MASK 0x00007c0000000000ULL 162201052Smarius#define FO_PCI_IMU_ERR_INT_SPARE_S_SHFT 42 163201052Smarius#define FO_PCI_IMU_ERR_INT_EQ_OVER_S 0x0000020000000000ULL 164201052Smarius#define FO_PCI_IMU_ERR_INT_EQ_NOT_EN_S 0x0000010000000000ULL 165201052Smarius#define FO_PCI_IMU_ERR_INT_MSI_MAL_ERR_S 0x0000008000000000ULL 166201052Smarius#define FO_PCI_IMU_ERR_INT_MSI_PAR_ERR_S 0x0000004000000000ULL 167201052Smarius#define FO_PCI_IMU_ERR_INT_PMEACK_MES_NOT_EN_S 0x0000002000000000ULL 168201052Smarius#define FO_PCI_IMU_ERR_INT_PMPME_MES_NOT_EN_S 0x0000001000000000ULL 169201052Smarius#define FO_PCI_IMU_ERR_INT_FATAL_MES_NOT_EN_S 0x0000000800000000ULL 170201052Smarius#define FO_PCI_IMU_ERR_INT_NFATAL_MES_NOT_EN_S 0x0000000400000000ULL 171201052Smarius#define FO_PCI_IMU_ERR_INT_COR_MES_NOT_EN_S 0x0000000200000000ULL 172201052Smarius#define FO_PCI_IMU_ERR_INT_MSI_NOT_EN_S 0x0000000100000000ULL 173201052Smarius#define FO_PCI_IMU_ERR_INT_SPARE_P_MASK 0x0000000000007c00ULL 174201052Smarius#define FO_PCI_IMU_ERR_INT_SPARE_P_SHFT 10 175201052Smarius#define FO_PCI_IMU_ERR_INT_EQ_OVER_P 0x0000000000000200ULL 176201052Smarius#define FO_PCI_IMU_ERR_INT_EQ_NOT_EN_P 0x0000000000000100ULL 177201052Smarius#define FO_PCI_IMU_ERR_INT_MSI_MAL_ERR_P 0x0000000000000080ULL 178201052Smarius#define FO_PCI_IMU_ERR_INT_MSI_PAR_ERR_P 0x0000000000000040ULL 179201052Smarius#define FO_PCI_IMU_ERR_INT_PMEACK_MES_NOT_EN_P 0x0000000000000020ULL 180201052Smarius#define FO_PCI_IMU_ERR_INT_PMPME_MES_NOT_EN_P 0x0000000000000010ULL 181201052Smarius#define FO_PCI_IMU_ERR_INT_FATAL_MES_NOT_EN_P 0x0000000000000008ULL 182201052Smarius#define FO_PCI_IMU_ERR_INT_NFATAL_MES_NOT_EN_P 0x0000000000000004ULL 183201052Smarius#define FO_PCI_IMU_ERR_INT_COR_MES_NOT_EN_P 0x0000000000000002ULL 184201052Smarius#define FO_PCI_IMU_ERR_INT_MSI_NOT_EN_P 0x0000000000000001ULL 185201052Smarius 186201052Smarius/* PCI IMU RDS error log register */ 187201052Smarius#define FO_PCI_IMU_RDS_ERR_LOG_TYPE_MASK 0xfc00000000000000ULL 188201052Smarius#define FO_PCI_IMU_RDS_ERR_LOG_TYPE_SHFT 58 189201052Smarius#define FO_PCI_IMU_RDS_ERR_LOG_LENGTH_MASK 0x03ff000000000000ULL 190201052Smarius#define FO_PCI_IMU_RDS_ERR_LOG_LENGTH_SHFT 48 191201052Smarius#define FO_PCI_IMU_RDS_ERR_LOG_REQ_ID_MASK 0x0000ffff00000000ULL 192201052Smarius#define FO_PCI_IMU_RDS_ERR_LOG_REQ_ID_SHFT 32 193201052Smarius#define FO_PCI_IMU_RDS_ERR_LOG_TLP_TAG_MASK 0x00000000ff000000ULL 194201052Smarius#define FO_PCI_IMU_RDS_ERR_LOG_TLP_TAG_SHFT 24 195201052Smarius#define FO_PCI_IMU_RDS_ERR_LOG_BE_MCODE_MASK 0x0000000000ff0000ULL 196201052Smarius#define FO_PCI_IMU_RDS_ERR_LOG_BE_MCODE_SHFT 16 197201052Smarius#define FO_PCI_IMU_RDS_ERR_LOG_MSI_DATA_MASK 0x000000000000ffffULL 198201052Smarius#define FO_PCI_IMU_RDS_ERR_LOG_MSI_DATA_SHFT 0 199201052Smarius 200201052Smarius/* PCI IMU SCS error log register */ 201201052Smarius#define FO_PCI_IMU_SCS_ERR_LOG_TYPE_MASK 0xfc00000000000000ULL 202201052Smarius#define FO_PCI_IMU_SCS_ERR_LOG_TYPE_SHFT 58 203201052Smarius#define FO_PCI_IMU_SCS_ERR_LOG_LENGTH_MASK 0x03ff000000000000ULL 204201052Smarius#define FO_PCI_IMU_SCS_ERR_LOG_LENGTH_SHFT 48 205201052Smarius#define FO_PCI_IMU_SCS_ERR_LOG_REQ_ID_MASK 0x0000ffff00000000ULL 206201052Smarius#define FO_PCI_IMU_SCS_ERR_LOG_REQ_ID_SHFT 32 207201052Smarius#define FO_PCI_IMU_SCS_ERR_LOG_TLP_TAG_MASK 0x00000000ff000000ULL 208201052Smarius#define FO_PCI_IMU_SCS_ERR_LOG_TLP_TAG_SHFT 24 209201052Smarius#define FO_PCI_IMU_SCS_ERR_LOG_BE_MODE_MASK 0x0000000000ff0000ULL 210201052Smarius#define FO_PCI_IMU_SCS_ERR_LOG_BE_MCODE_SHFT 16 211201052Smarius#define FO_PCI_IMU_SCS_ERR_LOG_EQ_NUM_MASK 0x000000000000003fULL 212201052Smarius#define FO_PCI_IMU_SCS_ERR_LOG_EQ_NUM_SHFT 0 213201052Smarius 214201052Smarius/* PCI IMU EQS error log register */ 215201052Smarius#define FO_PCI_IMU_EQS_ERR_LOG_EQ_NUM_MASK 0x000000000000003fULL 216201052Smarius#define FO_PCI_IMU_EQS_ERROR_LOG_EQ_NUM_SHFT 0 217201052Smarius 218201052Smarius/* 219201052Smarius * PCI ERR COR, ERR NONFATAL, ERR FATAL, PM PME and PME To ACK mapping 220201052Smarius * registers 221201052Smarius */ 222201052Smarius#define FO_PCI_ERR_PME_V 0x8000000000000000ULL 223201052Smarius#define FO_PCI_ERR_PME_EQNUM_MASK 0x000000000000003fULL 224201052Smarius#define FO_PCI_ERR_PME_EQNUM_SHFT 0 225201052Smarius 226201052Smarius/* PCI DMC core and block interrupt enable register */ 227201052Smarius#define FO_PCI_DMC_CORE_BLOCK_INT_EN_DMC 0x8000000000000000ULL 228201052Smarius#define FO_PCI_DMC_CORE_BLOCK_INT_EN_MMU 0x0000000000000002ULL 229201052Smarius#define FO_PCI_DMC_CORE_BLOCK_INT_EN_IMU 0x0000000000000001ULL 230201052Smarius 231201052Smarius/* PCI DMC core and block error status register */ 232201052Smarius#define FO_PCI_DMC_CORE_BLOCK_ERR_STAT_MMU 0x0000000000000002ULL 233201052Smarius#define FO_PCI_DMC_CORE_BLOCK_ERR_STAT_IMU 0x0000000000000001ULL 234201052Smarius 235201052Smarius/* PCI multi core error status register */ 236201052Smarius#define FO_PCI_MULTI_CORE_ERR_STAT_PEC 0x0000000000000002ULL 237201052Smarius#define FO_PCI_MULTI_CORE_ERR_STAT_DMC 0x0000000000000001ULL 238201052Smarius 239201052Smarius/* PCI MSI 32-bit address register */ 240201052Smarius#define FO_PCI_MSI_32_BIT_ADDR_MASK 0x00000000ffff0000ULL 241201052Smarius#define FO_PCI_MSI_32_BIT_ADDR_SHFT 16 242201052Smarius 243201052Smarius/* PCI MSI 64-bit address register */ 244201052Smarius#define FO_PCI_MSI_64_BIT_ADDR_MASK 0x0000ffffffff0000ULL 245201052Smarius#define FO_PCI_MSI_64_BIT_ADDR_SHFT 16 246201052Smarius 247201052Smarius/* 248201052Smarius * PCI MMU interrupt enable, interrupt status and error status clear 249201052Smarius * registers 250201052Smarius */ 251201052Smarius#define FO_PCI_MMU_ERR_INT_S_MASK 0x0000ffff00000000ULL 252201052Smarius#define FO_PCI_MMU_ERR_INT_S_SHFT 32 253201052Smarius#define FO_PCI_MMU_ERR_INT_TBW_DPE_S 0x0000800000000000ULL 254201052Smarius#define FO_PCI_MMU_ERR_INT_TBW_ERR_S 0x0000400000000000ULL 255201052Smarius#define FO_PCI_MMU_ERR_INT_TBW_UDE_S 0x0000200000000000ULL 256201052Smarius#define FO_PCI_MMU_ERR_INT_TBW_DME_S 0x0000100000000000ULL 257201052Smarius#define FO_PCI_MMU_ERR_INT_SPARE3_S 0x0000080000000000ULL 258201052Smarius#define FO_PCI_MMU_ERR_INT_SPARE2_S 0x0000040000000000ULL 259201052Smarius#define FO_PCI_MMU_ERR_INT_TTC_CAE_S 0x0000020000000000ULL 260201052Smarius#define FIRE_PCI_MMU_ERR_INT_TTC_DPE_S 0x0000010000000000ULL 261201052Smarius#define OBERON_PCI_MMU_ERR_INT_TTC_DUE_S 0x0000010000000000ULL 262201052Smarius#define FO_PCI_MMU_ERR_INT_TTE_PRT_S 0x0000008000000000ULL 263201052Smarius#define FO_PCI_MMU_ERR_INT_TTE_INV_S 0x0000004000000000ULL 264201052Smarius#define FO_PCI_MMU_ERR_INT_TRN_OOR_S 0x0000002000000000ULL 265201052Smarius#define FO_PCI_MMU_ERR_INT_TRN_ERR_S 0x0000001000000000ULL 266201052Smarius#define FO_PCI_MMU_ERR_INT_SPARE1_S 0x0000000800000000ULL 267201052Smarius#define FO_PCI_MMU_ERR_INT_SPARE0_S 0x0000000400000000ULL 268201052Smarius#define FO_PCI_MMU_ERR_INT_BYP_OOR_S 0x0000000200000000ULL 269201052Smarius#define FO_PCI_MMU_ERR_INT_BYP_ERR_S 0x0000000100000000ULL 270201052Smarius#define FO_PCI_MMU_ERR_INT_P_MASK 0x000000000000ffffULL 271201052Smarius#define FO_PCI_MMU_ERR_INT_P_SHFT 0 272201052Smarius#define FO_PCI_MMU_ERR_INT_TBW_DPE_P 0x0000000000008000ULL 273201052Smarius#define FO_PCI_MMU_ERR_INT_TBW_ERR_P 0x0000000000004000ULL 274201052Smarius#define FO_PCI_MMU_ERR_INT_TBW_UDE_P 0x0000000000002000ULL 275201052Smarius#define FO_PCI_MMU_ERR_INT_TBW_DME_P 0x0000000000001000ULL 276201052Smarius#define FO_PCI_MMU_ERR_INT_SPARE3_P 0x0000000000000800ULL 277201052Smarius#define FO_PCI_MMU_ERR_INT_SPARE2_P 0x0000000000000400ULL 278201052Smarius#define FO_PCI_MMU_ERR_INT_TTC_CAE_P 0x0000000000000200ULL 279201052Smarius#define FIRE_PCI_MMU_ERR_INT_TTC_DPE_P 0x0000000000000100ULL 280201052Smarius#define OBERON_PCI_MMU_ERR_INT_TTC_DUE_P 0x0000000000000100ULL 281201052Smarius#define FO_PCI_MMU_ERR_INT_TTE_PRT_P 0x0000000000000080ULL 282201052Smarius#define FO_PCI_MMU_ERR_INT_TTE_INV_P 0x0000000000000040ULL 283201052Smarius#define FO_PCI_MMU_ERR_INT_TRN_OOR_P 0x0000000000000020ULL 284201052Smarius#define FO_PCI_MMU_ERR_INT_TRN_ERR_P 0x0000000000000010ULL 285201052Smarius#define FO_PCI_MMU_ERR_INT_SPARE1_P 0x0000000000000008ULL 286201052Smarius#define FO_PCI_MMU_ERR_INT_SPARE0_P 0x0000000000000004ULL 287201052Smarius#define FO_PCI_MMU_ERR_INT_BYP_OOR_P 0x0000000000000002ULL 288201052Smarius#define FO_PCI_MMU_ERR_INT_BYP_ERR_P 0x0000000000000001ULL 289201052Smarius 290201052Smarius/* PCI MMU translation fault address register */ 291201052Smarius#define FO_PCI_MMU_TRANS_FAULT_ADDR_VA_MASK 0xfffffffffffffffcULL 292201052Smarius#define FO_PCI_MMU_TRANS_FAULT_ADDR_VA_SHFT 2 293201052Smarius 294201052Smarius/* PCI MMU translation fault status register */ 295201052Smarius#define FO_PCI_MMU_TRANS_FAULT_STAT_ENTRY_MASK 0x000001ff00000000ULL 296201052Smarius#define FO_PCI_MMU_TRANS_FAULT_STAT_ENTRY_SHFT 32 297201052Smarius#define FO_PCI_MMU_TRANS_FAULT_STAT_TYPE_MASK 0x00000000007f0000ULL 298201052Smarius#define FO_PCI_MMU_TRANS_FAULT_STAT_TYPE_SHFT 16 299201052Smarius#define FO_PCI_MMU_TRANS_FAULT_STAT_ID_MASK 0x000000000000ffffULL 300201052Smarius#define FO_PCI_MMU_TRANS_FAULT_STAT_ID_SHFT 0 301201052Smarius 302201052Smarius/* 303201052Smarius * PCI ILU interrupt enable, interrupt status and error status clear 304201052Smarius * registers 305201052Smarius */ 306201052Smarius#define FO_PCI_ILU_ERR_INT_SPARE3_S 0x0000008000000000ULL 307201052Smarius#define FO_PCI_ILU_ERR_INT_SPARE2_S 0x0000004000000000ULL 308201052Smarius#define FO_PCI_ILU_ERR_INT_SPARE1_S 0x0000002000000000ULL 309201052Smarius#define FIRE_PCI_ILU_ERR_INT_IHB_PE_S 0x0000001000000000ULL 310201052Smarius#define OBERON_PCI_ILU_ERR_INT_IHB_UE_S 0x0000001000000000ULL 311201052Smarius#define FO_PCI_ILU_ERR_INT_SPARE3_P 0x0000000000000080ULL 312201052Smarius#define FO_PCI_ILU_ERR_INT_SPARE2_P 0x0000000000000040ULL 313201052Smarius#define FO_PCI_ILU_ERR_INT_SPARE1_P 0x0000000000000020ULL 314201052Smarius#define FIRE_PCI_ILU_ERR_INT_IHB_PE_P 0x0000000000000010ULL 315201052Smarius#define OBERON_PCI_ILU_ERR_INT_IHB_UE_P 0x0000000000000010ULL 316201052Smarius 317201052Smarius/* PCI DMC debug select registers for port a/b */ 318201052Smarius#define FO_PCI_DMC_DBG_SEL_PORT_BLCK_MASK 0x00000000000003c0ULL 319201052Smarius#define FO_PCI_DMC_DBG_SEL_PORT_BLCK_SHFT 6 320201052Smarius#define FO_PCI_DMC_DBG_SEL_PORT_SUB_MASK 0x0000000000000038ULL 321201052Smarius#define FO_PCI_DMC_DBG_SEL_PORT_SUB_SHFT 3 322201052Smarius#define FO_PCI_DMC_DBG_SEL_PORT_SUB_SGNL_MASK 0x0000000000000007ULL 323201052Smarius#define FO_PCI_DMC_DBG_SEL_PORT_SUB_SGNL_SHFT 0 324201052Smarius 325201052Smarius/* PCI PEC core and block interrupt enable register */ 326201052Smarius#define FO_PCI_PEC_CORE_BLOCK_INT_EN_PEC 0x8000000000000000ULL 327201052Smarius#define FO_PCI_PEC_CORE_BLOCK_INT_EN_ILU 0x0000000000000008ULL 328201052Smarius#define FO_PCI_PEC_CORE_BLOCK_INT_EN_UERR 0x0000000000000004ULL 329201052Smarius#define FO_PCI_PEC_CORE_BLOCK_INT_EN_CERR 0x0000000000000002ULL 330201052Smarius#define FO_PCI_PEC_CORE_BLOCK_INT_EN_OEVENT 0x0000000000000001ULL 331201052Smarius 332201052Smarius/* PCI PEC core and block interrupt status register */ 333201052Smarius#define FO_PCI_PEC_CORE_BLOCK_INT_STAT_ILU 0x0000000000000008ULL 334201052Smarius#define FO_PCI_PEC_CORE_BLOCK_INT_STAT_UERR 0x0000000000000004ULL 335201052Smarius#define FO_PCI_PEC_CORE_BLOCK_INT_STAT_CERR 0x0000000000000002ULL 336201052Smarius#define FO_PCI_PEC_CORE_BLOCK_INT_STAT_OEVENT 0x0000000000000001ULL 337201052Smarius 338201052Smarius/* PCI TLU control register */ 339201052Smarius#define FO_PCI_TLU_CTRL_L0S_TIM_MASK 0x00000000ff000000ULL 340201052Smarius#define FO_PCI_TLU_CTRL_L0S_TIM_SHFT 24 341201052Smarius#define FO_PCI_TLU_CTRL_NWPR_EN 0x0000000000100000ULL 342201052Smarius#define FO_PCI_TLU_CTRL_CTO_SEL_MASK 0x0000000000070000ULL 343201052Smarius#define FO_PCI_TLU_CTRL_CTO_SEL_SHFT 16 344201052Smarius#define FO_PCI_TLU_CTRL_CFG_MASK 0x000000000000ffffULL 345201052Smarius#define FO_PCI_TLU_CTRL_CFG_SHFT 0 346201052Smarius#define FO_PCI_TLU_CTRL_CFG_REMAIN_DETECT_QUIET 0x0000000000000100ULL 347233701Smarius#define FO_PCI_TLU_CTRL_CFG_PAD_LOOPBACK_EN 0x0000000000000080ULL 348233701Smarius#define FO_PCI_TLU_CTRL_CFG_EWRAP_LOOPBACK_EN 0x0000000000000040ULL 349233701Smarius#define FO_PCI_TLU_CTRL_CFG_DIGITAL_LOOPBACK_EN 0x0000000000000020ULL 350233701Smarius#define FO_PCI_TLU_CTRL_CFG_MPS_MASK 0x000000000000001cULL 351233701Smarius#define FO_PCI_TLU_CTRL_CFG_MPS_SHFT 2 352233701Smarius#define FO_PCI_TLU_CTRL_CFG_COMMON_CLK_CFG 0x0000000000000002ULL 353233701Smarius#define FO_PCI_TLU_CTRL_CFG_PORT 0x0000000000000001ULL 354201052Smarius 355201052Smarius/* 356201052Smarius * PCI TLU other event interrupt enable, interrupt status and status clear 357201052Smarius * registers 358201052Smarius */ 359201052Smarius#define FO_PCI_TLU_OEVENT_S_MASK 0x00ffffff00000000ULL 360201052Smarius#define FO_PCI_TLU_OEVENT_S_SHFT 32 361201052Smarius#define FO_PCI_TLU_OEVENT_SPARE_S 0x0080000000000000ULL 362201052Smarius#define FO_PCI_TLU_OEVENT_MFC_S 0x0040000000000000ULL 363201052Smarius#define FO_PCI_TLU_OEVENT_CTO_S 0x0020000000000000ULL 364201052Smarius#define FO_PCI_TLU_OEVENT_NFP_S 0x0010000000000000ULL 365201052Smarius#define FO_PCI_TLU_OEVENT_LWC_S 0x0008000000000000ULL 366201052Smarius#define FO_PCI_TLU_OEVENT_MRC_S 0x0004000000000000ULL 367201052Smarius#define FO_PCI_TLU_OEVENT_WUC_S 0x0002000000000000ULL 368201052Smarius#define FO_PCI_TLU_OEVENT_RUC_S 0x0001000000000000ULL 369201052Smarius#define FO_PCI_TLU_OEVENT_CRS_S 0x0000800000000000ULL 370201052Smarius#define FO_PCI_TLU_OEVENT_IIP_S 0x0000400000000000ULL 371201052Smarius#define FO_PCI_TLU_OEVENT_EDP_S 0x0000200000000000ULL 372201052Smarius#define FIRE_PCI_TLU_OEVENT_EHP_S 0x0000100000000000ULL 373201052Smarius#define OBERON_PCI_TLU_OEVENT_EHBUE_S 0x0000100000000000ULL 374201052Smarius#define OBERON_PCI_TLU_OEVENT_EDBUE_S 0x0000100000000000ULL 375201052Smarius#define FO_PCI_TLU_OEVENT_LIN_S 0x0000080000000000ULL 376201052Smarius#define FO_PCI_TLU_OEVENT_LRS_S 0x0000040000000000ULL 377201052Smarius#define FO_PCI_TLU_OEVENT_LDN_S 0x0000020000000000ULL 378201052Smarius#define FO_PCI_TLU_OEVENT_LUP_S 0x0000010000000000ULL 379201052Smarius#define FO_PCI_TLU_OEVENT_LPU_S_MASK 0x000000c000000000ULL 380201052Smarius#define FO_PCI_TLU_OEVENT_LPU_S_SHFT 38 381201052Smarius#define OBERON_PCI_TLU_OEVENT_TLUEITMO_S 0x0000008000000000ULL 382201052Smarius#define FO_PCI_TLU_OEVENT_ERU_S 0x0000002000000000ULL 383201052Smarius#define FO_PCI_TLU_OEVENT_ERO_S 0x0000001000000000ULL 384201052Smarius#define FO_PCI_TLU_OEVENT_EMP_S 0x0000000800000000ULL 385201052Smarius#define FO_PCI_TLU_OEVENT_EPE_S 0x0000000400000000ULL 386201052Smarius#define FIRE_PCI_TLU_OEVENT_ERP_S 0x0000000200000000ULL 387201052Smarius#define OBERON_PCI_TLU_OEVENT_ERBU_S 0x0000000200000000ULL 388201052Smarius#define FIRE_PCI_TLU_OEVENT_EIP_S 0x0000000100000000ULL 389201052Smarius#define OBERON_PCI_TLU_OEVENT_EIUE_S 0x0000000100000000ULL 390201052Smarius#define FO_PCI_TLU_OEVENT_P_MASK 0x0000000000ffffffULL 391201052Smarius#define FO_PCI_TLU_OEVENT_P_SHFT 0 392201052Smarius#define FO_PCI_TLU_OEVENT_SPARE_P 0x0000000000800000ULL 393201052Smarius#define FO_PCI_TLU_OEVENT_MFC_P 0x0000000000400000ULL 394201052Smarius#define FO_PCI_TLU_OEVENT_CTO_P 0x0000000000200000ULL 395201052Smarius#define FO_PCI_TLU_OEVENT_NFP_P 0x0000000000100000ULL 396201052Smarius#define FO_PCI_TLU_OEVENT_LWC_P 0x0000000000080000ULL 397201052Smarius#define FO_PCI_TLU_OEVENT_MRC_P 0x0000000000040000ULL 398201052Smarius#define FO_PCI_TLU_OEVENT_WUC_P 0x0000000000020000ULL 399201052Smarius#define FO_PCI_TLU_OEVENT_RUC_P 0x0000000000010000ULL 400201052Smarius#define FO_PCI_TLU_OEVENT_CRS_P 0x0000000000008000ULL 401201052Smarius#define FO_PCI_TLU_OEVENT_IIP_P 0x0000000000004000ULL 402201052Smarius#define FO_PCI_TLU_OEVENT_EDP_P 0x0000000000002000ULL 403201052Smarius#define FIRE_PCI_TLU_OEVENT_EHP_P 0x0000000000001000ULL 404201052Smarius#define OBERON_PCI_TLU_OEVENT_EHBUE_P 0x0000000000001000ULL 405201052Smarius#define OBERON_PCI_TLU_OEVENT_EDBUE_P 0x0000000000001000ULL 406201052Smarius#define FO_PCI_TLU_OEVENT_LIN_P 0x0000000000000800ULL 407201052Smarius#define FO_PCI_TLU_OEVENT_LRS_P 0x0000000000000400ULL 408201052Smarius#define FO_PCI_TLU_OEVENT_LDN_P 0x0000000000000200ULL 409201052Smarius#define FO_PCI_TLU_OEVENT_LUP_P 0x0000000000000100ULL 410201052Smarius#define FO_PCI_TLU_OEVENT_LPU_P_MASK 0x00000000000000c0ULL 411201052Smarius#define FO_PCI_TLU_OEVENT_LPU_P_SHFT 6 412201052Smarius#define OBERON_PCI_TLU_OEVENT_TLUEITMO_P 0x0000000000000080ULL 413201052Smarius#define FO_PCI_TLU_OEVENT_ERU_P 0x0000000000000020ULL 414201052Smarius#define FO_PCI_TLU_OEVENT_ERO_P 0x0000000000000010ULL 415201052Smarius#define FO_PCI_TLU_OEVENT_EMP_P 0x0000000000000008ULL 416201052Smarius#define FO_PCI_TLU_OEVENT_EPE_P 0x0000000000000004ULL 417201052Smarius#define FIRE_PCI_TLU_OEVENT_ERP_P 0x0000000000000002ULL 418201052Smarius#define OBERON_PCI_TLU_OEVENT_ERBU_P 0x0000000000000002ULL 419201052Smarius#define FIRE_PCI_TLU_OEVENT_EIP_P 0x0000000000000001ULL 420201052Smarius#define OBERON_PCI_TLU_OEVENT_EIUE_P 0x0000000000000001ULL 421201052Smarius 422201052Smarius/* PCI receive/transmit DLU/TLU other event header 1/2 log registers */ 423201052Smarius#define FO_PCI_TLU_OEVENT_HDR_LOG_MASK 0xffffffffffffffffULL 424201052Smarius#define FO_PCI_TLU_OEVENT_HDR_LOG_SHFT 0 425201052Smarius 426201052Smarius/* PCI TLU device control register */ 427201052Smarius#define FO_PCI_TLU_DEV_CTRL_MRRS_MASK 0x0000000000007000ULL 428201052Smarius#define FO_PCI_TLU_DEV_CTRL_MRRS_SHFT 12 429201052Smarius#define FO_PCI_TLU_DEV_CTRL_MPS_MASK 0x00000000000000e0ULL 430201052Smarius#define FO_PCI_TLU_DEV_CTRL_MPS_SHFT 5 431201052Smarius 432201052Smarius/* 433201052Smarius * PCI TLU uncorrectable error interrupt enable, interrupt status and 434201052Smarius * status clear registers 435201052Smarius */ 436201052Smarius#define FO_PCI_TLU_UERR_INT_S_MASK 0x001fffff00000000ULL 437201052Smarius#define FO_PCI_TLU_UERR_INT_S_SHFT 32 438201052Smarius#define FO_PCI_TLU_UERR_INT_UR_S 0x0010000000000000ULL 439201052Smarius#define OBERON_PCI_TLU_UERR_INT_ECRC_S 0x0008000000000000ULL 440201052Smarius#define FO_PCI_TLU_UERR_INT_MFP_S 0x0004000000000000ULL 441201052Smarius#define FO_PCI_TLU_UERR_INT_ROF_S 0x0002000000000000ULL 442201052Smarius#define FO_PCI_TLU_UERR_INT_UC_S 0x0001000000000000ULL 443201052Smarius#define FO_PCI_TLU_UERR_INT_CA_S 0x0000800000000000ULL 444201052Smarius#define FO_PCI_TLU_UERR_INT_CTO_S 0x0000400000000000ULL 445201052Smarius#define FO_PCI_TLU_UERR_INT_FCP_S 0x0000200000000000ULL 446201052Smarius#define FIRE_PCI_TLU_UERR_INT_PP_S 0x0000100000000000ULL 447201052Smarius#define OBERON_PCI_TLU_UERR_INT_POIS_S 0x0000100000000000ULL 448201052Smarius#define FO_PCI_TLU_UERR_INT_DLP_S 0x0000001000000000ULL 449201052Smarius#define FO_PCI_TLU_UERR_INT_TE_S 0x0000000100000000ULL 450201052Smarius#define FO_PCI_TLU_UERR_INT_P_MASK 0x00000000001fffffULL 451201052Smarius#define FO_PCI_TLU_UERR_INT_P_SHFT 0 452201052Smarius#define FO_PCI_TLU_UERR_INT_UR_P 0x0000000000100000ULL 453201052Smarius#define OBERON_PCI_TLU_UERR_INT_ECRC_P 0x0000000000080000ULL 454201052Smarius#define FO_PCI_TLU_UERR_INT_MFP_P 0x0000000000040000ULL 455201052Smarius#define FO_PCI_TLU_UERR_INT_ROF_P 0x0000000000020000ULL 456201052Smarius#define FO_PCI_TLU_UERR_INT_UC_P 0x0000000000010000ULL 457201052Smarius#define FO_PCI_TLU_UERR_INT_CA_P 0x0000000000008000ULL 458201052Smarius#define FO_PCI_TLU_UERR_INT_CTO_P 0x0000000000004000ULL 459201052Smarius#define FO_PCI_TLU_UERR_INT_FCP_P 0x0000000000002000ULL 460201052Smarius#define FIRE_PCI_TLU_UERR_INT_PP_P 0x0000000000001000ULL 461201052Smarius#define OBERON_PCI_TLU_UERR_INT_POIS_P 0x0000000000001000ULL 462201052Smarius#define FO_PCI_TLU_UERR_INT_DLP_P 0x0000000000000010ULL 463201052Smarius#define FO_PCI_TLU_UERR_INT_TE_P 0x0000000000000001ULL 464201052Smarius 465201052Smarius/* 466201052Smarius * PCI TLU correctable error interrupt enable, interrupt status and 467201052Smarius * status clear registers 468201052Smarius */ 469201052Smarius#define FO_PCI_TLU_CERR_INT_S_MASK 0x001fffff00000000ULL 470201052Smarius#define FO_PCI_TLU_CERR_INT_S_SHFT 32 471201052Smarius#define FO_PCI_TLU_CERR_INT_RTO_S 0x0000100000000000ULL 472201052Smarius#define FO_PCI_TLU_CERR_INT_RNR_S 0x0000010000000000ULL 473201052Smarius#define FO_PCI_TLU_CERR_INT_BDP_S 0x0000008000000000ULL 474201052Smarius#define FO_PCI_TLU_CERR_INT_BTP_S 0x0000004000000000ULL 475201052Smarius#define FO_PCI_TLU_CERR_INT_RE_S 0x0000000100000000ULL 476201052Smarius#define FO_PCI_TLU_CERR_INT_P_MASK 0x00000000001fffffULL 477201052Smarius#define FO_PCI_TLU_CERR_INT_P_SHFT 0 478201052Smarius#define FO_PCI_TLU_CERR_INT_RTO_P 0x0000000000001000ULL 479201052Smarius#define FO_PCI_TLU_CERR_INT_RNR_P 0x0000000000000100ULL 480201052Smarius#define FO_PCI_TLU_CERR_INT_BDP_P 0x0000000000000080ULL 481201052Smarius#define FO_PCI_TLU_CERR_INT_BTP_P 0x0000000000000040ULL 482201052Smarius#define FO_PCI_TLU_CERR_INT_RE_P 0x0000000000000001ULL 483201052Smarius 484201052Smarius/* PCI TLU reset register */ 485201052Smarius#define FO_PCI_LPU_RST_WE 0x0000000080000000ULL 486201052Smarius#define FO_PCI_LPU_RST_UNUSED_MASK 0x0000000000000e00ULL 487201052Smarius#define FO_PCI_LPU_RST_UNUSED_SHFT 9 488201052Smarius#define FO_PCI_LPU_RST_ERR 0x0000000000000100ULL 489201052Smarius#define FO_PCI_LPU_RST_TXLINK 0x0000000000000080ULL 490201052Smarius#define FO_PCI_LPU_RST_RXLINK 0x0000000000000040ULL 491201052Smarius#define FO_PCI_LPU_RST_SMLINK 0x0000000000000020ULL 492201052Smarius#define FO_PCI_LPU_RST_LTSSM 0x0000000000000010ULL 493201052Smarius#define FO_PCI_LPU_RST_TXPHY 0x0000000000000008ULL 494201052Smarius#define FO_PCI_LPU_RST_RXPHY 0x0000000000000004ULL 495201052Smarius#define FO_PCI_LPU_RST_TXPCS 0x0000000000000002ULL 496201052Smarius#define FO_PCI_LPU_RST_RXPCS 0x0000000000000001ULL 497201052Smarius 498201052Smarius/* PCI TLU link control register */ 499201052Smarius#define FO_PCI_TLU_LNK_CTRL_EXTSYNC 0x0000000000000080ULL 500201052Smarius#define FO_PCI_TLU_LNK_CTRL_CLK 0x0000000000000040ULL 501201052Smarius#define FO_PCI_TLU_LNK_CTRL_RETRAIN 0x0000000000000020ULL 502201052Smarius#define FO_PCI_TLU_LNK_CTRL_DIS 0x0000000000000010ULL 503201052Smarius#define FO_PCI_TLU_LNK_CTRL_RCB 0x0000000000000008ULL 504201052Smarius#define FO_PCI_TLU_LNK_CTRL_ASPM_L0S_L1S 0x0000000000000003ULL 505201052Smarius#define FO_PCI_TLU_LNK_CTRL_ASPM_L1S 0x0000000000000002ULL 506201052Smarius#define FO_PCI_TLU_LNK_CTRL_ASPM_L0S 0x0000000000000001ULL 507201052Smarius#define FO_PCI_TLU_LNK_CTRL_ASPM_DIS 0x0000000000000000ULL 508201052Smarius 509201052Smarius/* PCI TLU link status register */ 510201052Smarius#define FO_PCI_TLU_LNK_STAT_CLK 0x0000000000001000ULL 511201052Smarius#define FO_PCI_TLU_LNK_STAT_TRAIN 0x0000000000000800ULL 512201052Smarius#define FO_PCI_TLU_LNK_STAT_ERR 0x0000000000000400ULL 513201052Smarius#define FO_PCI_TLU_LNK_STAT_WDTH_MASK 0x00000000000003f0ULL 514201052Smarius#define FO_PCI_TLU_LNK_STAT_WDTH_SHFT 4 515201052Smarius#define FO_PCI_TLU_LNK_STAT_SPEED_MASK 0x000000000000000fULL 516201052Smarius#define FO_PCI_TLU_LNK_STAT_SPEED_SHFT 0 517201052Smarius 518201052Smarius/* 519201052Smarius * PCI receive/transmit DLU/TLU uncorrectable error header 1/2 log 520201052Smarius * registers 521201052Smarius */ 522201052Smarius#define FO_PCI_TLU_UERR_HDR_LOG_MASK 0xffffffffffffffffULL 523201052Smarius#define FO_PCI_TLU_UERR_HDR_LOG_SHFT 0 524201052Smarius 525201052Smarius/* PCI DLU/LPU interrupt status and mask registers */ 526201052Smarius#define FO_PCI_LPU_INT_INT 0x0000000080000000ULL 527201052Smarius#define FIRE_PCI_LPU_INT_PRF_CNT2_OFLW 0x0000000000000080ULL 528201052Smarius#define FIRE_PCI_LPU_INT_PRF_CNT1_OFLW 0x0000000000000040ULL 529201052Smarius#define FO_PCI_LPU_INT_LNK_LYR 0x0000000000000020ULL 530201052Smarius#define FO_PCI_LPU_INT_PHY_ERR 0x0000000000000010ULL 531201052Smarius#define FIRE_PCI_LPU_INT_LTSSM 0x0000000000000008ULL 532201052Smarius#define FIRE_PCI_LPU_INT_PHY_TX 0x0000000000000004ULL 533201052Smarius#define FIRE_PCI_LPU_INT_PHY_RX 0x0000000000000002ULL 534201052Smarius#define FIRE_PCI_LPU_INT_PHY_GB 0x0000000000000001ULL 535201052Smarius 536201052Smarius/* PCI DLU/LPU link layer config register */ 537201052Smarius#define FIRE_PCI_LPU_LNK_LYR_CFG_AUTO_UPDT_DIS 0x0000000000080000ULL 538201052Smarius#define FIRE_PCI_LPU_LNK_LYR_CFG_FREQ_NAK_EN 0x0000000000040000ULL 539201052Smarius#define FIRE_PCI_LPU_LNK_LYR_CFG_RPLY_AFTER_REQ 0x0000000000020000ULL 540201052Smarius#define FIRE_PCI_LPU_LNK_LYR_CFG_LAT_THRS_WR_EN 0x0000000000010000ULL 541201052Smarius#define FO_PCI_LPU_LNK_LYR_CFG_VC0_EN 0x0000000000000100ULL 542201052Smarius#define FIRE_PCI_LPU_LNK_LYR_CFG_L0S_ADJ_FAC_EN 0x0000000000000010ULL 543201052Smarius#define FIER_PCI_LPU_LNK_LYR_CFG_TLP_XMIT_FC_EN 0x0000000000000008ULL 544201052Smarius#define FO_PCI_LPU_LNK_LYR_CFG_FREQ_ACK_EN 0x0000000000000004ULL 545201052Smarius#define FO_PCI_LPU_LNK_LYR_CFG_RETRY_DIS 0x0000000000000002ULL 546201052Smarius 547201052Smarius/* PCI DLU/LPU link layer interrupt and status register */ 548201052Smarius#define FO_PCI_LPU_LNK_LYR_INT_STAT_LNK_ERR_ACT 0x0000000080000000ULL 549201052Smarius#define OBERON_PCI_LPU_LNK_LYR_INT_STAT_PBUS_PE 0x0000000000800000ULL 550201052Smarius#define FO_PCI_LPU_LNK_LYR_INT_STAT_USPRTD_DLLP 0x0000000000400000ULL 551201052Smarius#define FO_PCI_LPU_LNK_LYR_INT_STAT_DLLP_RX_ERR 0x0000000000200000ULL 552201052Smarius#define FO_PCI_LPU_LNK_LYR_INT_STAT_BAD_DLLP 0x0000000000100000ULL 553201052Smarius#define FO_PCI_LPU_LNK_LYR_INT_STAT_TLP_RX_ERR 0x0000000000040000ULL 554201052Smarius#define FO_PCI_LPU_LNK_LYR_INT_STAT_SRC_ERR_TLP 0x0000000000020000ULL 555201052Smarius#define FO_PCI_LPU_LNK_LYR_INT_STAT_BAD_TLP 0x0000000000010000ULL 556201052Smarius#define FO_PCI_LPU_LNK_LYR_INT_STAT_RBF_UDF_ERR 0x0000000000000200ULL 557201052Smarius#define FO_PCI_LPU_LNK_LYR_INT_STAT_RBF_OVF_ERR 0x0000000000000100ULL 558201052Smarius#define FO_PCI_LPU_LNK_LYR_INT_STAT_EG_TLPM_ERR 0x0000000000000080ULL 559201052Smarius#define FO_PCI_LPU_LNK_LYR_INT_STAT_EG_TFRM_ERR 0x0000000000000040ULL 560201052Smarius#define FO_PCI_LPU_LNK_LYR_INT_STAT_RBF_PE 0x0000000000000020ULL 561201052Smarius#define FO_PCI_LPU_LNK_LYR_INT_STAT_EGRESS_PE 0x0000000000000010ULL 562201052Smarius#define FO_PCI_LPU_LNK_LYR_INT_STAT_RPLY_TMR_TO 0x0000000000000004ULL 563201052Smarius#define FO_PCI_LPU_LNK_LYR_INT_STAT_RPLY_NUM_RO 0x0000000000000002ULL 564201052Smarius#define FO_PCI_LPU_LNK_LYR_INT_STAT_DLNK_PES 0x0000000000000001ULL 565201052Smarius 566201052Smarius/* PCI DLU/LPU flow control update control register */ 567201052Smarius#define FO_PCI_LPU_FLW_CTRL_UPDT_CTRL_FC0_C_EN 0x0000000000000004ULL 568201052Smarius#define FO_PCI_LPU_FLW_CTRL_UPDT_CTRL_FC0_NP_EN 0x0000000000000002ULL 569201052Smarius#define FO_PCI_LPU_FLW_CTRL_UPDT_CTRL_FC0_P_EN 0x0000000000000001ULL 570201052Smarius 571201052Smarius/* PCI DLU/LPU txlink ACKNAK latency timer threshold register */ 572201052Smarius#define FO_PCI_LPU_TXLNK_FREQ_LAT_TMR_THRS_MASK 0x000000000000ffffULL 573201052Smarius#define FO_PCI_LPU_TXLNK_FREQ_LAT_TMR_THRS_SHFT 0 574201052Smarius 575201052Smarius/* PCI DLU/LPU txlink replay timer threshold register */ 576201052Smarius#define FO_PCI_LPU_TXLNK_RPLY_TMR_THRS_MASK 0x00000000000fffffULL 577201052Smarius#define FO_PCI_LPU_TXLNK_RPLY_TMR_THRS_SHFT 0 578201052Smarius 579201052Smarius/* PCI DLU/LPU txlink FIFO pointer register */ 580201052Smarius#define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR_TL_MASK 0x00000000ffff0000ULL 581201052Smarius#define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR_TL_SHFT 16 582201052Smarius#define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR_HD_MASK 0x000000000000ffffULL 583201052Smarius#define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR_HD_SHFT 0 584201052Smarius 585201052Smarius/* PCI DLU/LPU phy layer interrupt and status register */ 586201052Smarius#define FO_PCI_LPU_PHY_LYR_INT_STAT_PHY_LYR_ERR 0x0000000080000000ULL 587201052Smarius#define FO_PCI_LPU_PHY_LYR_INT_STAT_KC_DLLP_ERR 0x0000000000000800ULL 588201052Smarius#define FO_PCI_LPU_PHY_LYR_INT_STAT_END_POS_ERR 0x0000000000000400ULL 589201052Smarius#define FO_PCI_LPU_PHY_LYR_INT_STAT_LNK_ERR 0x0000000000000200ULL 590201052Smarius#define FO_PCI_LPU_PHY_LYR_INT_STAT_TRN_ERR 0x0000000000000100ULL 591201052Smarius#define FO_PCI_LPU_PHY_LYR_INT_STAT_EDB_DET 0x0000000000000080ULL 592201052Smarius#define FO_PCI_LPU_PHY_LYR_INT_STAT_SDP_END 0x0000000000000040ULL 593201052Smarius#define FO_PCI_LPU_PHY_LYR_INT_STAT_STP_END_EDB 0x0000000000000020ULL 594201052Smarius#define FO_PCI_LPU_PHY_LYR_INT_STAT_INVC_ERR 0x0000000000000010ULL 595201052Smarius#define FO_PCI_LPU_PHY_LYR_INT_STAT_MULTI_SDP 0x0000000000000008ULL 596201052Smarius#define FO_PCI_LPU_PHY_LYR_INT_STAT_MULTI_STP 0x0000000000000004ULL 597201052Smarius#define FO_PCI_LPU_PHY_LYR_INT_STAT_ILL_SDP_POS 0x0000000000000002ULL 598201052Smarius#define FO_PCI_LPU_PHY_LYR_INT_STAT_ILL_STP_POS 0x0000000000000001ULL 599201052Smarius 600201052Smarius/* PCI DLU/LPU LTSSM config2 register */ 601201052Smarius#define FO_PCI_LPU_LTSSM_CFG2_12_TO_MASK 0x00000000ffffffffULL 602201052Smarius#define FO_PCI_LPU_LTSSM_CFG2_12_TO_SHFT 0 603201052Smarius 604201052Smarius/* PCI DLU/LPU LTSSM config3 register */ 605201052Smarius#define FO_PCI_LPU_LTSSM_CFG3_2_TO_MASK 0x00000000ffffffffULL 606201052Smarius#define FO_PCI_LPU_LTSSM_CFG3_2_TO_SHFT 0 607201052Smarius 608201052Smarius/* PCI DLU/LPU LTSSM config4 register */ 609201052Smarius#define FO_PCI_LPU_LTSSM_CFG4_TRN_CTRL_MASK 0x00000000ff000000ULL 610201052Smarius#define FO_PCI_LPU_LTSSM_CFG4_TRN_CTRL_SHFT 24 611201052Smarius#define FO_PCI_LPU_LTSSM_CFG4_DATA_RATE_MASK 0x0000000000ff0000ULL 612201052Smarius#define FO_PCI_LPU_LTSSM_CFG4_DATA_RATE_SHFT 16 613201052Smarius#define FO_PCI_LPU_LTSSM_CFG4_N_FTS_MASK 0x000000000000ff00ULL 614201052Smarius#define FO_PCI_LPU_LTSSM_CFG4_N_FTS_SHFT 8 615201052Smarius#define FO_PCI_LPU_LTSSM_CFG4_LNK_NUM_MASK 0x00000000000000ffULL 616201052Smarius#define FO_PCI_LPU_LTSSM_CFG4_LNK_NUM_SHFT 0 617201052Smarius 618201052Smarius/* PCI DLU/LPU LTSSM config5 register */ 619201052Smarius#define FO_PCI_LPU_LTSSM_CFG5_UNUSED0_MASK 0x00000000ffffe000ULL 620201052Smarius#define FO_PCI_LPU_LTSSM_CFG5_UNUSED0_SHFT 13 621201052Smarius#define FO_PCI_LPU_LTSSM_CFG5_RCV_DET_TST_MODE 0x0000000000001000ULL 622201052Smarius#define FO_PCI_LPU_LTSSM_CFG5_POLL_CMPLNC_DIS 0x0000000000000800ULL 623201052Smarius#define FO_PCI_LPU_LTSSM_CFG5_TX_IDLE_TX_FTS 0x0000000000000400ULL 624201052Smarius#define FO_PCI_LPU_LTSSM_CFG5_RX_FTS_RVR_LK 0x0000000000000200ULL 625201052Smarius#define FO_PCI_LPU_LTSSM_CFG5_UNUSED1_MASK 0x0000000000000180ULL 626201052Smarius#define FO_PCI_LPU_LTSSM_CFG5_UNUSED1_SHFT 7 627201052Smarius#define FO_PCI_LPU_LTSSM_CFG5_LPBK_NTRY_ACTIVE 0x0000000000000040ULL 628201052Smarius#define FO_PCI_LPU_LTSSM_CFG5_LPBK_NTRY_EXIT 0x0000000000000020ULL 629201052Smarius#define FO_PCI_LPU_LTSSM_CFG5_LPBK_ACTIVE_EXIT 0x0000000000000010ULL 630201052Smarius#define FO_PCI_LPU_LTSSM_CFG5_L1_IDLE_RCVRY_LK 0x0000000000000008ULL 631201052Smarius#define FO_PCI_LPU_LTSSM_CFG5_L0_TRN_CNTRL_RST 0x0000000000000004ULL 632201052Smarius#define FO_PCI_LPU_LTSSM_CFG5_L0_LPBK 0x0000000000000002ULL 633201052Smarius#define FO_PCI_LPU_LTSSM_CFG5_UNUSED2 0x0000000000000001ULL 634201052Smarius 635201052Smarius/* Controller configuration and status registers */ 636201052Smarius#define FIRE_JBUS_PAR_CTRL 0x60010 637201052Smarius#define FO_XBC_ERR_LOG_EN 0x61000 638201052Smarius#define FO_XBC_INT_EN 0x61008 639201052Smarius#define FO_XBC_INT_STAT 0x61010 640201052Smarius#define FO_XBC_ERR_STAT_CLR 0x61018 641201052Smarius#define FIRE_JBC_FATAL_RST_EN 0x61028 642201052Smarius#define FIRE_JBCINT_ITRANS_ERR_LOG 0x61040 643201052Smarius#define FIRE_JBCINT_ITRANS_ERR_LOG2 0x61048 644201052Smarius#define FIRE_JBCINT_OTRANS_ERR_LOG 0x61040 645201052Smarius#define FIRE_JBCINT_OTRANS_ERR_LOG2 0x61048 646201052Smarius#define FIRE_FATAL_ERR_LOG 0x61050 647201052Smarius#define FIRE_FATAL_ERR_LOG2 0x61058 648201052Smarius#define FIRE_MERGE_TRANS_ERR_LOG 0x61060 649201052Smarius#define FIRE_DMCINT_ODCD_ERR_LOG 0x61068 650201052Smarius#define FIRE_DMCINT_IDC_ERR_LOG 0x61070 651201052Smarius#define FIRE_JBC_CSR_ERR_LOG 0x61078 652201052Smarius#define FIRE_JBC_CORE_BLOCK_INT_EN 0x61800 653201052Smarius#define FIRE_JBC_CORE_BLOCK_ERR_STAT 0x61808 654201052Smarius#define FO_XBC_PRF_CNT_SEL 0x62000 655201052Smarius#define FO_XBC_PRF_CNT0 0x62008 656201052Smarius#define FO_XBC_PRF_CNT1 0x62010 657201052Smarius 658201052Smarius/* JBus parity control register */ 659201052Smarius#define FIRE_JBUS_PAR_CTRL_P_EN 0x8000000000000000ULL 660201052Smarius#define FIRE_JBUS_PAR_CTRL_INVRTD_PAR_MASK 0x000000000000003cULL 661201052Smarius#define FIRE_JBUS_PAR_CTRL_INVRTD_PAR_SHFT 2 662201052Smarius#define FIRE_JBUS_PAR_CTRL_NEXT_DATA 0x0000000000000002ULL 663201052Smarius#define FIRE_JBUS_PAR_CTRL_NEXT_ADDR 0x0000000000000001ULL 664201052Smarius 665201052Smarius/* JBC error log enable register - may also apply to UBC */ 666201052Smarius#define FIRE_JBC_ERR_LOG_EN_SPARE_MASK 0x00000000e0000000ULL 667201052Smarius#define FIRE_JBC_ERR_LOG_EN_SPARE_SHFT 29 668201052Smarius#define FIRE_JBC_ERR_LOG_EN_PIO_UNMAP_RD 0x0000000010000000ULL 669201052Smarius#define FIRE_JBC_ERR_LOG_EN_ILL_ACC_RD 0x0000000008000000ULL 670201052Smarius#define FIRE_JBC_ERR_LOG_EN_EBUS_TO 0x0000000004000000ULL 671201052Smarius#define FIRE_JBC_ERR_LOG_EN_MB_PEA 0x0000000002000000ULL 672201052Smarius#define FIRE_JBC_ERR_LOG_EN_MB_PER 0x0000000001000000ULL 673201052Smarius#define FIRE_JBC_ERR_LOG_EN_MB_PEW 0x0000000000800000ULL 674201052Smarius#define FIRE_JBC_ERR_LOG_EN_UE_ASYN 0x0000000000400000ULL 675201052Smarius#define FIRE_JBC_ERR_LOG_EN_CE_ASYN 0x0000000000200000ULL 676201052Smarius#define FIRE_JBC_ERR_LOG_EN_JTE 0x0000000000100000ULL 677201052Smarius#define FIRE_JBC_ERR_LOG_EN_JBE 0x0000000000080000ULL 678201052Smarius#define FIRE_JBC_ERR_LOG_EN_JUE 0x0000000000040000ULL 679201052Smarius#define FIRE_JBC_ERR_LOG_EN_IJP 0x0000000000020000ULL 680201052Smarius#define FIRE_JBC_ERR_LOG_EN_ICISE 0x0000000000010000ULL 681201052Smarius#define FIRE_JBC_ERR_LOG_EN_CPE 0x0000000000008000ULL 682201052Smarius#define FIRE_JBC_ERR_LOG_EN_APE 0x0000000000004000ULL 683201052Smarius#define FIRE_JBC_ERR_LOG_EN_WR_DPE 0x0000000000002000ULL 684201052Smarius#define FIRE_JBC_ERR_LOG_EN_RD_DPE 0x0000000000001000ULL 685201052Smarius#define FIRE_JBC_ERR_LOG_EN_ILL_BMW 0x0000000000000800ULL 686201052Smarius#define FIRE_JBC_ERR_LOG_EN_ILL_BMR 0x0000000000000400ULL 687201052Smarius#define FIRE_JBC_ERR_LOG_EN_BJC 0x0000000000000200ULL 688201052Smarius#define FIRE_JBC_ERR_LOG_EN_PIO_UNMAP 0x0000000000000100ULL 689201052Smarius#define FIRE_JBC_ERR_LOG_EN_PIO_DPE 0x0000000000000080ULL 690201052Smarius#define FIRE_JBC_ERR_LOG_EN_PIO_CPE 0x0000000000000040ULL 691201052Smarius#define FIRE_JBC_ERR_LOG_EN_ILL_ACC 0x0000000000000020ULL 692201052Smarius#define FIRE_JBC_ERR_LOG_EN_UNSOL_RD 0x0000000000000010ULL 693201052Smarius#define FIRE_JBC_ERR_LOG_EN_UNSOL_INT 0x0000000000000008ULL 694201052Smarius#define FIRE_JBC_ERR_LOG_EN_JTCEEW 0x0000000000000004ULL 695201052Smarius#define FIRE_JBC_ERR_LOG_EN_JTCEEI 0x0000000000000002ULL 696201052Smarius#define FIRE_JBC_ERR_LOG_EN_JTCEER 0x0000000000000001ULL 697201052Smarius 698201052Smarius/* JBC interrupt enable, interrupt status and error status clear registers */ 699201052Smarius#define FIRE_JBC_ERR_INT_SPARE_S_MASK 0xe000000000000000ULL 700201052Smarius#define FIRE_JBC_ERR_INT_SPARE_S_SHFT 61 701201052Smarius#define FIRE_JBC_ERR_INT_PIO_UNMAP_RD_S 0x1000000000000000ULL 702201052Smarius#define FIRE_JBC_ERR_INT_ILL_ACC_RD_S 0x0800000000000000ULL 703201052Smarius#define FIRE_JBC_ERR_INT_EBUS_TO_S 0x0400000000000000ULL 704201052Smarius#define FIRE_JBC_ERR_INT_MB_PEA_S 0x0200000000000000ULL 705201052Smarius#define FIRE_JBC_ERR_INT_MB_PER_S 0x0100000000000000ULL 706201052Smarius#define FIRE_JBC_ERR_INT_MB_PEW_S 0x0080000000000000ULL 707201052Smarius#define FIRE_JBC_ERR_INT_UE_ASYN_S 0x0040000000000000ULL 708201052Smarius#define FIRE_JBC_ERR_INT_CE_ASYN_S 0x0020000000000000ULL 709201052Smarius#define FIRE_JBC_ERR_INT_JTE_S 0x0010000000000000ULL 710201052Smarius#define FIRE_JBC_ERR_INT_JBE_S 0x0008000000000000ULL 711201052Smarius#define FIRE_JBC_ERR_INT_JUE_S 0x0004000000000000ULL 712201052Smarius#define FIRE_JBC_ERR_INT_IJP_S 0x0002000000000000ULL 713201052Smarius#define FIRE_JBC_ERR_INT_ICISE_S 0x0001000000000000ULL 714201052Smarius#define FIRE_JBC_ERR_INT_CPE_S 0x0000800000000000ULL 715201052Smarius#define FIRE_JBC_ERR_INT_APE_S 0x0000400000000000ULL 716201052Smarius#define FIRE_JBC_ERR_INT_WR_DPE_S 0x0000200000000000ULL 717201052Smarius#define FIRE_JBC_ERR_INT_RD_DPE_S 0x0000100000000000ULL 718201052Smarius#define FIRE_JBC_ERR_INT_ILL_BMW_S 0x0000080000000000ULL 719201052Smarius#define FIRE_JBC_ERR_INT_ILL_BMR_S 0x0000040000000000ULL 720201052Smarius#define FIRE_JBC_ERR_INT_BJC_S 0x0000020000000000ULL 721201052Smarius#define FIRE_JBC_ERR_INT_PIO_UNMAP_S 0x0000010000000000ULL 722201052Smarius#define FIRE_JBC_ERR_INT_PIO_DPE_S 0x0000008000000000ULL 723201052Smarius#define FIRE_JBC_ERR_INT_PIO_CPE_S 0x0000004000000000ULL 724201052Smarius#define FIRE_JBC_ERR_INT_ILL_ACC_S 0x0000002000000000ULL 725201052Smarius#define FIRE_JBC_ERR_INT_UNSOL_RD_S 0x0000001000000000ULL 726201052Smarius#define FIRE_JBC_ERR_INT_UNSOL_INT_S 0x0000000800000000ULL 727201052Smarius#define FIRE_JBC_ERR_INT_JTCEEW_S 0x0000000400000000ULL 728201052Smarius#define FIRE_JBC_ERR_INT_JTCEEI_S 0x0000000200000000ULL 729201052Smarius#define FIRE_JBC_ERR_INT_JTCEER_S 0x0000000100000000ULL 730201052Smarius#define FIRE_JBC_ERR_INT_SPARE_P_MASK 0x00000000e0000000ULL 731201052Smarius#define FIRE_JBC_ERR_INT_SPARE_P_SHFT 29 732201052Smarius#define FIRE_JBC_ERR_INT_PIO_UNMAP_RD_P 0x0000000010000000ULL 733201052Smarius#define FIRE_JBC_ERR_INT_ILL_ACC_RD_P 0x0000000008000000ULL 734201052Smarius#define FIRE_JBC_ERR_INT_EBUS_TO_P 0x0000000004000000ULL 735201052Smarius#define FIRE_JBC_ERR_INT_MB_PEA_P 0x0000000002000000ULL 736201052Smarius#define FIRE_JBC_ERR_INT_MB_PER_P 0x0000000001000000ULL 737201052Smarius#define FIRE_JBC_ERR_INT_MB_PEW_P 0x0000000000800000ULL 738201052Smarius#define FIRE_JBC_ERR_INT_UE_ASYN_P 0x0000000000400000ULL 739201052Smarius#define FIRE_JBC_ERR_INT_CE_ASYN_P 0x0000000000200000ULL 740201052Smarius#define FIRE_JBC_ERR_INT_JTE_P 0x0000000000100000ULL 741201052Smarius#define FIRE_JBC_ERR_INT_JBE_P 0x0000000000080000ULL 742201052Smarius#define FIRE_JBC_ERR_INT_JUE_P 0x0000000000040000ULL 743201052Smarius#define FIRE_JBC_ERR_INT_IJP_P 0x0000000000020000ULL 744201052Smarius#define FIRE_JBC_ERR_INT_ICISE_P 0x0000000000010000ULL 745201052Smarius#define FIRE_JBC_ERR_INT_CPE_P 0x0000000000008000ULL 746201052Smarius#define FIRE_JBC_ERR_INT_APE_P 0x0000000000004000ULL 747201052Smarius#define FIRE_JBC_ERR_INT_WR_DPE_P 0x0000000000002000ULL 748201052Smarius#define FIRE_JBC_ERR_INT_RD_DPE_P 0x0000000000001000ULL 749201052Smarius#define FIRE_JBC_ERR_INT_ILL_BMW_P 0x0000000000000800ULL 750201052Smarius#define FIRE_JBC_ERR_INT_ILL_BMR_P 0x0000000000000400ULL 751201052Smarius#define FIRE_JBC_ERR_INT_BJC_P 0x0000000000000200ULL 752201052Smarius#define FIRE_JBC_ERR_INT_PIO_UNMAP_P 0x0000000000000100ULL 753201052Smarius#define FIRE_JBC_ERR_INT_PIO_DPE_P 0x0000000000000080ULL 754201052Smarius#define FIRE_JBC_ERR_INT_PIO_CPE_P 0x0000000000000040ULL 755201052Smarius#define FIRE_JBC_ERR_INT_ILL_ACC_P 0x0000000000000020ULL 756201052Smarius#define FIRE_JBC_ERR_INT_UNSOL_RD_P 0x0000000000000010ULL 757201052Smarius#define FIRE_JBC_ERR_INT_UNSOL_INT_P 0x0000000000000008ULL 758201052Smarius#define FIRE_JBC_ERR_INT_JTCEEW_P 0x0000000000000004ULL 759201052Smarius#define FIRE_JBC_ERR_INT_JTCEEI_P 0x0000000000000002ULL 760201052Smarius#define FIRE_JBC_ERR_INT_JTCEER_P 0x0000000000000001ULL 761201052Smarius 762201052Smarius/* UBC interrupt enable, error status and error status clear registers */ 763201052Smarius#define OBERON_UBC_ERR_INT_PIORBEUE_S 0x0004000000000000ULL 764201052Smarius#define OBERON_UBC_ERR_INT_PIOWBEUE_S 0x0002000000000000ULL 765201052Smarius#define OBERON_UBC_ERR_INT_PIOWTUE_S 0x0001000000000000ULL 766201052Smarius#define OBERON_UBC_ERR_INT_MEMWTAXB_S 0x0000080000000000ULL 767201052Smarius#define OBERON_UBC_ERR_INT_MEMRDAXB_S 0x0000040000000000ULL 768201052Smarius#define OBERON_UBC_ERR_INT_DMAWTUEB_S 0x0000020000000000ULL 769201052Smarius#define OBERON_UBC_ERR_INT_DMARDUEB_S 0x0000010000000000ULL 770201052Smarius#define OBERON_UBC_ERR_INT_MEMWTAXA_S 0x0000000800000000ULL 771201052Smarius#define OBERON_UBC_ERR_INT_MEMRDAXA_S 0x0000000400000000ULL 772201052Smarius#define OBERON_UBC_ERR_INT_DMAWTUEA_S 0x0000000200000000ULL 773201052Smarius#define OBERON_UBC_ERR_INT_DMARDUEA_S 0x0000000100000000ULL 774201052Smarius#define OBERON_UBC_ERR_INT_PIORBEUE_P 0x0000000000040000ULL 775201052Smarius#define OBERON_UBC_ERR_INT_PIOWBEUE_P 0x0000000000020000ULL 776201052Smarius#define OBERON_UBC_ERR_INT_PIOWTUE_P 0x0000000000010000ULL 777201052Smarius#define OBERON_UBC_ERR_INT_MEMWTAXB_P 0x0000000000000800ULL 778201052Smarius#define OBERON_UBC_ERR_INT_MEMRDAXB_P 0x0000000000000400ULL 779201052Smarius#define OBERON_UBC_ERR_INT_DMARDUEB_P 0x0000000000000200ULL 780201052Smarius#define OBERON_UBC_ERR_INT_DMAWTUEB_P 0x0000000000000100ULL 781201052Smarius#define OBERON_UBC_ERR_INT_MEMWTAXA_P 0x0000000000000008ULL 782201052Smarius#define OBERON_UBC_ERR_INT_MEMRDAXA_P 0x0000000000000004ULL 783201052Smarius#define OBERON_UBC_ERR_INT_DMAWTUEA_P 0x0000000000000002ULL 784201052Smarius#define OBERON_UBC_ERR_INT_DMARDUEA_P 0x0000000000000001ULL 785201052Smarius 786201052Smarius/* JBC fatal reset enable register */ 787201052Smarius#define FIRE_JBC_FATAL_RST_EN_SPARE_P_INT_MASK 0x000000000c000000ULL 788201052Smarius#define FIRE_JBC_FATAL_RST_EN_SPARE_P_INT_SHFT 26 789201052Smarius#define FIRE_JBC_FATAL_RST_EN_MB_PEA_P_INT 0x0000000002000000ULL 790201052Smarius#define FIRE_JBC_FATAL_RST_EN_CPE_P_INT 0x0000000000008000ULL 791201052Smarius#define FIRE_JBC_FATAL_RST_EN_APE_P_INT 0x0000000000004000ULL 792201052Smarius#define FIRE_JBC_FATAL_RST_EN_PIO_CPE_INT 0x0000000000000040ULL 793201052Smarius#define FIRE_JBC_FATAL_RST_EN_JTCEEW_P_INT 0x0000000000000004ULL 794201052Smarius#define FIRE_JBC_FATAL_RST_EN_JTCEEI_P_INT 0x0000000000000002ULL 795201052Smarius#define FIRE_JBC_FATAL_RST_EN_JTCEER_P_INT 0x0000000000000001ULL 796201052Smarius 797201052Smarius/* JBC JBCINT in transaction error log register */ 798201052Smarius#define FIRE_JBCINT_ITRANS_ERR_LOG_Q_WORD_MASK 0x00c0000000000000ULL 799201052Smarius#define FIRE_JBCINT_ITRANS_ERR_LOG_Q_WORD_SHFT 54 800201052Smarius#define FIRE_JBCINT_ITRANS_ERR_LOG_TRANSID_MASK 0x0003000000000000ULL 801201052Smarius#define FIRE_JBCINT_ITRANS_ERR_LOG_TRANSID_SHFT 48 802201052Smarius#define FIRE_JBCINT_ITRANS_ERR_LOG_ADDR_MASK 0x000007ffffffffffULL 803201052Smarius#define FIRE_JBCINT_ITRANS_ERR_LOG_ADDR_SHFT 0 804201052Smarius 805201052Smarius/* JBC JBCINT in transaction error log register 2 */ 806201052Smarius#define FIRE_JBCINT_ITRANS_ERR_LOG2_ARB_WN_MASK 0x000ffffff0000000ULL 807201052Smarius#define FIRE_JBCINT_ITRANS_ERR_LOG2_ARB_WN_SHFT 28 808201052Smarius#define FIRE_JBCINT_ITRANS_ERR_LOG2_J_REQ_MASK 0x000000000fe00000ULL 809201052Smarius#define FIRE_JBCINT_ITRANS_ERR_LOG2_J_REQ_SHFT 21 810201052Smarius#define FIRE_JBCINT_ITRANS_ERR_LOG2_J_PACK_MASK 0x00000000001fffffULL 811201052Smarius#define FIRE_JBCINT_ITRANS_ERR_LOG2_J_PACK_SHFT 0 812201052Smarius 813201052Smarius/* JBC JBCINT out transaction error log register */ 814201052Smarius#define FIRE_JBCINT_OTRANS_ERR_LOG_TRANSID_MASK 0x003f000000000000ULL 815201052Smarius#define FIRE_JBCINT_OTRANS_ERR_LOG_TRANSID_SHFT 48 816201052Smarius#define FIRE_JBCINT_OTRANS_ERR_LOG_ADDR_MASK 0x000007ffffffffffULL 817201052Smarius#define FIRE_JBCINT_OTRANS_ERR_LOG_ADDR_SHFT 0 818201052Smarius 819201052Smarius/* JBC JBCINT out transaction error log register 2 */ 820201052Smarius#define FIRE_JBCINT_OTRANS_ERR_LOG2_ARB_WN_MASK 0x000ffffff0000000ULL 821201052Smarius#define FIRE_JBCINT_OTRANS_ERR_LOG2_ARB_WN_SHFT 28 822201052Smarius#define FIRE_JBCINT_OTRANS_ERR_LOG2_J_REQ_MASK 0x000000000fe00000ULL 823201052Smarius#define FIRE_JBCINT_OTRANS_ERR_LOG2_J_REQ_SHFT 21 824201052Smarius#define FIRE_JBCINT_OTRANS_ERR_LOG2_J_PACK_MASK 0x00000000001fffffULL 825201052Smarius#define FIRE_JBCINT_OTRANS_ERR_LOG2_J_PACK_SHFT 0 826201052Smarius 827201052Smarius/* JBC merge transaction error log register */ 828201052Smarius#define FIRE_FATAL_ERR_LOG_DATA_MASK 0xffffffffffffffffULL 829201052Smarius#define FIRE_FATAL_ERR_LOG_DATA_SHFT 0 830201052Smarius 831201052Smarius/* JBC merge transaction error log register 2 */ 832201052Smarius#define FIRE_FATAL_ERR_LOG2_ARB_WN_MASK 0x000ffffff0000000ULL 833201052Smarius#define FIRE_FATAL_ERR_LOG2_ARB_WN_SHFT 28 834201052Smarius#define FIRE_FATAL_ERR_LOG2_J_REQ_MASK 0x000000000fe00000ULL 835201052Smarius#define FIRE_FATAL_ERR_LOG2_J_REQ_SHFT 21 836201052Smarius#define FIRE_FATAL_ERR_LOG2_J_PACK_MASK 0x00000000001fffffULL 837201052Smarius#define FIRE_FATAL_ERR_LOG2_J_PACK_SHFT 0 838201052Smarius 839201052Smarius/* JBC merge transaction error log register */ 840201052Smarius#define FIRE_MERGE_TRANS_ERR_LOG_Q_WORD_MASK 0x00c0000000000000ULL 841201052Smarius#define FIRE_MERGE_TRANS_ERR_LOG_Q_WORD_SHFT 54 842201052Smarius#define FIRE_MERGE_TRANS_ERR_LOG_TRANSID_MASK 0x0003000000000000ULL 843201052Smarius#define FIRE_MERGE_TRANS_ERR_LOG_TRANSID_SHFT 48 844201052Smarius#define FIRE_MERGE_TRANS_ERR_LOG_JBC_TAG_MASK 0x0000f80000000000ULL 845201052Smarius#define FIRE_MERGE_TRANS_ERR_LOG_JBC_TAG_SHFT 43 846201052Smarius#define FIRE_MERGE_TRANS_ERR_LOG_ADDR_MASK 0x000007ffffffffffULL 847201052Smarius#define FIRE_MERGE_TRANS_ERR_LOG_ADDR_SHFT 0 848201052Smarius 849201052Smarius/* JBC DMCINT ODCD error log register */ 850201052Smarius#define FIRE_DMCINT_ODCD_ERR_LOG_TRANS_ID_MASK 0x0030000000000000ULL 851201052Smarius#define FIRE_DMCINT_ODCD_ERR_LOG_TRANS_ID_SHFT 52 852201052Smarius#define FIRE_DMCINT_ODCD_ERR_LOG_AID_MASK 0x000f000000000000ULL 853201052Smarius#define FIRE_DMCINT_ODCD_ERR_LOG_AID_SHFT 48 854201052Smarius#define FIRE_DMCINT_ODCD_ERR_LOG_TTYPE_MASK 0x0000f80000000000ULL 855201052Smarius#define FIRE_DMCINT_ODCD_ERR_LOG_TTYPE_SHFT 43 856201052Smarius#define FIRE_DMCINT_ODCD_ERR_LOG_ADDR_MASK 0x000007ffffffffffULL 857201052Smarius#define FIRE_DMCINT_ODCD_ERR_LOG_ADDR_SHFT 0 858201052Smarius 859201052Smarius/* JBC DMCINT IDC error log register */ 860201052Smarius#define FIRE_DMCINT_IDC_ERR_DMC_CTAG_MASK 0x000000000fff0000ULL 861201052Smarius#define FIRE_DMCINT_IDC_ERR_DMC_CTAG_SHFT 16 862201052Smarius#define FIRE_DMCINT_IDC_ERR_TRANSID_MASK 0x000000000000c000ULL 863201052Smarius#define FIRE_DMCINT_IDC_ERR_AGNTID_MASK 0x0000000000003c00ULL 864201052Smarius#define FIRE_DMCINT_IDC_ERR_AGNTID_SHFT 10 865201052Smarius#define FIRE_DMCINT_IDC_ERR_SRCID_MASK 0x00000000000003e0ULL 866201052Smarius#define FIRE_DMCINT_IDC_ERR_SRCID_SHFT 5 867201052Smarius#define FIRE_DMCINT_IDC_ERR_TARGID_MASK 0x000000000000001fULL 868201052Smarius#define FIRE_DMCINT_IDC_ERRO_TARGID_SHFT 0 869201052Smarius 870201052Smarius/* JBC CSR error log register */ 871201052Smarius#define FIRE_JBC_CSR_ERR_LOG_WR 0x0000040000000000ULL 872201052Smarius#define FIRE_JBC_CSR_ERR_LOG_BMASK_MASK 0x000003fffc000000ULL 873201052Smarius#define FIRE_JBC_CSR_ERR_LOG_BMASK_SHFT 26 874201052Smarius#define FIRE_JBC_CSR_ERR_LOG_ADDR_MASK 0x0000000003ffffffULL 875201052Smarius#define FIRE_JBC_CSR_ERR_LOG_ADDR_SHFT 0 876201052Smarius 877201052Smarius/* JBC core and block interrupt enable register */ 878201052Smarius#define FIRE_JBC_CORE_BLOCK_INT_EN_JBC 0x8000000000000000ULL 879201052Smarius#define FIRE_JBC_CORE_BLOCK_INT_EN_CSR 0x0000000000000008ULL 880201052Smarius#define FIRE_JBC_CORE_BLOCK_INT_EN_MERGE 0x0000000000000004ULL 881201052Smarius#define FIRE_JBC_CORE_BLOCK_INT_EN_JBCINT 0x0000000000000002ULL 882201052Smarius#define FIRE_JBC_CORE_BLOCK_INT_EN_DMCINT 0x0000000000000001ULL 883201052Smarius 884201052Smarius/* JBC core and block error status register */ 885201052Smarius#define FIRE_JBC_CORE_BLOCK_ERR_STAT_CSR 0x0000000000000008ULL 886201052Smarius#define FIRE_JBC_CORE_BLOCK_ERR_STAT_MERGE 0x0000000000000004ULL 887201052Smarius#define FIRE_JBC_CORE_BLOCK_ERR_STAT_JBCINT 0x0000000000000002ULL 888201052Smarius#define FIRE_JBC_CORE_BLOCK_ERR_STAT_DMCINT 0x0000000000000001ULL 889201052Smarius 890201052Smarius/* JBC performance counter select register - may also apply to UBC */ 891201052Smarius#define FO_XBC_PRF_CNT_PIO_RD_PCIEB 0x0000000000000018ULL 892201052Smarius#define FO_XBC_PRF_CNT_PIO_WR_PCIEB 0x0000000000000017ULL 893201052Smarius#define FO_XBC_PRF_CNT_PIO_RD_PCIEA 0x0000000000000016ULL 894201052Smarius#define FO_XBC_PRF_CNT_PIO_WR_PCIEA 0x0000000000000015ULL 895201052Smarius#define FO_XBC_PRF_CNT_WB 0x0000000000000014ULL 896201052Smarius#define FO_XBC_PRF_CNT_PIO_FRGN 0x0000000000000013ULL 897201052Smarius#define FO_XBC_PRF_CNT_XB_NCHRNT 0x0000000000000012ULL 898201052Smarius#define FO_XBC_PRF_CNT_FO_CHRNT 0x0000000000000011ULL 899201052Smarius#define FO_XBC_PRF_CNT_XB_CHRNT 0x0000000000000010ULL 900201052Smarius#define FO_XBC_PRF_CNT_AOKOFF_DOKOFF 0x000000000000000fULL 901201052Smarius#define FO_XBC_PRF_CNT_DOKOFF 0x000000000000000eULL 902201052Smarius#define FO_XBC_PRF_CNT_AOKOFF 0x000000000000000dULL 903201052Smarius#define FO_XBC_PRF_CNT_RD_TOTAL 0x000000000000000cULL 904201052Smarius#define FO_XBC_PRF_CNT_WR_TOTAL 0x000000000000000bULL 905201052Smarius#define FO_XBC_PRF_CNT_WR_PARTIAL 0x000000000000000aULL 906201052Smarius#define FO_XBC_PRF_CNT_PIOS_CSR_RINGB 0x0000000000000009ULL 907201052Smarius#define FO_XBC_PRF_CNT_PIOS_CSR_RINGA 0x0000000000000008ULL 908201052Smarius#define FO_XBC_PRF_CNT_PIOS_EBUS 0x0000000000000007ULL 909201052Smarius#define FO_XBC_PRF_CNT_PIOS_I2C 0x0000000000000006ULL 910201052Smarius#define FO_XBC_PRF_CNT_RD_LAT_SMPLS 0x0000000000000005ULL 911201052Smarius#define FO_XBC_PRF_CNT_RD_LAT 0x0000000000000004ULL 912201052Smarius#define FO_XBC_PRF_CNT_ON_XB 0x0000000000000003ULL 913201052Smarius#define FO_XBC_PRF_CNT_XB_IDL 0x0000000000000002ULL 914201052Smarius#define FO_XBC_PRF_CNT_XB_CLK 0x0000000000000001ULL 915201052Smarius#define FO_XBC_PRF_CNT_NONE 0x0000000000000000ULL 916201052Smarius#define FO_XBC_PRF_CNT_CNT1_SHFT 8 917201052Smarius#define FO_XBC_PRF_CNT_CNT0_SHFT 0 918201052Smarius 919201052Smarius/* JBC performance counter 0/1 registers - may also apply to UBC */ 920201052Smarius#define FO_XBC_PRF_CNT_MASK 0xffffffffffffffffULL 921201052Smarius#define FO_XBC_PRF_CNT_SHFT 0 922201052Smarius 923201052Smarius/* Lookup tables */ 924262613Sdimconst uint16_t fire_freq_nak_tmr_thrs[6][4] = { 925201052Smarius { 0x00ed, 0x049, 0x043, 0x030 }, 926201052Smarius { 0x01a0, 0x076, 0x06b, 0x048 }, 927201052Smarius { 0x022f, 0x09a, 0x056, 0x056 }, 928201052Smarius { 0x042f, 0x11a, 0x096, 0x096 }, 929201052Smarius { 0x082f, 0x21a, 0x116, 0x116 }, 930201052Smarius { 0x102f, 0x41a, 0x216, 0x216 } 931201052Smarius}; 932201052Smarius 933262613Sdimconst uint16_t fire_rply_tmr_thrs[6][4] = { 934201052Smarius { 0x0379, 0x112, 0x0fc, 0x0b4 }, 935201052Smarius { 0x0618, 0x1BA, 0x192, 0x10e }, 936201052Smarius { 0x0831, 0x242, 0x143, 0x143 }, 937201052Smarius { 0x0fb1, 0x422, 0x233, 0x233 }, 938201052Smarius { 0x1eb0, 0x7e1, 0x412, 0x412 }, 939201052Smarius { 0x3cb0, 0xf61, 0x7d2, 0x7d2 } 940201052Smarius}; 941201052Smarius 942201052Smarius/* Register default values */ 943201052Smarius#define FO_PCI_TLU_CTRL_L0S_TIM_DFLT 0xda 944201052Smarius#define FO_PCI_TLU_CTRL_CFG_DFLT 0x1 945201052Smarius#define FO_PCI_LPU_LTSSM_CFG2_12_TO_DFLT 0x2dc6c0 946201052Smarius#define FO_PCI_LPU_LTSSM_CFG3_2_TO_DFLT 0x7a120 947201052Smarius#define FO_PCI_LPU_LTSSM_CFG4_DATA_RATE_DFLT 0x2 948201052Smarius#define FO_PCI_LPU_LTSSM_CFG4_N_FTS_DFLT 0x8c 949201052Smarius#define OBERON_PCI_LPU_TXLNK_RPLY_TMR_THRS_DFLT 0xc9 950201052Smarius#define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR_HD_DFLT 0x0 951201052Smarius#define FO_PCI_LPU_TXLNK_RTR_FIFO_PTR_TL_DFLT 0xffff 952201052Smarius 953201052Smarius/* INO macros */ 954201052Smarius#define FO_EQ_FIRST_INO 0x18 955201052Smarius#define FO_EQ_LAST_INO 0x3b 956201052Smarius#define FO_DMC_PEC_INO 0x3e 957201052Smarius#define FO_XCB_INO 0x3f 958201052Smarius#define FO_MAX_INO FO_XCB_INO 959201052Smarius 960201052Smarius/* Device space macros */ 961201052Smarius#define FO_CONF_BUS_SHFT 20 962201052Smarius#define FO_CONF_DEV_SHFT 15 963201052Smarius#define FO_CONF_FUNC_SHFT 12 964201052Smarius#define FO_CONF_REG_SHFT 0 965201052Smarius#define FO_IO_SIZE 0x10000000 966201052Smarius#define FO_MEM_SIZE 0x1ffff0000 967201052Smarius 968201052Smarius#define FO_CONF_OFF(bus, slot, func, reg) \ 969201052Smarius (((bus) << FO_CONF_BUS_SHFT) | \ 970201052Smarius ((slot) << FO_CONF_DEV_SHFT) | \ 971201052Smarius ((func) << FO_CONF_FUNC_SHFT) | \ 972201052Smarius ((reg) << FO_CONF_REG_SHFT)) 973201052Smarius 974201052Smarius/* Width of the physical addresses the IOMMU translates to */ 975201052Smarius#define FIRE_IOMMU_BITS 43 976201052Smarius#define OBERON_IOMMU_BITS 47 977201052Smarius 978201052Smarius/* Event queue macros */ 979201052Smarius#define FO_EQ_ALIGNMENT (512 * 1024) 980201052Smarius#define FO_EQ_NRECORDS 128 981201052Smarius#define FO_EQ_RECORD_SIZE 64 982201052Smarius 983201052Smarius/* Event queue record format */ 984201052Smariusstruct fo_msiq_record { 985201052Smarius uint64_t fomqr_word0; 986201052Smarius uint64_t fomqr_word1; 987201052Smarius uint64_t fomqr_reserved[6]; 988201052Smarius}; 989201052Smarius 990201052Smarius#define FO_MQR_WORD0_FMT_TYPE_MASK 0x7f00000000000000ULL 991201052Smarius#define FO_MQR_WORD0_FMT_TYPE_SHFT 56 992201052Smarius#define FO_MQR_WORD0_FMT_TYPE_MSI64 0x7800000000000000ULL 993201052Smarius#define FO_MQR_WORD0_FMT_TYPE_MSI32 0x5800000000000000ULL 994201052Smarius#define FO_MQR_WORD0_FMT_TYPE_MSG 0x3000000000000000ULL 995201052Smarius#define FO_MQR_WORD0_FMT_TYPE_MSG_ROUTE_MASK 0x0700000000000000ULL 996201052Smarius#define FO_MQR_WORD0_FMT_TYPE_MSG_ROUTE_SHFT 56 997201052Smarius#define FO_MQR_WORD0_LENGTH_MASK 0x00ffc00000000000ULL 998201052Smarius#define FO_MQR_WORD0_LENGTH_SHFT 46 999201052Smarius#define FO_MQR_WORD0_ADDR0_MASK 0x00003fff00000000ULL 1000201052Smarius#define FO_MQR_WORD0_ADDR0_SHFT 32 1001201052Smarius#define FO_MQR_WORD0_RID_MASK 0x00000000ffff0000ULL 1002201052Smarius#define FO_MQR_WORD0_RID_SHFT 16 1003201052Smarius#define FO_MQR_WORD0_DATA0_MASK 0x000000000000ffffULL 1004201052Smarius#define FO_MQR_WORD0_DATA0_SHFT 0 1005201052Smarius#define FO_MQR_WORD1_ADDR1_MASK 0xffffffffffff0000ULL 1006201052Smarius#define FO_MQR_WORD1_ADDR1_SHFT 16 1007201052Smarius#define FO_MQR_WORD1_DATA1_MASK 0x000000000000ffffULL 1008201052Smarius#define FO_MQR_WORD1_DATA1_SHFT 0 1009201052Smarius 1010201052Smarius#endif /* !_SPARC64_PCI_FIREREG_H_ */ 1011