tlb.h revision 93687
1/*- 2 * Copyright (c) 2001 Jake Burkholder. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/sparc64/include/tlb.h 93687 2002-04-02 17:50:13Z tmm $ 27 */ 28 29#ifndef _MACHINE_TLB_H_ 30#define _MACHINE_TLB_H_ 31 32#define TLB_DAR_SLOT_SHIFT (3) 33#define TLB_DAR_SLOT(slot) ((slot) << TLB_DAR_SLOT_SHIFT) 34 35#define TAR_VPN_SHIFT (13) 36#define TAR_CTX_MASK ((1 << TAR_VPN_SHIFT) - 1) 37 38#define TLB_TAR_VA(va) ((va) & ~TAR_CTX_MASK) 39#define TLB_TAR_CTX(ctx) ((ctx) & TAR_CTX_MASK) 40 41#define TLB_DEMAP_ID_SHIFT (4) 42#define TLB_DEMAP_ID_PRIMARY (0) 43#define TLB_DEMAP_ID_SECONDARY (1) 44#define TLB_DEMAP_ID_NUCLEUS (2) 45 46#define TLB_DEMAP_TYPE_SHIFT (6) 47#define TLB_DEMAP_TYPE_PAGE (0) 48#define TLB_DEMAP_TYPE_CONTEXT (1) 49 50#define TLB_DEMAP_VA(va) ((va) & ~PAGE_MASK) 51#define TLB_DEMAP_ID(id) ((id) << TLB_DEMAP_ID_SHIFT) 52#define TLB_DEMAP_TYPE(type) ((type) << TLB_DEMAP_TYPE_SHIFT) 53 54#define TLB_DEMAP_PAGE (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_PAGE)) 55#define TLB_DEMAP_CONTEXT (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_CONTEXT)) 56 57#define TLB_DEMAP_PRIMARY (TLB_DEMAP_ID(TLB_DEMAP_ID_PRIMARY)) 58#define TLB_DEMAP_SECONDARY (TLB_DEMAP_ID(TLB_DEMAP_ID_SECONDARY)) 59#define TLB_DEMAP_NUCLEUS (TLB_DEMAP_ID(TLB_DEMAP_ID_NUCLEUS)) 60 61#define TLB_CTX_KERNEL (0) 62#define TLB_CTX_USER_MIN (1) 63#define TLB_CTX_USER_MAX (8192) 64 65#define TLB_DTLB (1 << 0) 66#define TLB_ITLB (1 << 1) 67 68#define MMU_SFSR_ASI_SHIFT (16) 69#define MMU_SFSR_FT_SHIFT (7) 70#define MMU_SFSR_E_SHIFT (6) 71#define MMU_SFSR_CT_SHIFT (4) 72#define MMU_SFSR_PR_SHIFT (3) 73#define MMU_SFSR_W_SHIFT (2) 74#define MMU_SFSR_OW_SHIFT (1) 75#define MMU_SFSR_FV_SHIFT (0) 76 77#define MMU_SFSR_ASI_SIZE (8) 78#define MMU_SFSR_FT_SIZE (6) 79#define MMU_SFSR_CT_SIZE (2) 80 81#define MMU_SFSR_W (1L << MMU_SFSR_W_SHIFT) 82 83extern int kernel_tlb_slots; 84extern struct tte *kernel_ttes; 85 86/* 87 * Some tlb operations must be atomic, so no interrupt or trap can be allowed 88 * while they are in progress. Traps should not happen, but interrupts need to 89 * be explicitely disabled. critical_enter() cannot be used here, since it only 90 * disables soft interrupts. 91 */ 92 93static __inline void 94tlb_context_demap(struct pmap *pm) 95{ 96 void *cookie; 97 u_long s; 98 99 /* 100 * It is important that we are not interrupted or preempted while 101 * doing the IPIs. The interrupted CPU may hold locks, and since 102 * it will wait for the CPU that sent the IPI, this can lead 103 * to a deadlock when an interrupt comes in on that CPU and it's 104 * handler tries to grab one of that locks. This will only happen for 105 * spin locks, but these IPI types are delivered even if normal 106 * interrupts are disabled, so the lock critical section will not 107 * protect the target processor from entering the IPI handler with 108 * the lock held. 109 */ 110 critical_enter(); 111 cookie = ipi_tlb_context_demap(pm); 112 if (pm->pm_active & PCPU_GET(cpumask)) { 113 KASSERT(pm->pm_context[PCPU_GET(cpuid)] != -1, 114 ("tlb_context_demap: inactive pmap?")); 115 s = intr_disable(); 116 stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_DMMU_DEMAP, 0); 117 stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_IMMU_DEMAP, 0); 118 membar(Sync); 119 intr_restore(s); 120 } 121 ipi_wait(cookie); 122 critical_exit(); 123} 124 125static __inline void 126tlb_page_demap(u_int tlb, struct pmap *pm, vm_offset_t va) 127{ 128 u_long flags; 129 void *cookie; 130 u_long s; 131 132 critical_enter(); 133 cookie = ipi_tlb_page_demap(tlb, pm, va); 134 if (pm->pm_active & PCPU_GET(cpumask)) { 135 KASSERT(pm->pm_context[PCPU_GET(cpuid)] != -1, 136 ("tlb_page_demap: inactive pmap?")); 137 if (pm == kernel_pmap) 138 flags = TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE; 139 else 140 flags = TLB_DEMAP_PRIMARY | TLB_DEMAP_PAGE; 141 142 s = intr_disable(); 143 if (tlb & TLB_DTLB) { 144 stxa(TLB_DEMAP_VA(va) | flags, ASI_DMMU_DEMAP, 0); 145 membar(Sync); 146 } 147 if (tlb & TLB_ITLB) { 148 stxa(TLB_DEMAP_VA(va) | flags, ASI_IMMU_DEMAP, 0); 149 membar(Sync); 150 } 151 intr_restore(s); 152 } 153 ipi_wait(cookie); 154 critical_exit(); 155} 156 157static __inline void 158tlb_range_demap(struct pmap *pm, vm_offset_t start, vm_offset_t end) 159{ 160 vm_offset_t va; 161 void *cookie; 162 u_long flags; 163 u_long s; 164 165 critical_enter(); 166 cookie = ipi_tlb_range_demap(pm, start, end); 167 if (pm->pm_active & PCPU_GET(cpumask)) { 168 KASSERT(pm->pm_context[PCPU_GET(cpuid)] != -1, 169 ("tlb_range_demap: inactive pmap?")); 170 if (pm == kernel_pmap) 171 flags = TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE; 172 else 173 flags = TLB_DEMAP_PRIMARY | TLB_DEMAP_PAGE; 174 175 s = intr_disable(); 176 for (va = start; va < end; va += PAGE_SIZE) { 177 stxa(TLB_DEMAP_VA(va) | flags, ASI_DMMU_DEMAP, 0); 178 stxa(TLB_DEMAP_VA(va) | flags, ASI_IMMU_DEMAP, 0); 179 membar(Sync); 180 } 181 intr_restore(s); 182 } 183 ipi_wait(cookie); 184 critical_exit(); 185} 186 187#define tlb_tte_demap(tte, pm) \ 188 tlb_page_demap(TD_GET_TLB((tte).tte_data), pm, \ 189 TV_GET_VA((tte).tte_vpn)); 190 191#endif /* !_MACHINE_TLB_H_ */ 192