tlb.h revision 93002
1/*- 2 * Copyright (c) 2001 Jake Burkholder. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/sparc64/include/tlb.h 93002 2002-03-23 04:20:00Z jake $ 27 */ 28 29#ifndef _MACHINE_TLB_H_ 30#define _MACHINE_TLB_H_ 31 32#define TLB_SLOT_COUNT 64 /* XXX */ 33 34#define TLB_SLOT_TSB_KERNEL_MIN 62 /* XXX */ 35#define TLB_SLOT_KERNEL 63 /* XXX */ 36 37#define TLB_DAR_SLOT_SHIFT (3) 38#define TLB_DAR_SLOT(slot) ((slot) << TLB_DAR_SLOT_SHIFT) 39 40#define TAR_VPN_SHIFT (13) 41#define TAR_CTX_MASK ((1 << TAR_VPN_SHIFT) - 1) 42 43#define TLB_TAR_VA(va) ((va) & ~TAR_CTX_MASK) 44#define TLB_TAR_CTX(ctx) ((ctx) & TAR_CTX_MASK) 45 46#define TLB_DEMAP_ID_SHIFT (4) 47#define TLB_DEMAP_ID_PRIMARY (0) 48#define TLB_DEMAP_ID_SECONDARY (1) 49#define TLB_DEMAP_ID_NUCLEUS (2) 50 51#define TLB_DEMAP_TYPE_SHIFT (6) 52#define TLB_DEMAP_TYPE_PAGE (0) 53#define TLB_DEMAP_TYPE_CONTEXT (1) 54 55#define TLB_DEMAP_VA(va) ((va) & ~PAGE_MASK) 56#define TLB_DEMAP_ID(id) ((id) << TLB_DEMAP_ID_SHIFT) 57#define TLB_DEMAP_TYPE(type) ((type) << TLB_DEMAP_TYPE_SHIFT) 58 59#define TLB_DEMAP_PAGE (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_PAGE)) 60#define TLB_DEMAP_CONTEXT (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_CONTEXT)) 61 62#define TLB_DEMAP_PRIMARY (TLB_DEMAP_ID(TLB_DEMAP_ID_PRIMARY)) 63#define TLB_DEMAP_SECONDARY (TLB_DEMAP_ID(TLB_DEMAP_ID_SECONDARY)) 64#define TLB_DEMAP_NUCLEUS (TLB_DEMAP_ID(TLB_DEMAP_ID_NUCLEUS)) 65 66#define TLB_CTX_KERNEL (0) 67#define TLB_CTX_USER_MIN (1) 68#define TLB_CTX_USER_MAX (8192) 69 70#define TLB_DTLB (1 << 0) 71#define TLB_ITLB (1 << 1) 72 73#define MMU_SFSR_ASI_SHIFT (16) 74#define MMU_SFSR_FT_SHIFT (7) 75#define MMU_SFSR_E_SHIFT (6) 76#define MMU_SFSR_CT_SHIFT (4) 77#define MMU_SFSR_PR_SHIFT (3) 78#define MMU_SFSR_W_SHIFT (2) 79#define MMU_SFSR_OW_SHIFT (1) 80#define MMU_SFSR_FV_SHIFT (0) 81 82#define MMU_SFSR_ASI_SIZE (8) 83#define MMU_SFSR_FT_SIZE (6) 84#define MMU_SFSR_CT_SIZE (2) 85 86#define MMU_SFSR_W (1L << MMU_SFSR_W_SHIFT) 87 88extern int kernel_tlb_slots; 89extern struct tte *kernel_ttes; 90 91/* 92 * Some tlb operations must be atomic, so no interrupt or trap can be allowed 93 * while they are in progress. Traps should not happen, but interrupts need to 94 * be explicitely disabled. critical_enter() cannot be used here, since it only 95 * disables soft interrupts. 96 */ 97 98static __inline void 99tlb_context_demap(struct pmap *pm) 100{ 101 void *cookie; 102 u_long s; 103 104 /* 105 * It is important that we are not interrupted or preempted while 106 * doing the IPIs. The interrupted CPU may hold locks, and since 107 * it will wait for the CPU that sent the IPI, this can lead 108 * to a deadlock when an interrupt comes in on that CPU and it's 109 * handler tries to grab one of that locks. This will only happen for 110 * spin locks, but these IPI types are delivered even if normal 111 * interrupts are disabled, so the lock critical section will not 112 * protect the target processor from entering the IPI handler with 113 * the lock held. 114 */ 115 critical_enter(); 116 cookie = ipi_tlb_context_demap(pm); 117 if (pm->pm_active & PCPU_GET(cpumask)) { 118 KASSERT(pm->pm_context[PCPU_GET(cpuid)] != -1, 119 ("tlb_context_demap: inactive pmap?")); 120 s = intr_disable(); 121 stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_DMMU_DEMAP, 0); 122 stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_IMMU_DEMAP, 0); 123 membar(Sync); 124 intr_restore(s); 125 } 126 ipi_wait(cookie); 127 critical_exit(); 128} 129 130static __inline void 131tlb_page_demap(u_int tlb, struct pmap *pm, vm_offset_t va) 132{ 133 u_long flags; 134 void *cookie; 135 u_long s; 136 137 critical_enter(); 138 cookie = ipi_tlb_page_demap(tlb, pm, va); 139 if (pm->pm_active & PCPU_GET(cpumask)) { 140 KASSERT(pm->pm_context[PCPU_GET(cpuid)] != -1, 141 ("tlb_page_demap: inactive pmap?")); 142 if (pm == kernel_pmap) 143 flags = TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE; 144 else 145 flags = TLB_DEMAP_PRIMARY | TLB_DEMAP_PAGE; 146 147 s = intr_disable(); 148 if (tlb & TLB_DTLB) { 149 stxa(TLB_DEMAP_VA(va) | flags, ASI_DMMU_DEMAP, 0); 150 membar(Sync); 151 } 152 if (tlb & TLB_ITLB) { 153 stxa(TLB_DEMAP_VA(va) | flags, ASI_IMMU_DEMAP, 0); 154 membar(Sync); 155 } 156 intr_restore(s); 157 } 158 ipi_wait(cookie); 159 critical_exit(); 160} 161 162static __inline void 163tlb_range_demap(struct pmap *pm, vm_offset_t start, vm_offset_t end) 164{ 165 vm_offset_t va; 166 void *cookie; 167 u_long flags; 168 u_long s; 169 170 critical_enter(); 171 cookie = ipi_tlb_range_demap(pm, start, end); 172 if (pm->pm_active & PCPU_GET(cpumask)) { 173 KASSERT(pm->pm_context[PCPU_GET(cpuid)] != -1, 174 ("tlb_range_demap: inactive pmap?")); 175 if (pm == kernel_pmap) 176 flags = TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE; 177 else 178 flags = TLB_DEMAP_PRIMARY | TLB_DEMAP_PAGE; 179 180 s = intr_disable(); 181 for (va = start; va < end; va += PAGE_SIZE) { 182 stxa(TLB_DEMAP_VA(va) | flags, ASI_DMMU_DEMAP, 0); 183 stxa(TLB_DEMAP_VA(va) | flags, ASI_IMMU_DEMAP, 0); 184 membar(Sync); 185 } 186 intr_restore(s); 187 } 188 ipi_wait(cookie); 189 critical_exit(); 190} 191 192#define tlb_tte_demap(tte, pm) \ 193 tlb_page_demap(TD_GET_TLB((tte).tte_data), pm, \ 194 TV_GET_VA((tte).tte_vpn)); 195 196#endif /* !_MACHINE_TLB_H_ */ 197