tlb.h revision 91224 
1/*-
2 * Copyright (c) 2001 Jake Burkholder.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/sparc64/include/tlb.h 91224 2002-02-25 04:56:50Z jake $
27 */
28
29#ifndef	_MACHINE_TLB_H_
30#define	_MACHINE_TLB_H_
31
32#define	TLB_SLOT_COUNT			64
33
34#define	TLB_SLOT_TSB_KERNEL_MIN		62	/* XXX */
35#define	TLB_SLOT_KERNEL			63
36
37#define	TLB_DAR_SLOT_SHIFT		(3)
38#define	TLB_DAR_SLOT(slot)		((slot) << TLB_DAR_SLOT_SHIFT)
39
40#define	TAR_VPN_SHIFT			(13)
41#define	TAR_CTX_MASK			((1 << TAR_VPN_SHIFT) - 1)
42
43#define	TLB_TAR_VA(va)			((va) & ~TAR_CTX_MASK)
44#define	TLB_TAR_CTX(ctx)		((ctx) & TAR_CTX_MASK)
45
46#define	TLB_DEMAP_ID_SHIFT		(4)
47#define	TLB_DEMAP_ID_PRIMARY		(0)
48#define	TLB_DEMAP_ID_SECONDARY		(1)
49#define	TLB_DEMAP_ID_NUCLEUS		(2)
50
51#define	TLB_DEMAP_TYPE_SHIFT		(6)
52#define	TLB_DEMAP_TYPE_PAGE		(0)
53#define	TLB_DEMAP_TYPE_CONTEXT		(1)
54
55#define	TLB_DEMAP_VA(va)		((va) & ~PAGE_MASK)
56#define	TLB_DEMAP_ID(id)		((id) << TLB_DEMAP_ID_SHIFT)
57#define	TLB_DEMAP_TYPE(type)		((type) << TLB_DEMAP_TYPE_SHIFT)
58
59#define	TLB_DEMAP_PAGE			(TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_PAGE))
60#define	TLB_DEMAP_CONTEXT		(TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_CONTEXT))
61
62#define	TLB_DEMAP_PRIMARY		(TLB_DEMAP_ID(TLB_DEMAP_ID_PRIMARY))
63#define	TLB_DEMAP_SECONDARY		(TLB_DEMAP_ID(TLB_DEMAP_ID_SECONDARY))
64#define	TLB_DEMAP_NUCLEUS		(TLB_DEMAP_ID(TLB_DEMAP_ID_NUCLEUS))
65
66#define	TLB_CTX_KERNEL			(0)
67
68#define	TLB_DTLB			(1 << 0)
69#define	TLB_ITLB			(1 << 1)
70
71#define	MMU_SFSR_ASI_SHIFT		(16)
72#define	MMU_SFSR_FT_SHIFT		(7)
73#define	MMU_SFSR_E_SHIFT		(6)
74#define	MMU_SFSR_CT_SHIFT		(4)
75#define	MMU_SFSR_PR_SHIFT		(3)
76#define	MMU_SFSR_W_SHIFT		(2)
77#define	MMU_SFSR_OW_SHIFT		(1)
78#define	MMU_SFSR_FV_SHIFT		(0)
79
80#define	MMU_SFSR_ASI_SIZE		(8)
81#define	MMU_SFSR_FT_SIZE		(6)
82#define	MMU_SFSR_CT_SIZE		(2)
83
84#define	MMU_SFSR_W			(1L << MMU_SFSR_W_SHIFT)
85
86/*
87 * Some tlb operations must be atomical, so no interrupt or trap can be allowed
88 * while they are in progress. Traps should not happen, but interrupts need to
89 * be explicitely disabled. critical_enter() cannot be used here, since it only
90 * disables soft interrupts.
91 * XXX: is something like this needed elsewhere, too?
92 */
93
94static __inline void
95tlb_dtlb_context_primary_demap(void)
96{
97	stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_DMMU_DEMAP, 0);
98	membar(Sync);
99}
100
101static __inline void
102tlb_dtlb_page_demap(u_long ctx, vm_offset_t va)
103{
104	if (ctx == TLB_CTX_KERNEL) {
105		stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE,
106		    ASI_DMMU_DEMAP, 0);
107		membar(Sync);
108	} else {
109		stxa(AA_DMMU_SCXR, ASI_DMMU, ctx);
110		membar(Sync);
111		stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_SECONDARY | TLB_DEMAP_PAGE,
112		    ASI_DMMU_DEMAP, 0);
113		membar(Sync);
114		stxa(AA_DMMU_SCXR, ASI_DMMU, 0);
115		membar(Sync);
116	}
117}
118
119static __inline void
120tlb_dtlb_store(vm_offset_t va, u_long ctx, struct tte tte)
121{
122	u_long pst;
123
124	pst = intr_disable();
125	stxa(AA_DMMU_TAR, ASI_DMMU,
126	    TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
127	stxa(0, ASI_DTLB_DATA_IN_REG, tte.tte_data);
128	membar(Sync);
129	intr_restore(pst);
130}
131
132static __inline void
133tlb_dtlb_store_slot(vm_offset_t va, u_long ctx, struct tte tte, int slot)
134{
135	u_long pst;
136
137	pst = intr_disable();
138	stxa(AA_DMMU_TAR, ASI_DMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
139	stxa(TLB_DAR_SLOT(slot), ASI_DTLB_DATA_ACCESS_REG, tte.tte_data);
140	membar(Sync);
141	intr_restore(pst);
142}
143
144static __inline void
145tlb_itlb_context_primary_demap(void)
146{
147	stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_IMMU_DEMAP, 0);
148	membar(Sync);
149}
150
151static __inline void
152tlb_itlb_page_demap(u_long ctx, vm_offset_t va)
153{
154	if (ctx == TLB_CTX_KERNEL) {
155		stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE,
156		    ASI_IMMU_DEMAP, 0);
157		flush(KERNBASE);
158	} else {
159		stxa(AA_DMMU_SCXR, ASI_DMMU, ctx);
160		membar(Sync);
161		stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_SECONDARY | TLB_DEMAP_PAGE,
162		    ASI_IMMU_DEMAP, 0);
163		membar(Sync);
164		stxa(AA_DMMU_SCXR, ASI_DMMU, 0);
165		/* flush probably not needed. */
166		membar(Sync);
167	}
168}
169
170static __inline void
171tlb_itlb_store(vm_offset_t va, u_long ctx, struct tte tte)
172{
173	u_long pst;
174
175	pst = intr_disable();
176	stxa(AA_IMMU_TAR, ASI_IMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
177	stxa(0, ASI_ITLB_DATA_IN_REG, tte.tte_data);
178	if (ctx == TLB_CTX_KERNEL)
179		flush(va);
180	else {
181		/*
182		 * flush probably not needed and impossible here, no access to
183		 * user page.
184		 */
185		membar(Sync);
186	}
187	intr_restore(pst);
188}
189
190static __inline void
191tlb_context_demap(u_int context)
192{
193	tlb_dtlb_context_primary_demap();
194	tlb_itlb_context_primary_demap();
195}
196
197static __inline void
198tlb_itlb_store_slot(vm_offset_t va, u_long ctx, struct tte tte, int slot)
199{
200	u_long pst;
201
202	pst = intr_disable();
203	stxa(AA_IMMU_TAR, ASI_IMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
204	stxa(TLB_DAR_SLOT(slot), ASI_ITLB_DATA_ACCESS_REG, tte.tte_data);
205	flush(va);
206	intr_restore(pst);
207}
208
209static __inline void
210tlb_page_demap(u_int tlb, u_int ctx, vm_offset_t va)
211{
212	if (tlb & TLB_DTLB)
213		tlb_dtlb_page_demap(ctx, va);
214	if (tlb & TLB_ITLB)
215		tlb_itlb_page_demap(ctx, va);
216}
217
218static __inline void
219tlb_range_demap(u_int ctx, vm_offset_t start, vm_offset_t end)
220{
221	for (; start < end; start += PAGE_SIZE)
222		tlb_page_demap(TLB_DTLB | TLB_ITLB, ctx, start);
223}
224
225static __inline void
226tlb_tte_demap(struct tte tte, u_int ctx)
227{
228	tlb_page_demap(TD_GET_TLB(tte.tte_data), ctx, TV_GET_VA(tte.tte_vpn));
229}
230
231static __inline void
232tlb_store(u_int tlb, vm_offset_t va, u_long ctx, struct tte tte)
233{
234	if (tlb & TLB_DTLB)
235		tlb_dtlb_store(va, ctx, tte);
236	if (tlb & TLB_ITLB)
237		tlb_itlb_store(va, ctx, tte);
238}
239
240static __inline void
241tlb_store_slot(u_int tlb, vm_offset_t va, u_long ctx, struct tte tte, int slot)
242{
243	if (tlb & TLB_DTLB)
244		tlb_dtlb_store_slot(va, ctx, tte, slot);
245	if (tlb & TLB_ITLB)
246		tlb_itlb_store_slot(va, ctx, tte, slot);
247}
248
249#endif /* !_MACHINE_TLB_H_ */
250