tlb.h revision 81377 
1/*-
2 * Copyright (c) 2001 Jake Burkholder.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/sparc64/include/tlb.h 81377 2001-08-10 04:21:44Z jake $
27 */
28
29#ifndef	_MACHINE_TLB_H_
30#define	_MACHINE_TLB_H_
31
32#define	TLB_SLOT_COUNT			64
33
34#define	TLB_SLOT_TSB_KERNEL_MIN		60	/* XXX */
35#define	TLB_SLOT_TSB_USER_PRIMARY	61
36#define	TLB_SLOT_TSB_USER_SECONDARY	62
37#define	TLB_SLOT_KERNEL			63
38
39#define	TLB_DAR_SLOT_SHIFT		(3)
40#define	TLB_DAR_SLOT(slot)		((slot) << TLB_DAR_SLOT_SHIFT)
41
42#define	TLB_TAR_VA(va)			((va) & ~PAGE_MASK)
43#define	TLB_TAR_CTX(ctx)		((ctx) & PAGE_MASK)
44
45#define	TLB_DEMAP_ID_SHIFT		(4)
46#define	TLB_DEMAP_ID_PRIMARY		(0)
47#define	TLB_DEMAP_ID_SECONDARY		(1)
48#define	TLB_DEMAP_ID_NUCLEUS		(2)
49
50#define	TLB_DEMAP_TYPE_SHIFT		(6)
51#define	TLB_DEMAP_TYPE_PAGE		(0)
52#define	TLB_DEMAP_TYPE_CONTEXT		(1)
53
54#define	TLB_DEMAP_VA(va)		((va) & ~PAGE_MASK)
55#define	TLB_DEMAP_ID(id)		((id) << TLB_DEMAP_ID_SHIFT)
56#define	TLB_DEMAP_TYPE(type)		((type) << TLB_DEMAP_TYPE_SHIFT)
57
58#define	TLB_DEMAP_PAGE			(TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_PAGE))
59#define	TLB_DEMAP_CONTEXT		(TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_CONTEXT))
60
61#define	TLB_DEMAP_PRIMARY		(TLB_DEMAP_ID(TLB_DEMAP_ID_PRIMARY))
62#define	TLB_DEMAP_SECONDARY		(TLB_DEMAP_ID(TLB_DEMAP_ID_SECONDARY))
63#define	TLB_DEMAP_NUCLEUS		(TLB_DEMAP_ID(TLB_DEMAP_ID_NUCLEUS))
64
65#define	TLB_CTX_KERNEL			(0)
66
67#define	TLB_DTLB			(1 << 0)
68#define	TLB_ITLB			(1 << 1)
69
70#define	MMU_SFSR_ASI_SHIFT		(16)
71#define	MMU_SFSR_FT_SHIFT		(7)
72#define	MMU_SFSR_E_SHIFT		(6)
73#define	MMU_SFSR_CT_SHIFT		(4)
74#define	MMU_SFSR_PR_SHIFT		(3)
75#define	MMU_SFSR_W_SHIFT		(2)
76#define	MMU_SFSR_OW_SHIFT		(1)
77#define	MMU_SFSR_FV_SHIFT		(0)
78
79#define	MMU_SFSR_ASI_SIZE		(8)
80#define	MMU_SFSR_FT_SIZE		(6)
81#define	MMU_SFSR_CT_SIZE		(2)
82
83#define	MMU_SFSR_W			(1L << MMU_SFSR_W_SHIFT)
84
85static __inline void
86tlb_dtlb_page_demap(u_long ctx, vm_offset_t va)
87{
88	if (ctx == TLB_CTX_KERNEL) {
89		stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE,
90		    ASI_DMMU_DEMAP, 0);
91		membar(Sync);
92	} else {
93		stxa(AA_DMMU_SCXR, ASI_DMMU, ctx);
94		membar(Sync);
95		stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_SECONDARY | TLB_DEMAP_PAGE,
96		    ASI_DMMU_DEMAP, 0);
97		stxa(AA_DMMU_SCXR, ASI_DMMU, 0);
98		membar(Sync);
99	}
100}
101
102static __inline void
103tlb_dtlb_store(vm_offset_t va, u_long ctx, struct tte tte)
104{
105	stxa(AA_DMMU_TAR, ASI_DMMU,
106	    TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
107	stxa(0, ASI_DTLB_DATA_IN_REG, tte.tte_data);
108	membar(Sync);
109}
110
111static __inline void
112tlb_dtlb_store_slot(vm_offset_t va, u_long ctx, struct tte tte, int slot)
113{
114	stxa(AA_DMMU_TAR, ASI_DMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
115	stxa(TLB_DAR_SLOT(slot), ASI_DTLB_DATA_ACCESS_REG, tte.tte_data);
116	membar(Sync);
117}
118
119static __inline void
120tlb_itlb_page_demap(u_long ctx, vm_offset_t va)
121{
122	if (ctx == TLB_CTX_KERNEL) {
123		stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE,
124		    ASI_IMMU_DEMAP, 0);
125		flush(KERNBASE);
126	} else {
127		stxa(AA_DMMU_SCXR, ASI_DMMU, ctx);
128		membar(Sync);
129		stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_SECONDARY | TLB_DEMAP_PAGE,
130		    ASI_IMMU_DEMAP, 0);
131		stxa(AA_DMMU_SCXR, ASI_DMMU, 0);
132		/* flush probably not needed. */
133		membar(Sync);
134	}
135}
136
137static __inline void
138tlb_itlb_store(vm_offset_t va, u_long ctx, struct tte tte)
139{
140	stxa(AA_IMMU_TAR, ASI_IMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
141	stxa(0, ASI_ITLB_DATA_IN_REG, tte.tte_data);
142	if (ctx == TLB_CTX_KERNEL)
143		flush(va);
144	else {
145		/*
146		 * flush probably not needed and impossible here, no access to
147		 * user page.
148		 */
149		membar(Sync);
150	}
151}
152
153static __inline void
154tlb_itlb_store_slot(vm_offset_t va, u_long ctx, struct tte tte, int slot)
155{
156	stxa(AA_IMMU_TAR, ASI_IMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
157	stxa(TLB_DAR_SLOT(slot), ASI_ITLB_DATA_ACCESS_REG, tte.tte_data);
158	flush(va);
159}
160
161static __inline void
162tlb_page_demap(u_int tlb, u_int ctx, vm_offset_t va)
163{
164	if (tlb & TLB_DTLB)
165		tlb_dtlb_page_demap(ctx, va);
166	if (tlb & TLB_ITLB)
167		tlb_itlb_page_demap(ctx, va);
168}
169
170static __inline void
171tlb_store(u_int tlb, vm_offset_t va, u_long ctx, struct tte tte)
172{
173	if (tlb & TLB_DTLB)
174		tlb_dtlb_store(va, ctx, tte);
175	if (tlb & TLB_ITLB)
176		tlb_itlb_store(va, ctx, tte);
177}
178
179static __inline void
180tlb_store_slot(u_int tlb, vm_offset_t va, u_long ctx, struct tte tte, int slot)
181{
182	if (tlb & TLB_DTLB)
183		tlb_dtlb_store_slot(va, ctx, tte, slot);
184	if (tlb & TLB_ITLB)
185		tlb_itlb_store_slot(va, ctx, tte, slot);
186}
187
188#endif /* !_MACHINE_TLB_H_ */
189