tlb.h revision 91170
180709Sjake/*- 280709Sjake * Copyright (c) 2001 Jake Burkholder. 380709Sjake * All rights reserved. 480709Sjake * 580709Sjake * Redistribution and use in source and binary forms, with or without 680709Sjake * modification, are permitted provided that the following conditions 780709Sjake * are met: 880709Sjake * 1. Redistributions of source code must retain the above copyright 980709Sjake * notice, this list of conditions and the following disclaimer. 1080709Sjake * 2. Redistributions in binary form must reproduce the above copyright 1180709Sjake * notice, this list of conditions and the following disclaimer in the 1280709Sjake * documentation and/or other materials provided with the distribution. 1380709Sjake * 1481334Sobrien * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1580709Sjake * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1680709Sjake * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1781334Sobrien * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1880709Sjake * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1980709Sjake * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2080709Sjake * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2180709Sjake * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2280709Sjake * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2380709Sjake * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2480709Sjake * SUCH DAMAGE. 2580709Sjake * 2680709Sjake * $FreeBSD: head/sys/sparc64/include/tlb.h 91170 2002-02-23 20:59:35Z jake $ 2780709Sjake */ 2880709Sjake 2980709Sjake#ifndef _MACHINE_TLB_H_ 3080709Sjake#define _MACHINE_TLB_H_ 3180709Sjake 3280709Sjake#define TLB_SLOT_COUNT 64 3380709Sjake 3480709Sjake#define TLB_SLOT_TSB_KERNEL_MIN 60 /* XXX */ 3580709Sjake#define TLB_SLOT_TSB_USER_PRIMARY 61 3680709Sjake#define TLB_SLOT_TSB_USER_SECONDARY 62 3780709Sjake#define TLB_SLOT_KERNEL 63 3880709Sjake 3980709Sjake#define TLB_DAR_SLOT_SHIFT (3) 4080709Sjake#define TLB_DAR_SLOT(slot) ((slot) << TLB_DAR_SLOT_SHIFT) 4180709Sjake 4280709Sjake#define TLB_TAR_VA(va) ((va) & ~PAGE_MASK) 4381176Sjake#define TLB_TAR_CTX(ctx) ((ctx) & PAGE_MASK) 4480709Sjake 4580709Sjake#define TLB_DEMAP_ID_SHIFT (4) 4680709Sjake#define TLB_DEMAP_ID_PRIMARY (0) 4780709Sjake#define TLB_DEMAP_ID_SECONDARY (1) 4880709Sjake#define TLB_DEMAP_ID_NUCLEUS (2) 4980709Sjake 5080709Sjake#define TLB_DEMAP_TYPE_SHIFT (6) 5180709Sjake#define TLB_DEMAP_TYPE_PAGE (0) 5280709Sjake#define TLB_DEMAP_TYPE_CONTEXT (1) 5380709Sjake 5480709Sjake#define TLB_DEMAP_VA(va) ((va) & ~PAGE_MASK) 5580709Sjake#define TLB_DEMAP_ID(id) ((id) << TLB_DEMAP_ID_SHIFT) 5680709Sjake#define TLB_DEMAP_TYPE(type) ((type) << TLB_DEMAP_TYPE_SHIFT) 5780709Sjake 5880709Sjake#define TLB_DEMAP_PAGE (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_PAGE)) 5980709Sjake#define TLB_DEMAP_CONTEXT (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_CONTEXT)) 6080709Sjake 6180709Sjake#define TLB_DEMAP_PRIMARY (TLB_DEMAP_ID(TLB_DEMAP_ID_PRIMARY)) 6280709Sjake#define TLB_DEMAP_SECONDARY (TLB_DEMAP_ID(TLB_DEMAP_ID_SECONDARY)) 6380709Sjake#define TLB_DEMAP_NUCLEUS (TLB_DEMAP_ID(TLB_DEMAP_ID_NUCLEUS)) 6480709Sjake 6580709Sjake#define TLB_CTX_KERNEL (0) 6680709Sjake 6780709Sjake#define TLB_DTLB (1 << 0) 6880709Sjake#define TLB_ITLB (1 << 1) 6980709Sjake 7081176Sjake#define MMU_SFSR_ASI_SHIFT (16) 7181176Sjake#define MMU_SFSR_FT_SHIFT (7) 7281176Sjake#define MMU_SFSR_E_SHIFT (6) 7381176Sjake#define MMU_SFSR_CT_SHIFT (4) 7481176Sjake#define MMU_SFSR_PR_SHIFT (3) 7581176Sjake#define MMU_SFSR_W_SHIFT (2) 7681176Sjake#define MMU_SFSR_OW_SHIFT (1) 7781176Sjake#define MMU_SFSR_FV_SHIFT (0) 7881176Sjake 7981176Sjake#define MMU_SFSR_ASI_SIZE (8) 8081176Sjake#define MMU_SFSR_FT_SIZE (6) 8181176Sjake#define MMU_SFSR_CT_SIZE (2) 8281176Sjake 8381176Sjake#define MMU_SFSR_W (1L << MMU_SFSR_W_SHIFT) 8481176Sjake 8588629Sjake/* 8688629Sjake * Some tlb operations must be atomical, so no interrupt or trap can be allowed 8788629Sjake * while they are in progress. Traps should not happen, but interrupts need to 8888629Sjake * be explicitely disabled. critical_enter() cannot be used here, since it only 8988629Sjake * disables soft interrupts. 9088629Sjake * XXX: is something like this needed elsewhere, too? 9188629Sjake */ 9288629Sjake 9380709Sjakestatic __inline void 9488629Sjaketlb_dtlb_context_primary_demap(void) 9588629Sjake{ 9688629Sjake stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_DMMU_DEMAP, 0); 9788629Sjake membar(Sync); 9888629Sjake} 9988629Sjake 10088629Sjakestatic __inline void 10181377Sjaketlb_dtlb_page_demap(u_long ctx, vm_offset_t va) 10280709Sjake{ 10380709Sjake if (ctx == TLB_CTX_KERNEL) { 10480709Sjake stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE, 10580709Sjake ASI_DMMU_DEMAP, 0); 10680709Sjake membar(Sync); 10781377Sjake } else { 10881377Sjake stxa(AA_DMMU_SCXR, ASI_DMMU, ctx); 10981377Sjake membar(Sync); 11081377Sjake stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_SECONDARY | TLB_DEMAP_PAGE, 11181377Sjake ASI_DMMU_DEMAP, 0); 11288629Sjake membar(Sync); 11381377Sjake stxa(AA_DMMU_SCXR, ASI_DMMU, 0); 11481377Sjake membar(Sync); 11581377Sjake } 11680709Sjake} 11780709Sjake 11880709Sjakestatic __inline void 11981377Sjaketlb_dtlb_store(vm_offset_t va, u_long ctx, struct tte tte) 12080709Sjake{ 12188629Sjake u_long pst; 12288629Sjake 12391170Sjake pst = intr_disable(); 12481176Sjake stxa(AA_DMMU_TAR, ASI_DMMU, 12581377Sjake TLB_TAR_VA(va) | TLB_TAR_CTX(ctx)); 12680709Sjake stxa(0, ASI_DTLB_DATA_IN_REG, tte.tte_data); 12780709Sjake membar(Sync); 12891170Sjake intr_restore(pst); 12980709Sjake} 13080709Sjake 13180709Sjakestatic __inline void 13281377Sjaketlb_dtlb_store_slot(vm_offset_t va, u_long ctx, struct tte tte, int slot) 13380709Sjake{ 13488629Sjake u_long pst; 13588629Sjake 13691170Sjake pst = intr_disable(); 13781377Sjake stxa(AA_DMMU_TAR, ASI_DMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx)); 13880709Sjake stxa(TLB_DAR_SLOT(slot), ASI_DTLB_DATA_ACCESS_REG, tte.tte_data); 13980709Sjake membar(Sync); 14091170Sjake intr_restore(pst); 14180709Sjake} 14280709Sjake 14380709Sjakestatic __inline void 14488629Sjaketlb_itlb_context_primary_demap(void) 14588629Sjake{ 14688629Sjake stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_IMMU_DEMAP, 0); 14788629Sjake membar(Sync); 14888629Sjake} 14988629Sjake 15088629Sjakestatic __inline void 15181377Sjaketlb_itlb_page_demap(u_long ctx, vm_offset_t va) 15280709Sjake{ 15380709Sjake if (ctx == TLB_CTX_KERNEL) { 15480709Sjake stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE, 15580709Sjake ASI_IMMU_DEMAP, 0); 15680709Sjake flush(KERNBASE); 15781377Sjake } else { 15881377Sjake stxa(AA_DMMU_SCXR, ASI_DMMU, ctx); 15981377Sjake membar(Sync); 16081377Sjake stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_SECONDARY | TLB_DEMAP_PAGE, 16181377Sjake ASI_IMMU_DEMAP, 0); 16288629Sjake membar(Sync); 16381377Sjake stxa(AA_DMMU_SCXR, ASI_DMMU, 0); 16481377Sjake /* flush probably not needed. */ 16581377Sjake membar(Sync); 16681377Sjake } 16780709Sjake} 16880709Sjake 16980709Sjakestatic __inline void 17081377Sjaketlb_itlb_store(vm_offset_t va, u_long ctx, struct tte tte) 17180709Sjake{ 17288629Sjake u_long pst; 17388629Sjake 17491170Sjake pst = intr_disable(); 17581377Sjake stxa(AA_IMMU_TAR, ASI_IMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx)); 17681377Sjake stxa(0, ASI_ITLB_DATA_IN_REG, tte.tte_data); 17781377Sjake if (ctx == TLB_CTX_KERNEL) 17881377Sjake flush(va); 17981377Sjake else { 18081377Sjake /* 18181377Sjake * flush probably not needed and impossible here, no access to 18281377Sjake * user page. 18381377Sjake */ 18481377Sjake membar(Sync); 18581377Sjake } 18691170Sjake intr_restore(pst); 18780709Sjake} 18880709Sjake 18980709Sjakestatic __inline void 19088629Sjaketlb_context_primary_demap(u_int tlb) 19188629Sjake{ 19288629Sjake if (tlb & TLB_DTLB) 19388629Sjake tlb_dtlb_context_primary_demap(); 19488629Sjake if (tlb & TLB_ITLB) 19588629Sjake tlb_itlb_context_primary_demap(); 19688629Sjake} 19788629Sjake 19888629Sjakestatic __inline void 19981377Sjaketlb_itlb_store_slot(vm_offset_t va, u_long ctx, struct tte tte, int slot) 20080709Sjake{ 20188629Sjake u_long pst; 20288629Sjake 20391170Sjake pst = intr_disable(); 20481377Sjake stxa(AA_IMMU_TAR, ASI_IMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx)); 20580709Sjake stxa(TLB_DAR_SLOT(slot), ASI_ITLB_DATA_ACCESS_REG, tte.tte_data); 20680709Sjake flush(va); 20791170Sjake intr_restore(pst); 20880709Sjake} 20980709Sjake 21080709Sjakestatic __inline void 21180709Sjaketlb_page_demap(u_int tlb, u_int ctx, vm_offset_t va) 21280709Sjake{ 21380709Sjake if (tlb & TLB_DTLB) 21480709Sjake tlb_dtlb_page_demap(ctx, va); 21580709Sjake if (tlb & TLB_ITLB) 21680709Sjake tlb_itlb_page_demap(ctx, va); 21780709Sjake} 21880709Sjake 21980709Sjakestatic __inline void 22081377Sjaketlb_store(u_int tlb, vm_offset_t va, u_long ctx, struct tte tte) 22180709Sjake{ 22280709Sjake if (tlb & TLB_DTLB) 22381377Sjake tlb_dtlb_store(va, ctx, tte); 22480709Sjake if (tlb & TLB_ITLB) 22581377Sjake tlb_itlb_store(va, ctx, tte); 22680709Sjake} 22780709Sjake 22880709Sjakestatic __inline void 22981377Sjaketlb_store_slot(u_int tlb, vm_offset_t va, u_long ctx, struct tte tte, int slot) 23080709Sjake{ 23180709Sjake if (tlb & TLB_DTLB) 23281377Sjake tlb_dtlb_store_slot(va, ctx, tte, slot); 23380709Sjake if (tlb & TLB_ITLB) 23481377Sjake tlb_itlb_store_slot(va, ctx, tte, slot); 23580709Sjake} 23680709Sjake 23780709Sjake#endif /* !_MACHINE_TLB_H_ */ 238