tlb.h revision 88629
180709Sjake/*- 280709Sjake * Copyright (c) 2001 Jake Burkholder. 380709Sjake * All rights reserved. 480709Sjake * 580709Sjake * Redistribution and use in source and binary forms, with or without 680709Sjake * modification, are permitted provided that the following conditions 780709Sjake * are met: 880709Sjake * 1. Redistributions of source code must retain the above copyright 980709Sjake * notice, this list of conditions and the following disclaimer. 1080709Sjake * 2. Redistributions in binary form must reproduce the above copyright 1180709Sjake * notice, this list of conditions and the following disclaimer in the 1280709Sjake * documentation and/or other materials provided with the distribution. 1380709Sjake * 1481334Sobrien * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1580709Sjake * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1680709Sjake * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1781334Sobrien * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1880709Sjake * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1980709Sjake * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2080709Sjake * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2180709Sjake * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2280709Sjake * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2380709Sjake * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2480709Sjake * SUCH DAMAGE. 2580709Sjake * 2680709Sjake * $FreeBSD: head/sys/sparc64/include/tlb.h 88629 2001-12-29 07:07:35Z jake $ 2780709Sjake */ 2880709Sjake 2980709Sjake#ifndef _MACHINE_TLB_H_ 3080709Sjake#define _MACHINE_TLB_H_ 3180709Sjake 3280709Sjake#define TLB_SLOT_COUNT 64 3380709Sjake 3480709Sjake#define TLB_SLOT_TSB_KERNEL_MIN 60 /* XXX */ 3580709Sjake#define TLB_SLOT_TSB_USER_PRIMARY 61 3680709Sjake#define TLB_SLOT_TSB_USER_SECONDARY 62 3780709Sjake#define TLB_SLOT_KERNEL 63 3880709Sjake 3980709Sjake#define TLB_DAR_SLOT_SHIFT (3) 4080709Sjake#define TLB_DAR_SLOT(slot) ((slot) << TLB_DAR_SLOT_SHIFT) 4180709Sjake 4280709Sjake#define TLB_TAR_VA(va) ((va) & ~PAGE_MASK) 4381176Sjake#define TLB_TAR_CTX(ctx) ((ctx) & PAGE_MASK) 4480709Sjake 4580709Sjake#define TLB_DEMAP_ID_SHIFT (4) 4680709Sjake#define TLB_DEMAP_ID_PRIMARY (0) 4780709Sjake#define TLB_DEMAP_ID_SECONDARY (1) 4880709Sjake#define TLB_DEMAP_ID_NUCLEUS (2) 4980709Sjake 5080709Sjake#define TLB_DEMAP_TYPE_SHIFT (6) 5180709Sjake#define TLB_DEMAP_TYPE_PAGE (0) 5280709Sjake#define TLB_DEMAP_TYPE_CONTEXT (1) 5380709Sjake 5480709Sjake#define TLB_DEMAP_VA(va) ((va) & ~PAGE_MASK) 5580709Sjake#define TLB_DEMAP_ID(id) ((id) << TLB_DEMAP_ID_SHIFT) 5680709Sjake#define TLB_DEMAP_TYPE(type) ((type) << TLB_DEMAP_TYPE_SHIFT) 5780709Sjake 5880709Sjake#define TLB_DEMAP_PAGE (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_PAGE)) 5980709Sjake#define TLB_DEMAP_CONTEXT (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_CONTEXT)) 6080709Sjake 6180709Sjake#define TLB_DEMAP_PRIMARY (TLB_DEMAP_ID(TLB_DEMAP_ID_PRIMARY)) 6280709Sjake#define TLB_DEMAP_SECONDARY (TLB_DEMAP_ID(TLB_DEMAP_ID_SECONDARY)) 6380709Sjake#define TLB_DEMAP_NUCLEUS (TLB_DEMAP_ID(TLB_DEMAP_ID_NUCLEUS)) 6480709Sjake 6580709Sjake#define TLB_CTX_KERNEL (0) 6680709Sjake 6780709Sjake#define TLB_DTLB (1 << 0) 6880709Sjake#define TLB_ITLB (1 << 1) 6980709Sjake 7081176Sjake#define MMU_SFSR_ASI_SHIFT (16) 7181176Sjake#define MMU_SFSR_FT_SHIFT (7) 7281176Sjake#define MMU_SFSR_E_SHIFT (6) 7381176Sjake#define MMU_SFSR_CT_SHIFT (4) 7481176Sjake#define MMU_SFSR_PR_SHIFT (3) 7581176Sjake#define MMU_SFSR_W_SHIFT (2) 7681176Sjake#define MMU_SFSR_OW_SHIFT (1) 7781176Sjake#define MMU_SFSR_FV_SHIFT (0) 7881176Sjake 7981176Sjake#define MMU_SFSR_ASI_SIZE (8) 8081176Sjake#define MMU_SFSR_FT_SIZE (6) 8181176Sjake#define MMU_SFSR_CT_SIZE (2) 8281176Sjake 8381176Sjake#define MMU_SFSR_W (1L << MMU_SFSR_W_SHIFT) 8481176Sjake 8588629Sjake/* 8688629Sjake * Some tlb operations must be atomical, so no interrupt or trap can be allowed 8788629Sjake * while they are in progress. Traps should not happen, but interrupts need to 8888629Sjake * be explicitely disabled. critical_enter() cannot be used here, since it only 8988629Sjake * disables soft interrupts. 9088629Sjake * XXX: is something like this needed elsewhere, too? 9188629Sjake */ 9288629Sjake#define TLB_ATOMIC_START(s) do { \ 9388629Sjake (s) = rdpr(pstate); \ 9488629Sjake wrpr(pstate, (s) & ~PSTATE_IE, 0); \ 9588629Sjake} while (0) 9688629Sjake#define TLB_ATOMIC_END(s) wrpr(pstate, (s), 0) 9788629Sjake 9880709Sjakestatic __inline void 9988629Sjaketlb_dtlb_context_primary_demap(void) 10088629Sjake{ 10188629Sjake stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_DMMU_DEMAP, 0); 10288629Sjake membar(Sync); 10388629Sjake} 10488629Sjake 10588629Sjakestatic __inline void 10681377Sjaketlb_dtlb_page_demap(u_long ctx, vm_offset_t va) 10780709Sjake{ 10880709Sjake if (ctx == TLB_CTX_KERNEL) { 10980709Sjake stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE, 11080709Sjake ASI_DMMU_DEMAP, 0); 11180709Sjake membar(Sync); 11281377Sjake } else { 11381377Sjake stxa(AA_DMMU_SCXR, ASI_DMMU, ctx); 11481377Sjake membar(Sync); 11581377Sjake stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_SECONDARY | TLB_DEMAP_PAGE, 11681377Sjake ASI_DMMU_DEMAP, 0); 11788629Sjake membar(Sync); 11881377Sjake stxa(AA_DMMU_SCXR, ASI_DMMU, 0); 11981377Sjake membar(Sync); 12081377Sjake } 12180709Sjake} 12280709Sjake 12380709Sjakestatic __inline void 12481377Sjaketlb_dtlb_store(vm_offset_t va, u_long ctx, struct tte tte) 12580709Sjake{ 12688629Sjake u_long pst; 12788629Sjake 12888629Sjake TLB_ATOMIC_START(pst); 12981176Sjake stxa(AA_DMMU_TAR, ASI_DMMU, 13081377Sjake TLB_TAR_VA(va) | TLB_TAR_CTX(ctx)); 13180709Sjake stxa(0, ASI_DTLB_DATA_IN_REG, tte.tte_data); 13280709Sjake membar(Sync); 13388629Sjake TLB_ATOMIC_END(pst); 13480709Sjake} 13580709Sjake 13680709Sjakestatic __inline void 13781377Sjaketlb_dtlb_store_slot(vm_offset_t va, u_long ctx, struct tte tte, int slot) 13880709Sjake{ 13988629Sjake u_long pst; 14088629Sjake 14188629Sjake TLB_ATOMIC_START(pst); 14281377Sjake stxa(AA_DMMU_TAR, ASI_DMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx)); 14380709Sjake stxa(TLB_DAR_SLOT(slot), ASI_DTLB_DATA_ACCESS_REG, tte.tte_data); 14480709Sjake membar(Sync); 14588629Sjake TLB_ATOMIC_END(pst); 14680709Sjake} 14780709Sjake 14880709Sjakestatic __inline void 14988629Sjaketlb_itlb_context_primary_demap(void) 15088629Sjake{ 15188629Sjake stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_IMMU_DEMAP, 0); 15288629Sjake membar(Sync); 15388629Sjake} 15488629Sjake 15588629Sjakestatic __inline void 15681377Sjaketlb_itlb_page_demap(u_long ctx, vm_offset_t va) 15780709Sjake{ 15880709Sjake if (ctx == TLB_CTX_KERNEL) { 15980709Sjake stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE, 16080709Sjake ASI_IMMU_DEMAP, 0); 16180709Sjake flush(KERNBASE); 16281377Sjake } else { 16381377Sjake stxa(AA_DMMU_SCXR, ASI_DMMU, ctx); 16481377Sjake membar(Sync); 16581377Sjake stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_SECONDARY | TLB_DEMAP_PAGE, 16681377Sjake ASI_IMMU_DEMAP, 0); 16788629Sjake membar(Sync); 16881377Sjake stxa(AA_DMMU_SCXR, ASI_DMMU, 0); 16981377Sjake /* flush probably not needed. */ 17081377Sjake membar(Sync); 17181377Sjake } 17280709Sjake} 17380709Sjake 17480709Sjakestatic __inline void 17581377Sjaketlb_itlb_store(vm_offset_t va, u_long ctx, struct tte tte) 17680709Sjake{ 17788629Sjake u_long pst; 17888629Sjake 17988629Sjake TLB_ATOMIC_START(pst); 18081377Sjake stxa(AA_IMMU_TAR, ASI_IMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx)); 18181377Sjake stxa(0, ASI_ITLB_DATA_IN_REG, tte.tte_data); 18281377Sjake if (ctx == TLB_CTX_KERNEL) 18381377Sjake flush(va); 18481377Sjake else { 18581377Sjake /* 18681377Sjake * flush probably not needed and impossible here, no access to 18781377Sjake * user page. 18881377Sjake */ 18981377Sjake membar(Sync); 19081377Sjake } 19188629Sjake TLB_ATOMIC_END(pst); 19280709Sjake} 19380709Sjake 19480709Sjakestatic __inline void 19588629Sjaketlb_context_primary_demap(u_int tlb) 19688629Sjake{ 19788629Sjake if (tlb & TLB_DTLB) 19888629Sjake tlb_dtlb_context_primary_demap(); 19988629Sjake if (tlb & TLB_ITLB) 20088629Sjake tlb_itlb_context_primary_demap(); 20188629Sjake} 20288629Sjake 20388629Sjakestatic __inline void 20481377Sjaketlb_itlb_store_slot(vm_offset_t va, u_long ctx, struct tte tte, int slot) 20580709Sjake{ 20688629Sjake u_long pst; 20788629Sjake 20888629Sjake TLB_ATOMIC_START(pst); 20981377Sjake stxa(AA_IMMU_TAR, ASI_IMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx)); 21080709Sjake stxa(TLB_DAR_SLOT(slot), ASI_ITLB_DATA_ACCESS_REG, tte.tte_data); 21180709Sjake flush(va); 21288629Sjake TLB_ATOMIC_END(pst); 21380709Sjake} 21480709Sjake 21580709Sjakestatic __inline void 21680709Sjaketlb_page_demap(u_int tlb, u_int ctx, vm_offset_t va) 21780709Sjake{ 21880709Sjake if (tlb & TLB_DTLB) 21980709Sjake tlb_dtlb_page_demap(ctx, va); 22080709Sjake if (tlb & TLB_ITLB) 22180709Sjake tlb_itlb_page_demap(ctx, va); 22280709Sjake} 22380709Sjake 22480709Sjakestatic __inline void 22581377Sjaketlb_store(u_int tlb, vm_offset_t va, u_long ctx, struct tte tte) 22680709Sjake{ 22780709Sjake if (tlb & TLB_DTLB) 22881377Sjake tlb_dtlb_store(va, ctx, tte); 22980709Sjake if (tlb & TLB_ITLB) 23081377Sjake tlb_itlb_store(va, ctx, tte); 23180709Sjake} 23280709Sjake 23380709Sjakestatic __inline void 23481377Sjaketlb_store_slot(u_int tlb, vm_offset_t va, u_long ctx, struct tte tte, int slot) 23580709Sjake{ 23680709Sjake if (tlb & TLB_DTLB) 23781377Sjake tlb_dtlb_store_slot(va, ctx, tte, slot); 23880709Sjake if (tlb & TLB_ITLB) 23981377Sjake tlb_itlb_store_slot(va, ctx, tte, slot); 24080709Sjake} 24180709Sjake 24280709Sjake#endif /* !_MACHINE_TLB_H_ */ 243