tlb.h revision 81334 
1/*-
2 * Copyright (c) 2001 Jake Burkholder.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/sparc64/include/tlb.h 81334 2001-08-09 02:09:34Z obrien $
27 */
28
29#ifndef	_MACHINE_TLB_H_
30#define	_MACHINE_TLB_H_
31
32#define	TLB_SLOT_COUNT			64
33
34#define	TLB_SLOT_TSB_KERNEL_MIN		60	/* XXX */
35#define	TLB_SLOT_TSB_USER_PRIMARY	61
36#define	TLB_SLOT_TSB_USER_SECONDARY	62
37#define	TLB_SLOT_KERNEL			63
38
39#define	TLB_DAR_SLOT_SHIFT		(3)
40#define	TLB_DAR_SLOT(slot)		((slot) << TLB_DAR_SLOT_SHIFT)
41
42#define	TLB_TAR_VA(va)			((va) & ~PAGE_MASK)
43#define	TLB_TAR_CTX(ctx)		((ctx) & PAGE_MASK)
44
45#define	TLB_DEMAP_ID_SHIFT		(4)
46#define	TLB_DEMAP_ID_PRIMARY		(0)
47#define	TLB_DEMAP_ID_SECONDARY		(1)
48#define	TLB_DEMAP_ID_NUCLEUS		(2)
49
50#define	TLB_DEMAP_TYPE_SHIFT		(6)
51#define	TLB_DEMAP_TYPE_PAGE		(0)
52#define	TLB_DEMAP_TYPE_CONTEXT		(1)
53
54#define	TLB_DEMAP_VA(va)		((va) & ~PAGE_MASK)
55#define	TLB_DEMAP_ID(id)		((id) << TLB_DEMAP_ID_SHIFT)
56#define	TLB_DEMAP_TYPE(type)		((type) << TLB_DEMAP_TYPE_SHIFT)
57
58#define	TLB_DEMAP_PAGE			(TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_PAGE))
59#define	TLB_DEMAP_CONTEXT		(TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_CONTEXT))
60
61#define	TLB_DEMAP_PRIMARY		(TLB_DEMAP_ID(TLB_DEMAP_ID_PRIMARY))
62#define	TLB_DEMAP_SECONDARY		(TLB_DEMAP_ID(TLB_DEMAP_ID_SECONDARY))
63#define	TLB_DEMAP_NUCLEUS		(TLB_DEMAP_ID(TLB_DEMAP_ID_NUCLEUS))
64
65#define	TLB_CTX_KERNEL			(0)
66
67#define	TLB_DTLB			(1 << 0)
68#define	TLB_ITLB			(1 << 1)
69
70#define	MMU_SFSR_ASI_SHIFT		(16)
71#define	MMU_SFSR_FT_SHIFT		(7)
72#define	MMU_SFSR_E_SHIFT		(6)
73#define	MMU_SFSR_CT_SHIFT		(4)
74#define	MMU_SFSR_PR_SHIFT		(3)
75#define	MMU_SFSR_W_SHIFT		(2)
76#define	MMU_SFSR_OW_SHIFT		(1)
77#define	MMU_SFSR_FV_SHIFT		(0)
78
79#define	MMU_SFSR_ASI_SIZE		(8)
80#define	MMU_SFSR_FT_SIZE		(6)
81#define	MMU_SFSR_CT_SIZE		(2)
82
83#define	MMU_SFSR_W			(1L << MMU_SFSR_W_SHIFT)
84
85static __inline void
86tlb_dtlb_page_demap(u_int ctx, vm_offset_t va)
87{
88	if (ctx == TLB_CTX_KERNEL) {
89		stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE,
90		    ASI_DMMU_DEMAP, 0);
91		membar(Sync);
92	} else
93		TODO;
94}
95
96static __inline void
97tlb_dtlb_store(vm_offset_t va, struct tte tte)
98{
99	stxa(AA_DMMU_TAR, ASI_DMMU,
100	    TLB_TAR_VA(va) | TLB_TAR_CTX(tte_get_ctx(tte)));
101	stxa(0, ASI_DTLB_DATA_IN_REG, tte.tte_data);
102	membar(Sync);
103}
104
105static __inline void
106tlb_dtlb_store_slot(vm_offset_t va, struct tte tte, int slot)
107{
108	stxa(AA_DMMU_TAR, ASI_DMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(0));
109	stxa(TLB_DAR_SLOT(slot), ASI_DTLB_DATA_ACCESS_REG, tte.tte_data);
110	membar(Sync);
111}
112
113static __inline void
114tlb_itlb_page_demap(u_int ctx, vm_offset_t va)
115{
116	if (ctx == TLB_CTX_KERNEL) {
117		stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE,
118		    ASI_IMMU_DEMAP, 0);
119		flush(KERNBASE);
120	} else
121		TODO;
122}
123
124static __inline void
125tlb_itlb_store(vm_offset_t va, struct tte tte)
126{
127	TODO;
128}
129
130static __inline void
131tlb_itlb_store_slot(vm_offset_t va, struct tte tte, int slot)
132{
133	stxa(AA_IMMU_TAR, ASI_IMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(0));
134	stxa(TLB_DAR_SLOT(slot), ASI_ITLB_DATA_ACCESS_REG, tte.tte_data);
135	flush(va);
136}
137
138static __inline void
139tlb_page_demap(u_int tlb, u_int ctx, vm_offset_t va)
140{
141	if (tlb & TLB_DTLB)
142		tlb_dtlb_page_demap(ctx, va);
143	if (tlb & TLB_ITLB)
144		tlb_itlb_page_demap(ctx, va);
145}
146
147static __inline void
148tlb_store(u_int tlb, vm_offset_t va, struct tte tte)
149{
150	if (tlb & TLB_DTLB)
151		tlb_dtlb_store(va, tte);
152	if (tlb & TLB_ITLB)
153		tlb_itlb_store(va, tte);
154}
155
156static __inline void
157tlb_store_slot(u_int tlb, vm_offset_t va, struct tte tte, int slot)
158{
159	if (tlb & TLB_DTLB)
160		tlb_dtlb_store_slot(va, tte, slot);
161	if (tlb & TLB_ITLB)
162		tlb_itlb_store_slot(va, tte, slot);
163}
164
165#endif /* !_MACHINE_TLB_H_ */
166