tlb.h revision 205258
180709Sjake/*- 280709Sjake * Copyright (c) 2001 Jake Burkholder. 3205258Smarius * Copyright (c) 2008, 2010 Marius Strobl <marius@FreeBSD.org> 480709Sjake * All rights reserved. 580709Sjake * 680709Sjake * Redistribution and use in source and binary forms, with or without 780709Sjake * modification, are permitted provided that the following conditions 880709Sjake * are met: 980709Sjake * 1. Redistributions of source code must retain the above copyright 1080709Sjake * notice, this list of conditions and the following disclaimer. 1180709Sjake * 2. Redistributions in binary form must reproduce the above copyright 1280709Sjake * notice, this list of conditions and the following disclaimer in the 1380709Sjake * documentation and/or other materials provided with the distribution. 1480709Sjake * 1581334Sobrien * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1680709Sjake * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1780709Sjake * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1881334Sobrien * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1980709Sjake * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2080709Sjake * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2180709Sjake * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2280709Sjake * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2380709Sjake * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2480709Sjake * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2580709Sjake * SUCH DAMAGE. 2680709Sjake * 2780709Sjake * $FreeBSD: head/sys/sparc64/include/tlb.h 205258 2010-03-17 20:23:14Z marius $ 2880709Sjake */ 2980709Sjake 3080709Sjake#ifndef _MACHINE_TLB_H_ 3180709Sjake#define _MACHINE_TLB_H_ 3280709Sjake 33108245Sjake#define TLB_DIRECT_ADDRESS_BITS (43) 34108245Sjake#define TLB_DIRECT_PAGE_BITS (PAGE_SHIFT_4M) 35100771Sjake 36108245Sjake#define TLB_DIRECT_ADDRESS_MASK ((1UL << TLB_DIRECT_ADDRESS_BITS) - 1) 37108245Sjake#define TLB_DIRECT_PAGE_MASK ((1UL << TLB_DIRECT_PAGE_BITS) - 1) 38108245Sjake 39205258Smarius#define TLB_PHYS_TO_DIRECT(pa) \ 40108245Sjake ((pa) | VM_MIN_DIRECT_ADDRESS) 41205258Smarius#define TLB_DIRECT_TO_PHYS(va) \ 42108245Sjake ((va) & TLB_DIRECT_ADDRESS_MASK) 43205258Smarius#define TLB_DIRECT_TO_TTE_MASK \ 44108245Sjake (TD_V | TD_4M | (TLB_DIRECT_ADDRESS_MASK - TLB_DIRECT_PAGE_MASK)) 45108245Sjake 4680709Sjake#define TLB_DAR_SLOT_SHIFT (3) 4780709Sjake#define TLB_DAR_SLOT(slot) ((slot) << TLB_DAR_SLOT_SHIFT) 4880709Sjake 4991224Sjake#define TAR_VPN_SHIFT (13) 5091224Sjake#define TAR_CTX_MASK ((1 << TAR_VPN_SHIFT) - 1) 5180709Sjake 5291224Sjake#define TLB_TAR_VA(va) ((va) & ~TAR_CTX_MASK) 5391224Sjake#define TLB_TAR_CTX(ctx) ((ctx) & TAR_CTX_MASK) 5491224Sjake 55182878Smarius#define TLB_CXR_CTX_BITS (13) 56182878Smarius#define TLB_CXR_CTX_MASK \ 57182878Smarius (((1UL << TLB_CXR_CTX_BITS) - 1) << TLB_CXR_CTX_SHIFT) 58182878Smarius#define TLB_CXR_CTX_SHIFT (0) 59182878Smarius#define TLB_CXR_PGSZ_BITS (3) 60205258Smarius#define TLB_CXR_PGSZ_MASK (~TLB_CXR_CTX_MASK) 61205258Smarius#define TLB_PCXR_N_IPGSZ0_SHIFT (53) /* SPARC64 VI, VII, VIIIfx */ 62205258Smarius#define TLB_PCXR_N_IPGSZ1_SHIFT (50) /* SPARC64 VI, VII, VIIIfx */ 63182878Smarius#define TLB_PCXR_N_PGSZ0_SHIFT (61) 64182878Smarius#define TLB_PCXR_N_PGSZ1_SHIFT (58) 65205258Smarius#define TLB_PCXR_N_PGSZ_I_SHIFT (55) /* US-IV+ */ 66205258Smarius#define TLB_PCXR_P_IPGSZ0_SHIFT (24) /* SPARC64 VI, VII, VIIIfx */ 67205258Smarius#define TLB_PCXR_P_IPGSZ1_SHIFT (27) /* SPARC64 VI, VII, VIIIfx */ 68182878Smarius#define TLB_PCXR_P_PGSZ0_SHIFT (16) 69182878Smarius#define TLB_PCXR_P_PGSZ1_SHIFT (19) 70205258Smarius/* 71205258Smarius * Note that the US-IV+ documentation appears to have TLB_PCXR_P_PGSZ_I_SHIFT 72205258Smarius * and TLB_PCXR_P_PGSZ0_SHIFT erroneously inverted. 73205258Smarius */ 74205258Smarius#define TLB_PCXR_P_PGSZ_I_SHIFT (22) /* US-IV+ */ 75182878Smarius#define TLB_SCXR_S_PGSZ1_SHIFT (19) 76182878Smarius#define TLB_SCXR_S_PGSZ0_SHIFT (16) 77182878Smarius 78182878Smarius#define TLB_TAE_PGSZ_BITS (3) 79182878Smarius#define TLB_TAE_PGSZ0_MASK \ 80182878Smarius (((1UL << TLB_TAE_PGSZ_BITS) - 1) << TLB_TAE_PGSZ0_SHIFT) 81182878Smarius#define TLB_TAE_PGSZ1_MASK \ 82182878Smarius (((1UL << TLB_TAE_PGSZ_BITS) - 1) << TLB_TAE_PGSZ1_SHIFT) 83182878Smarius#define TLB_TAE_PGSZ0_SHIFT (16) 84182878Smarius#define TLB_TAE_PGSZ1_SHIFT (19) 85182878Smarius 8680709Sjake#define TLB_DEMAP_ID_SHIFT (4) 8780709Sjake#define TLB_DEMAP_ID_PRIMARY (0) 8880709Sjake#define TLB_DEMAP_ID_SECONDARY (1) 8980709Sjake#define TLB_DEMAP_ID_NUCLEUS (2) 9080709Sjake 9180709Sjake#define TLB_DEMAP_TYPE_SHIFT (6) 9280709Sjake#define TLB_DEMAP_TYPE_PAGE (0) 9380709Sjake#define TLB_DEMAP_TYPE_CONTEXT (1) 94205258Smarius#define TLB_DEMAP_TYPE_ALL (2) /* US-III and beyond only */ 9580709Sjake 9680709Sjake#define TLB_DEMAP_VA(va) ((va) & ~PAGE_MASK) 9780709Sjake#define TLB_DEMAP_ID(id) ((id) << TLB_DEMAP_ID_SHIFT) 9880709Sjake#define TLB_DEMAP_TYPE(type) ((type) << TLB_DEMAP_TYPE_SHIFT) 9980709Sjake 10080709Sjake#define TLB_DEMAP_PAGE (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_PAGE)) 10180709Sjake#define TLB_DEMAP_CONTEXT (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_CONTEXT)) 102176994Smarius#define TLB_DEMAP_ALL (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_ALL)) 10380709Sjake 10480709Sjake#define TLB_DEMAP_PRIMARY (TLB_DEMAP_ID(TLB_DEMAP_ID_PRIMARY)) 10580709Sjake#define TLB_DEMAP_SECONDARY (TLB_DEMAP_ID(TLB_DEMAP_ID_SECONDARY)) 10680709Sjake#define TLB_DEMAP_NUCLEUS (TLB_DEMAP_ID(TLB_DEMAP_ID_NUCLEUS)) 10780709Sjake 10880709Sjake#define TLB_CTX_KERNEL (0) 10991613Sjake#define TLB_CTX_USER_MIN (1) 11091613Sjake#define TLB_CTX_USER_MAX (8192) 11180709Sjake 11281176Sjake#define MMU_SFSR_ASI_SHIFT (16) 11381176Sjake#define MMU_SFSR_FT_SHIFT (7) 11481176Sjake#define MMU_SFSR_E_SHIFT (6) 11581176Sjake#define MMU_SFSR_CT_SHIFT (4) 11681176Sjake#define MMU_SFSR_PR_SHIFT (3) 11781176Sjake#define MMU_SFSR_W_SHIFT (2) 11881176Sjake#define MMU_SFSR_OW_SHIFT (1) 11981176Sjake#define MMU_SFSR_FV_SHIFT (0) 12081176Sjake 12181176Sjake#define MMU_SFSR_ASI_SIZE (8) 12281176Sjake#define MMU_SFSR_FT_SIZE (6) 12381176Sjake#define MMU_SFSR_CT_SIZE (2) 12481176Sjake 125205258Smarius#define MMU_SFSR_GET_ASI(sfsr) \ 126101955Sjake (((sfsr) >> MMU_SFSR_ASI_SHIFT) & ((1UL << MMU_SFSR_ASI_SIZE) - 1)) 127205258Smarius#define MMU_SFSR_GET_FT(sfsr) \ 128205258Smarius (((sfsr) >> MMU_SFSR_FT_SHIFT) & ((1UL << MMU_SFSR_FT_SIZE) - 1)) 129205258Smarius#define MMU_SFSR_GET_CT(sfsr) \ 130205258Smarius (((sfsr) >> MMU_SFSR_CT_SHIFT) & ((1UL << MMU_SFSR_CT_SIZE) - 1)) 131205258Smarius 132205258Smarius#define MMU_SFSR_E (1UL << MMU_SFSR_E_SHIFT) 133205258Smarius#define MMU_SFSR_PR (1UL << MMU_SFSR_PR_SHIFT) 134101955Sjake#define MMU_SFSR_W (1UL << MMU_SFSR_W_SHIFT) 135205258Smarius#define MMU_SFSR_OW (1UL << MMU_SFSR_OW_SHIFT) 136101955Sjake#define MMU_SFSR_FV (1UL << MMU_SFSR_FV_SHIFT) 13781176Sjake 138176994Smariustypedef void tlb_flush_nonlocked_t(void); 139113453Sjaketypedef void tlb_flush_user_t(void); 140113453Sjake 141113453Sjakestruct pmap; 14297445Sjakestruct tlb_entry; 14397445Sjake 144186682Smariusextern int dtlb_slots; 145186682Smariusextern int itlb_slots; 14691616Sjakeextern int kernel_tlb_slots; 14797445Sjakeextern struct tlb_entry *kernel_tlbs; 14891616Sjake 14996998Sjakevoid tlb_context_demap(struct pmap *pm); 150100718Sjakevoid tlb_page_demap(struct pmap *pm, vm_offset_t va); 15196998Sjakevoid tlb_range_demap(struct pmap *pm, vm_offset_t start, vm_offset_t end); 15288629Sjake 153176994Smariustlb_flush_nonlocked_t cheetah_tlb_flush_nonlocked; 154113453Sjaketlb_flush_user_t cheetah_tlb_flush_user; 155176994Smarius 156176994Smariustlb_flush_nonlocked_t spitfire_tlb_flush_nonlocked; 157113453Sjaketlb_flush_user_t spitfire_tlb_flush_user; 158113453Sjake 159176994Smariusextern tlb_flush_nonlocked_t *tlb_flush_nonlocked; 160113453Sjakeextern tlb_flush_user_t *tlb_flush_user; 161113453Sjake 16280709Sjake#endif /* !_MACHINE_TLB_H_ */ 163