iommuvar.h revision 90616
186230Stmm/* 286230Stmm * Copyright (c) 1999 Matthew R. Green 386230Stmm * All rights reserved. 486230Stmm * 586230Stmm * Redistribution and use in source and binary forms, with or without 686230Stmm * modification, are permitted provided that the following conditions 786230Stmm * are met: 886230Stmm * 1. Redistributions of source code must retain the above copyright 986230Stmm * notice, this list of conditions and the following disclaimer. 1086230Stmm * 2. Redistributions in binary form must reproduce the above copyright 1186230Stmm * notice, this list of conditions and the following disclaimer in the 1286230Stmm * documentation and/or other materials provided with the distribution. 1386230Stmm * 3. The name of the author may not be used to endorse or promote products 1486230Stmm * derived from this software without specific prior written permission. 1586230Stmm * 1686230Stmm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1786230Stmm * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1886230Stmm * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1986230Stmm * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2086230Stmm * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 2186230Stmm * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 2286230Stmm * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 2386230Stmm * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 2486230Stmm * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2586230Stmm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2686230Stmm * SUCH DAMAGE. 2786230Stmm * 2890616Stmm * from: NetBSD: iommuvar.h,v 1.9 2001/07/20 00:07:13 eeh Exp 2986230Stmm * 3086230Stmm * $FreeBSD: head/sys/sparc64/include/iommuvar.h 90616 2002-02-13 15:59:17Z tmm $ 3186230Stmm */ 3286230Stmm 3386230Stmm#ifndef _MACHINE_IOMMUVAR_H_ 3486230Stmm#define _MACHINE_IOMMUVAR_H_ 3586230Stmm 3690616Stmm#define IO_PAGE_SIZE PAGE_SIZE_8K 3790616Stmm#define IO_PAGE_MASK PAGE_MASK_8K 3890616Stmm#define IO_PAGE_SHIFT PAGE_SHIFT_8K 3990616Stmm#define round_io_page(x) round_page(x) 4090616Stmm#define trunc_io_page(x) trunc_page(x) 4190616Stmm 4286230Stmm/* 4386230Stmm * per-IOMMU state 4486230Stmm */ 4586230Stmmstruct iommu_state { 4686230Stmm vm_offset_t is_ptsb; /* TSB physical address */ 4786230Stmm u_int64_t *is_tsb; /* TSB virtual address */ 4886230Stmm int is_tsbsize; /* 0 = 8K, ... */ 4986230Stmm u_int64_t is_dvmabase; 5090616Stmm int64_t is_cr; /* IOMMU control register value */ 5186230Stmm struct rman is_dvma_rman; /* DVMA map for this instance */ 5286230Stmm 5390616Stmm vm_offset_t is_flushpa[2]; 5490616Stmm volatile int64_t *is_flushva[2]; 5590616Stmm /* 5690616Stmm * When a flush is completed, 64 bytes will be stored at the given 5790616Stmm * location, the first double word being 1, to indicate completion. 5890616Stmm * The lower 6 address bits are ignored, so the addresses need to be 5990616Stmm * suitably aligned; over-allocate a large enough margin to be able 6090616Stmm * to adjust it. 6190616Stmm * Two such buffers are needed. 6290616Stmm * Needs to be volatile or egcs optimizes away loads. 6390616Stmm */ 6490616Stmm volatile char is_flush[STRBUF_FLUSHSYNC_NBYTES * 3 - 1]; 6586230Stmm 6686230Stmm /* copies of our parents state, to allow us to be self contained */ 6786230Stmm bus_space_tag_t is_bustag; /* our bus tag */ 6890616Stmm bus_space_handle_t is_bushandle; 6990616Stmm bus_addr_t is_iommu; /* IOMMU registers */ 7090616Stmm bus_addr_t is_sb[2]; /* streaming buffer */ 7190616Stmm bus_addr_t is_dtag; /* tag diagnostics access */ 7290616Stmm bus_addr_t is_ddram; /* data ram diag. access */ 7390616Stmm bus_addr_t is_dqueue; /* LRU queue diag. access */ 7490616Stmm bus_addr_t is_dva; /* VA diag. register */ 7590616Stmm bus_addr_t is_dtcmp; /* tag compare diag. access */ 7686230Stmm}; 7786230Stmm 7886230Stmm/* interfaces for PCI/SBUS code */ 7986230Stmmvoid iommu_init __P((char *, struct iommu_state *, int, u_int32_t)); 8086230Stmmvoid iommu_reset __P((struct iommu_state *)); 8186230Stmmvoid iommu_enter __P((struct iommu_state *, vm_offset_t, vm_offset_t, int)); 8286230Stmmvoid iommu_remove __P((struct iommu_state *, vm_offset_t, size_t)); 8386230Stmm 8490616Stmmint iommu_dvmamap_create __P((bus_dma_tag_t, struct iommu_state *, int, 8586230Stmm bus_dmamap_t *)); 8690616Stmmint iommu_dvmamap_destroy __P((bus_dma_tag_t, struct iommu_state *, 8786230Stmm bus_dmamap_t)); 8886230Stmmint iommu_dvmamap_load __P((bus_dma_tag_t, struct iommu_state *, bus_dmamap_t, 8986230Stmm void *, bus_size_t, bus_dmamap_callback_t *, void *, int)); 9086230Stmmvoid iommu_dvmamap_unload __P((bus_dma_tag_t, struct iommu_state *, 9186230Stmm bus_dmamap_t)); 9286230Stmmvoid iommu_dvmamap_sync __P((bus_dma_tag_t, struct iommu_state *, bus_dmamap_t, 9386230Stmm bus_dmasync_op_t)); 9490616Stmmint iommu_dvmamem_alloc __P((bus_dma_tag_t, struct iommu_state *, void **, int, 9590616Stmm bus_dmamap_t *)); 9690616Stmmvoid iommu_dvmamem_free __P((bus_dma_tag_t, struct iommu_state *, void *, 9790616Stmm bus_dmamap_t)); 9886230Stmm 9986230Stmm#endif /* !_MACHINE_IOMMUVAR_H_ */ 100