iommuvar.h revision 178840
1139825Simp/*- 286230Stmm * Copyright (c) 1999 Matthew R. Green 386230Stmm * All rights reserved. 486230Stmm * 586230Stmm * Redistribution and use in source and binary forms, with or without 686230Stmm * modification, are permitted provided that the following conditions 786230Stmm * are met: 886230Stmm * 1. Redistributions of source code must retain the above copyright 986230Stmm * notice, this list of conditions and the following disclaimer. 1086230Stmm * 2. Redistributions in binary form must reproduce the above copyright 1186230Stmm * notice, this list of conditions and the following disclaimer in the 1286230Stmm * documentation and/or other materials provided with the distribution. 1386230Stmm * 3. The name of the author may not be used to endorse or promote products 1486230Stmm * derived from this software without specific prior written permission. 1586230Stmm * 1686230Stmm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1786230Stmm * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1886230Stmm * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1986230Stmm * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2086230Stmm * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 2186230Stmm * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 2286230Stmm * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 2386230Stmm * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 2486230Stmm * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2586230Stmm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2686230Stmm * SUCH DAMAGE. 2786230Stmm * 2890616Stmm * from: NetBSD: iommuvar.h,v 1.9 2001/07/20 00:07:13 eeh Exp 2986230Stmm * 3086230Stmm * $FreeBSD: head/sys/sparc64/include/iommuvar.h 178840 2008-05-07 21:22:15Z marius $ 3186230Stmm */ 3286230Stmm 3386230Stmm#ifndef _MACHINE_IOMMUVAR_H_ 34178840Smarius#define _MACHINE_IOMMUVAR_H_ 3586230Stmm 3690616Stmm#define IO_PAGE_SIZE PAGE_SIZE_8K 3790616Stmm#define IO_PAGE_MASK PAGE_MASK_8K 3890616Stmm#define IO_PAGE_SHIFT PAGE_SHIFT_8K 3990616Stmm#define round_io_page(x) round_page(x) 4090616Stmm#define trunc_io_page(x) trunc_page(x) 4190616Stmm 4286230Stmm/* 43171730Smarius * LRU queue handling for lazy resource allocation 44171730Smarius */ 45171730SmariusTAILQ_HEAD(iommu_maplruq_head, bus_dmamap); 46171730Smarius 47171730Smarius/* 48117390Stmm * Per-IOMMU state. The parenthesized comments indicate the locking strategy: 49171730Smarius * i - protected by is_mtx. 50117390Stmm * r - read-only after initialization. 51117390Stmm * * - comment refers to pointer target / target hardware registers 52117390Stmm * (for bus_addr_t). 53171730Smarius * is_maplruq is also locked by is_mtx. Elements of is_tsb may only be 54171730Smarius * accessed from functions operating on the map owning the corresponding 55171730Smarius * resource, so the locking the user is required to do to protect the 56171730Smarius * map is sufficient. 57171730Smarius * dm_reslist of all maps are locked by is_mtx as well. 58171730Smarius * is_dvma_rman has its own internal lock. 5986230Stmm */ 6086230Stmmstruct iommu_state { 61171730Smarius struct mtx is_mtx; 62171730Smarius struct rman is_dvma_rman; /* DVMA space rman */ 63171730Smarius struct iommu_maplruq_head is_maplruq; /* (i) LRU queue */ 64171730Smarius vm_paddr_t is_ptsb; /* (r) TSB physical address */ 65178840Smarius uint64_t *is_tsb; /* (*i) TSB virtual address */ 66117390Stmm int is_tsbsize; /* (r) 0 = 8K, ... */ 67178840Smarius uint64_t is_pmaxaddr; /* (r) max. physical address */ 68178840Smarius uint64_t is_dvmabase; /* (r) */ 69117390Stmm int64_t is_cr; /* (r) Control reg value */ 7086230Stmm 71117390Stmm vm_paddr_t is_flushpa[2]; /* (r) */ 72117390Stmm volatile int64_t *is_flushva[2]; /* (r, *i) */ 7390616Stmm /* 74117390Stmm * (i) 7590616Stmm * When a flush is completed, 64 bytes will be stored at the given 7690616Stmm * location, the first double word being 1, to indicate completion. 7790616Stmm * The lower 6 address bits are ignored, so the addresses need to be 7890616Stmm * suitably aligned; over-allocate a large enough margin to be able 7990616Stmm * to adjust it. 8090616Stmm * Two such buffers are needed. 8190616Stmm */ 8290616Stmm volatile char is_flush[STRBUF_FLUSHSYNC_NBYTES * 3 - 1]; 8386230Stmm 8486230Stmm /* copies of our parents state, to allow us to be self contained */ 85117390Stmm bus_space_tag_t is_bustag; /* (r) Our bus tag */ 86117390Stmm bus_space_handle_t is_bushandle; /* (r) */ 87117390Stmm bus_addr_t is_iommu; /* (r, *i) IOMMU registers */ 88117390Stmm bus_addr_t is_sb[2]; /* (r, *i) Streaming buffer */ 89117390Stmm /* Tag diagnostics access */ 90117390Stmm bus_addr_t is_dtag; /* (r, *r) */ 91117390Stmm /* Data RAM diagnostic access */ 92117390Stmm bus_addr_t is_ddram; /* (r, *r) */ 93117390Stmm /* LRU queue diag. access */ 94117390Stmm bus_addr_t is_dqueue; /* (r, *r) */ 95117390Stmm /* Virtual address diagnostics register */ 96117390Stmm bus_addr_t is_dva; /* (r, *r) */ 97117390Stmm /* Tag compare diagnostics access */ 98117390Stmm bus_addr_t is_dtcmp; /* (r, *r) */ 9986230Stmm}; 10086230Stmm 101171730Smarius/* interfaces for PCI/SBus code */ 102178840Smariusvoid iommu_init(const char *name, struct iommu_state *is, int tsbsize, 103178840Smarius uint32_t iovabase, int resvpg); 104178840Smariusvoid iommu_reset(struct iommu_state *is); 105178840Smariusvoid iommu_decode_fault(struct iommu_state *is, vm_offset_t phys); 10686230Stmm 107116541Stmmextern struct bus_dma_methods iommu_dma_methods; 10886230Stmm 10986230Stmm#endif /* !_MACHINE_IOMMUVAR_H_ */ 110