iommuvar.h revision 171730
1203288Srnoland/*- 2203288Srnoland * Copyright (c) 1999 Matthew R. Green 3203288Srnoland * All rights reserved. 4203288Srnoland * 5203288Srnoland * Redistribution and use in source and binary forms, with or without 6203288Srnoland * modification, are permitted provided that the following conditions 7203288Srnoland * are met: 8203288Srnoland * 1. Redistributions of source code must retain the above copyright 9203288Srnoland * notice, this list of conditions and the following disclaimer. 10203288Srnoland * 2. Redistributions in binary form must reproduce the above copyright 11203288Srnoland * notice, this list of conditions and the following disclaimer in the 12203288Srnoland * documentation and/or other materials provided with the distribution. 13203288Srnoland * 3. The name of the author may not be used to endorse or promote products 14203288Srnoland * derived from this software without specific prior written permission. 15203288Srnoland * 16203288Srnoland * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17203288Srnoland * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18203288Srnoland * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19203288Srnoland * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20203288Srnoland * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21203288Srnoland * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22203288Srnoland * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23203288Srnoland * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24203288Srnoland * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25203288Srnoland * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26203288Srnoland * SUCH DAMAGE. 27203288Srnoland * 28203288Srnoland * from: NetBSD: iommuvar.h,v 1.9 2001/07/20 00:07:13 eeh Exp 29203288Srnoland * 30203288Srnoland * $FreeBSD: head/sys/sparc64/include/iommuvar.h 171730 2007-08-05 11:56:44Z marius $ 31203288Srnoland */ 32203288Srnoland 33203288Srnoland#ifndef _MACHINE_IOMMUVAR_H_ 34203288Srnoland#define _MACHINE_IOMMUVAR_H_ 35203288Srnoland 36203288Srnoland#define IO_PAGE_SIZE PAGE_SIZE_8K 37203288Srnoland#define IO_PAGE_MASK PAGE_MASK_8K 38203288Srnoland#define IO_PAGE_SHIFT PAGE_SHIFT_8K 39203288Srnoland#define round_io_page(x) round_page(x) 40203288Srnoland#define trunc_io_page(x) trunc_page(x) 41203288Srnoland 42203288Srnoland/* 43203288Srnoland * LRU queue handling for lazy resource allocation 44203288Srnoland */ 45203288SrnolandTAILQ_HEAD(iommu_maplruq_head, bus_dmamap); 46203288Srnoland 47203288Srnoland/* 48203288Srnoland * Per-IOMMU state. The parenthesized comments indicate the locking strategy: 49203288Srnoland * i - protected by is_mtx. 50203288Srnoland * r - read-only after initialization. 51203288Srnoland * * - comment refers to pointer target / target hardware registers 52203288Srnoland * (for bus_addr_t). 53203288Srnoland * is_maplruq is also locked by is_mtx. Elements of is_tsb may only be 54203288Srnoland * accessed from functions operating on the map owning the corresponding 55203288Srnoland * resource, so the locking the user is required to do to protect the 56203288Srnoland * map is sufficient. 57203288Srnoland * dm_reslist of all maps are locked by is_mtx as well. 58203288Srnoland * is_dvma_rman has its own internal lock. 59203288Srnoland */ 60203288Srnolandstruct iommu_state { 61203288Srnoland struct mtx is_mtx; 62203288Srnoland struct rman is_dvma_rman; /* DVMA space rman */ 63203288Srnoland struct iommu_maplruq_head is_maplruq; /* (i) LRU queue */ 64203288Srnoland vm_paddr_t is_ptsb; /* (r) TSB physical address */ 65203288Srnoland u_int64_t *is_tsb; /* (*i) TSB virtual address */ 66 int is_tsbsize; /* (r) 0 = 8K, ... */ 67 u_int64_t is_pmaxaddr; /* (r) max. physical address */ 68 u_int64_t is_dvmabase; /* (r) */ 69 int64_t is_cr; /* (r) Control reg value */ 70 71 vm_paddr_t is_flushpa[2]; /* (r) */ 72 volatile int64_t *is_flushva[2]; /* (r, *i) */ 73 /* 74 * (i) 75 * When a flush is completed, 64 bytes will be stored at the given 76 * location, the first double word being 1, to indicate completion. 77 * The lower 6 address bits are ignored, so the addresses need to be 78 * suitably aligned; over-allocate a large enough margin to be able 79 * to adjust it. 80 * Two such buffers are needed. 81 */ 82 volatile char is_flush[STRBUF_FLUSHSYNC_NBYTES * 3 - 1]; 83 84 /* copies of our parents state, to allow us to be self contained */ 85 bus_space_tag_t is_bustag; /* (r) Our bus tag */ 86 bus_space_handle_t is_bushandle; /* (r) */ 87 bus_addr_t is_iommu; /* (r, *i) IOMMU registers */ 88 bus_addr_t is_sb[2]; /* (r, *i) Streaming buffer */ 89 /* Tag diagnostics access */ 90 bus_addr_t is_dtag; /* (r, *r) */ 91 /* Data RAM diagnostic access */ 92 bus_addr_t is_ddram; /* (r, *r) */ 93 /* LRU queue diag. access */ 94 bus_addr_t is_dqueue; /* (r, *r) */ 95 /* Virtual address diagnostics register */ 96 bus_addr_t is_dva; /* (r, *r) */ 97 /* Tag compare diagnostics access */ 98 bus_addr_t is_dtcmp; /* (r, *r) */ 99}; 100 101/* interfaces for PCI/SBus code */ 102void iommu_init(char *, struct iommu_state *, int, u_int32_t, int); 103void iommu_reset(struct iommu_state *); 104void iommu_decode_fault(struct iommu_state *, vm_offset_t); 105 106extern struct bus_dma_methods iommu_dma_methods; 107 108#endif /* !_MACHINE_IOMMUVAR_H_ */ 109