iommuvar.h revision 139825
1139825Simp/*-
286230Stmm * Copyright (c) 1999 Matthew R. Green
386230Stmm * All rights reserved.
486230Stmm *
586230Stmm * Redistribution and use in source and binary forms, with or without
686230Stmm * modification, are permitted provided that the following conditions
786230Stmm * are met:
886230Stmm * 1. Redistributions of source code must retain the above copyright
986230Stmm *    notice, this list of conditions and the following disclaimer.
1086230Stmm * 2. Redistributions in binary form must reproduce the above copyright
1186230Stmm *    notice, this list of conditions and the following disclaimer in the
1286230Stmm *    documentation and/or other materials provided with the distribution.
1386230Stmm * 3. The name of the author may not be used to endorse or promote products
1486230Stmm *    derived from this software without specific prior written permission.
1586230Stmm *
1686230Stmm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
1786230Stmm * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
1886230Stmm * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
1986230Stmm * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2086230Stmm * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
2186230Stmm * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
2286230Stmm * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
2386230Stmm * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
2486230Stmm * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
2586230Stmm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
2686230Stmm * SUCH DAMAGE.
2786230Stmm *
2890616Stmm *	from: NetBSD: iommuvar.h,v 1.9 2001/07/20 00:07:13 eeh Exp
2986230Stmm *
3086230Stmm * $FreeBSD: head/sys/sparc64/include/iommuvar.h 139825 2005-01-07 02:29:27Z imp $
3186230Stmm */
3286230Stmm
3386230Stmm#ifndef _MACHINE_IOMMUVAR_H_
3486230Stmm#define _MACHINE_IOMMUVAR_H_
3586230Stmm
3690616Stmm#define	IO_PAGE_SIZE		PAGE_SIZE_8K
3790616Stmm#define	IO_PAGE_MASK		PAGE_MASK_8K
3890616Stmm#define	IO_PAGE_SHIFT		PAGE_SHIFT_8K
3990616Stmm#define	round_io_page(x)	round_page(x)
4090616Stmm#define	trunc_io_page(x)	trunc_page(x)
4190616Stmm
4286230Stmm/*
43117390Stmm * Per-IOMMU state. The parenthesized comments indicate the locking strategy:
44117390Stmm *	i - protected by iommu_mtx.
45117390Stmm *	r - read-only after initialization.
46117390Stmm *	* - comment refers to pointer target / target hardware registers
47117390Stmm *	    (for bus_addr_t).
48117390Stmm * iommu_map_lruq is also locked by iommu_mtx. Elements of iommu_tsb may only
49117390Stmm * be accessed from functions operating on the map owning the corresponding
50117390Stmm * resource, so the locking the user is required to do to protect the map is
51117390Stmm * sufficient. As soon as the TSBs are divorced, these will be moved into struct
52117390Stmm * iommu_state, and each state struct will get its own lock.
53117390Stmm * iommu_dvma_rman needs to be moved there too, but has its own internal lock.
5486230Stmm */
5586230Stmmstruct iommu_state {
56117390Stmm	int			is_tsbsize;	/* (r) 0 = 8K, ... */
57117390Stmm	u_int64_t		is_dvmabase;	/* (r) */
58117390Stmm	int64_t			is_cr;		/* (r) Control reg value */
5986230Stmm
60117390Stmm	vm_paddr_t		is_flushpa[2];	/* (r) */
61117390Stmm	volatile int64_t	*is_flushva[2];	/* (r, *i) */
6290616Stmm	/*
63117390Stmm	 * (i)
6490616Stmm	 * When a flush is completed, 64 bytes will be stored at the given
6590616Stmm	 * location, the first double word being 1, to indicate completion.
6690616Stmm	 * The lower 6 address bits are ignored, so the addresses need to be
6790616Stmm	 * suitably aligned; over-allocate a large enough margin to be able
6890616Stmm	 * to adjust it.
6990616Stmm	 * Two such buffers are needed.
7090616Stmm	 */
7190616Stmm	volatile char		is_flush[STRBUF_FLUSHSYNC_NBYTES * 3 - 1];
7286230Stmm
7386230Stmm	/* copies of our parents state, to allow us to be self contained */
74117390Stmm	bus_space_tag_t		is_bustag;	/* (r) Our bus tag */
75117390Stmm	bus_space_handle_t	is_bushandle;	/* (r) */
76117390Stmm	bus_addr_t		is_iommu;	/* (r, *i) IOMMU registers */
77117390Stmm	bus_addr_t		is_sb[2];	/* (r, *i) Streaming buffer */
78117390Stmm	/* Tag diagnostics access */
79117390Stmm	bus_addr_t		is_dtag;	/* (r, *r) */
80117390Stmm	/* Data RAM diagnostic access */
81117390Stmm	bus_addr_t		is_ddram;	/* (r, *r) */
82117390Stmm	/* LRU queue diag. access */
83117390Stmm	bus_addr_t		is_dqueue;	/* (r, *r) */
84117390Stmm	/* Virtual address diagnostics register */
85117390Stmm	bus_addr_t		is_dva;		/* (r, *r) */
86117390Stmm	/* Tag compare diagnostics access */
87117390Stmm	bus_addr_t		is_dtcmp;	/* (r, *r) */
88100188Stmm
89117390Stmm	STAILQ_ENTRY(iommu_state)	is_link;	/* (r) */
9086230Stmm};
9186230Stmm
9286230Stmm/* interfaces for PCI/SBUS code */
93100188Stmmvoid iommu_init(char *, struct iommu_state *, int, u_int32_t, int);
9492844Salfredvoid iommu_reset(struct iommu_state *);
9593053Stmmvoid iommu_decode_fault(struct iommu_state *, vm_offset_t);
9686230Stmm
97116541Stmmextern struct bus_dma_methods iommu_dma_methods;
9886230Stmm
9986230Stmm#endif /* !_MACHINE_IOMMUVAR_H_ */
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