1139825Simp/*- 286230Stmm * Copyright (c) 1999 Matthew R. Green 386230Stmm * All rights reserved. 486230Stmm * 586230Stmm * Redistribution and use in source and binary forms, with or without 686230Stmm * modification, are permitted provided that the following conditions 786230Stmm * are met: 886230Stmm * 1. Redistributions of source code must retain the above copyright 986230Stmm * notice, this list of conditions and the following disclaimer. 1086230Stmm * 2. Redistributions in binary form must reproduce the above copyright 1186230Stmm * notice, this list of conditions and the following disclaimer in the 1286230Stmm * documentation and/or other materials provided with the distribution. 1386230Stmm * 1486230Stmm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1586230Stmm * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1686230Stmm * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1786230Stmm * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1886230Stmm * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 1986230Stmm * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 2086230Stmm * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 2186230Stmm * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 2286230Stmm * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2386230Stmm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2486230Stmm * SUCH DAMAGE. 2586230Stmm * 26219567Smarius * from: NetBSD: iommuvar.h,v 1.6 2008/05/29 14:51:26 mrg Exp 2786230Stmm * 2886230Stmm * $FreeBSD$ 2986230Stmm */ 3086230Stmm 3186230Stmm#ifndef _MACHINE_IOMMUVAR_H_ 32178840Smarius#define _MACHINE_IOMMUVAR_H_ 3386230Stmm 3490616Stmm#define IO_PAGE_SIZE PAGE_SIZE_8K 3590616Stmm#define IO_PAGE_MASK PAGE_MASK_8K 3690616Stmm#define IO_PAGE_SHIFT PAGE_SHIFT_8K 3790616Stmm#define round_io_page(x) round_page(x) 3890616Stmm#define trunc_io_page(x) trunc_page(x) 3990616Stmm 4086230Stmm/* 41171730Smarius * LRU queue handling for lazy resource allocation 42171730Smarius */ 43171730SmariusTAILQ_HEAD(iommu_maplruq_head, bus_dmamap); 44171730Smarius 45171730Smarius/* 46185008Smarius * Per-IOMMU state; the parenthesized comments indicate the locking strategy: 47171730Smarius * i - protected by is_mtx. 48117390Stmm * r - read-only after initialization. 49117390Stmm * * - comment refers to pointer target / target hardware registers 50117390Stmm * (for bus_addr_t). 51185008Smarius * is_maplruq is also locked by is_mtx. Elements of is_tsb may only be 52171730Smarius * accessed from functions operating on the map owning the corresponding 53171730Smarius * resource, so the locking the user is required to do to protect the 54171730Smarius * map is sufficient. 55171730Smarius * dm_reslist of all maps are locked by is_mtx as well. 56171730Smarius * is_dvma_rman has its own internal lock. 5786230Stmm */ 5886230Stmmstruct iommu_state { 59171730Smarius struct mtx is_mtx; 60171730Smarius struct rman is_dvma_rman; /* DVMA space rman */ 61171730Smarius struct iommu_maplruq_head is_maplruq; /* (i) LRU queue */ 62171730Smarius vm_paddr_t is_ptsb; /* (r) TSB physical address */ 63178840Smarius uint64_t *is_tsb; /* (*i) TSB virtual address */ 64117390Stmm int is_tsbsize; /* (r) 0 = 8K, ... */ 65178840Smarius uint64_t is_pmaxaddr; /* (r) max. physical address */ 66178840Smarius uint64_t is_dvmabase; /* (r) */ 67200923Smarius uint64_t is_cr; /* (r) Control reg value */ 6886230Stmm 69117390Stmm vm_paddr_t is_flushpa[2]; /* (r) */ 70200923Smarius volatile uint64_t *is_flushva[2]; /* (r, *i) */ 7190616Stmm /* 72117390Stmm * (i) 7390616Stmm * When a flush is completed, 64 bytes will be stored at the given 7490616Stmm * location, the first double word being 1, to indicate completion. 7590616Stmm * The lower 6 address bits are ignored, so the addresses need to be 7690616Stmm * suitably aligned; over-allocate a large enough margin to be able 7790616Stmm * to adjust it. 7890616Stmm * Two such buffers are needed. 7990616Stmm */ 8090616Stmm volatile char is_flush[STRBUF_FLUSHSYNC_NBYTES * 3 - 1]; 8186230Stmm 82185008Smarius /* copies of our parent's state, to allow us to be self contained */ 83117390Stmm bus_space_tag_t is_bustag; /* (r) Our bus tag */ 84117390Stmm bus_space_handle_t is_bushandle; /* (r) */ 85117390Stmm bus_addr_t is_iommu; /* (r, *i) IOMMU registers */ 86117390Stmm bus_addr_t is_sb[2]; /* (r, *i) Streaming buffer */ 87117390Stmm /* Tag diagnostics access */ 88117390Stmm bus_addr_t is_dtag; /* (r, *r) */ 89117390Stmm /* Data RAM diagnostic access */ 90117390Stmm bus_addr_t is_ddram; /* (r, *r) */ 91117390Stmm /* LRU queue diag. access */ 92117390Stmm bus_addr_t is_dqueue; /* (r, *r) */ 93117390Stmm /* Virtual address diagnostics register */ 94117390Stmm bus_addr_t is_dva; /* (r, *r) */ 95117390Stmm /* Tag compare diagnostics access */ 96117390Stmm bus_addr_t is_dtcmp; /* (r, *r) */ 97185008Smarius /* behavior flags */ 98185008Smarius u_int is_flags; /* (r) */ 99185008Smarius#define IOMMU_RERUN_DISABLE (1 << 0) 100200923Smarius#define IOMMU_FIRE (1 << 1) 101200923Smarius#define IOMMU_FLUSH_CACHE (1 << 2) 102200923Smarius#define IOMMU_PRESERVE_PROM (1 << 3) 10386230Stmm}; 10486230Stmm 105171730Smarius/* interfaces for PCI/SBus code */ 106200923Smariusvoid iommu_init(const char *name, struct iommu_state *is, u_int tsbsize, 107200923Smarius uint32_t iovabase, u_int resvpg); 108178840Smariusvoid iommu_reset(struct iommu_state *is); 109178840Smariusvoid iommu_decode_fault(struct iommu_state *is, vm_offset_t phys); 11086230Stmm 111116541Stmmextern struct bus_dma_methods iommu_dma_methods; 11286230Stmm 11386230Stmm#endif /* !_MACHINE_IOMMUVAR_H_ */ 114