iommureg.h revision 86230
1/* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratory. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. All advertising materials mentioning features or use of this software 23 * must display the following acknowledgement: 24 * This product includes software developed by the University of 25 * California, Berkeley and its contributors. 26 * 4. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 * from: @(#)sbusreg.h 8.1 (Berkeley) 6/11/93 43 * from: NetBSD: iommureg.h,v 1.6 2001/07/20 00:07:13 eeh Exp 44 * 45 * $FreeBSD: head/sys/sparc64/include/iommureg.h 86230 2001-11-09 20:14:41Z tmm $ 46 */ 47 48#ifndef _MACHINE_IOMMUREG_H_ 49#define _MACHINE_IOMMUREG_H_ 50 51/* 52 * UltraSPARC IOMMU registers, common to both the sbus and PCI 53 * controllers. 54 */ 55 56/* iommmu registers */ 57struct iommureg { 58 u_int64_t iommu_cr; /* IOMMU control register */ 59 u_int64_t iommu_tsb; /* IOMMU TSB base register */ 60 u_int64_t iommu_flush; /* IOMMU flush register */ 61}; 62 63/* streaming buffer registers */ 64struct iommu_strbuf { 65 u_int64_t strbuf_ctl; /* streaming buffer control reg */ 66 u_int64_t strbuf_pgflush; /* streaming buffer page flush */ 67 u_int64_t strbuf_flushsync;/* streaming buffer flush sync */ 68}; 69 70/* streaming buffer control register */ 71#define STRBUF_EN 0x0000000000000001UL 72#define STRBUF_D 0x0000000000000002UL 73 74#define IOMMU_BITS 34 75#define IOMMU_MAXADDR (1UL << IOMMU_BITS) 76 77/* 78 * control register bits 79 */ 80/* Nummber of entries in IOTSB */ 81#define IOMMUCR_TSB1K 0x0000000000000000UL 82#define IOMMUCR_TSB2K 0x0000000000010000UL 83#define IOMMUCR_TSB4K 0x0000000000020000UL 84#define IOMMUCR_TSB8K 0x0000000000030000UL 85#define IOMMUCR_TSB16K 0x0000000000040000UL 86#define IOMMUCR_TSB32K 0x0000000000050000UL 87#define IOMMUCR_TSB64K 0x0000000000060000UL 88#define IOMMUCR_TSB128K 0x0000000000070000UL 89/* Mask for above */ 90#define IOMMUCR_TSBMASK 0xfffffffffff8ffffUL 91/* 8K iommu page size */ 92#define IOMMUCR_8KPG 0x0000000000000000UL 93/* 64K iommu page size */ 94#define IOMMUCR_64KPG 0x0000000000000004UL 95/* Diag enable */ 96#define IOMMUCR_DE 0x0000000000000002UL 97/* Enable IOMMU */ 98#define IOMMUCR_EN 0x0000000000000001UL 99 100/* 101 * IOMMU stuff 102 */ 103/* Entry valid */ 104#define IOTTE_V 0x8000000000000000UL 105/* 8K or 64K page? */ 106#define IOTTE_64K 0x2000000000000000UL 107#define IOTTE_8K 0x0000000000000000UL 108/* Is page streamable? */ 109#define IOTTE_STREAM 0x1000000000000000UL 110/* Accesses to same bus segment? */ 111#define IOTTE_LOCAL 0x0800000000000000UL 112/* Let's assume this is correct */ 113#define IOTTE_PAMASK 0x000001ffffffe000UL 114/* Accesses to cacheable space */ 115#define IOTTE_C 0x0000000000000010UL 116/* Writeable */ 117#define IOTTE_W 0x0000000000000002UL 118 119/* 120 * On sun4u each bus controller has a separate IOMMU. The IOMMU has 121 * a TSB which must be page aligned and physically contiguous. Mappings 122 * can be of 8K IOMMU pages or 64K IOMMU pages. We use 8K for compatibility 123 * with the CPU's MMU. 124 * 125 * On sysio, psycho, and psycho+, IOMMU TSBs using 8K pages can map the 126 * following size segments: 127 * 128 * VA size VA base TSB size tsbsize 129 * -------- -------- --------- ------- 130 * 8MB ff800000 8K 0 131 * 16MB ff000000 16K 1 132 * 32MB fe000000 32K 2 133 * 64MB fc000000 64K 3 134 * 128MB f8000000 128K 4 135 * 256MB f0000000 256K 5 136 * 512MB e0000000 512K 6 137 * 1GB c0000000 1MB 7 138 * 139 * Unfortunately, sabres on UltraSPARC IIi and IIe processors does not use 140 * this scheme to determine the IOVA base address. Instead, bits 31-29 are 141 * used to check against the Target Address Space register in the IIi and 142 * the the IOMMU is used if they hit. God knows what goes on in the IIe. 143 * 144 */ 145 146#define IOTSB_VEND (~PAGE_MASK) 147#define IOTSB_VSTART(sz) (u_int)(IOTSB_VEND << ((sz) + 10)) 148 149#define MAKEIOTTE(pa,w,c,s) \ 150 (((pa) & IOTTE_PAMASK) | ((w) ? IOTTE_W : 0) | \ 151 ((c) ? IOTTE_C : 0) | ((s) ? IOTTE_STREAM : 0) | \ 152 (IOTTE_V | IOTTE_8K)) 153#define IOTSBSLOT(va,sz) \ 154 ((u_int)(((vm_offset_t)(va)) - (is->is_dvmabase)) >> PAGE_SHIFT) 155 156#endif /* !_MACHINE_IOMMUREG_H_ */ 157