iommureg.h revision 218909
1139776Simp/*- 264880Sphk * Copyright (c) 1992, 1993 364880Sphk * The Regents of the University of California. All rights reserved. 464880Sphk * 564880Sphk * This software was developed by the Computer Systems Engineering group 664880Sphk * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 764880Sphk * contributed to Berkeley. 864880Sphk * 964880Sphk * Redistribution and use in source and binary forms, with or without 1064880Sphk * modification, are permitted provided that the following conditions 1164880Sphk * are met: 1264880Sphk * 1. Redistributions of source code must retain the above copyright 1364880Sphk * notice, this list of conditions and the following disclaimer. 1464880Sphk * 2. Redistributions in binary form must reproduce the above copyright 1564880Sphk * notice, this list of conditions and the following disclaimer in the 1664880Sphk * documentation and/or other materials provided with the distribution. 1764880Sphk * 4. Neither the name of the University nor the names of its contributors 1864880Sphk * may be used to endorse or promote products derived from this software 1964880Sphk * without specific prior written permission. 2064880Sphk * 2164880Sphk * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 2264880Sphk * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2364880Sphk * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2464880Sphk * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 2564880Sphk * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2664880Sphk * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2764880Sphk * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2864880Sphk * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2964880Sphk * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 3064880Sphk * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3164880Sphk * SUCH DAMAGE. 3264880Sphk * 3364880Sphk * from: @(#)sbusreg.h 8.1 (Berkeley) 6/11/93 3464880Sphk * from: NetBSD: iommureg.h,v 1.6 2001/07/20 00:07:13 eeh Exp 3564880Sphk * 3664880Sphk * $FreeBSD: head/sys/sparc64/include/iommureg.h 218909 2011-02-21 09:01:34Z brucec $ 3764880Sphk */ 3864880Sphk 3964880Sphk#ifndef _MACHINE_IOMMUREG_H_ 4076166Smarkm#define _MACHINE_IOMMUREG_H_ 4176166Smarkm 4276166Smarkm/* 4376166Smarkm * UltraSPARC IOMMU registers, common to both the PCI and SBus 44150342Sphk * controllers. 4564880Sphk */ 46150342Sphk 4764880Sphk/* IOMMU registers */ 4864880Sphk#define IMR_CTL 0x0000 /* IOMMU control register */ 4964880Sphk#define IMR_TSB 0x0008 /* IOMMU TSB base register */ 50150342Sphk#define IMR_FLUSH 0x0010 /* IOMMU flush register */ 51150342Sphk/* The TTE Cache is Fire and Oberon only. */ 5264880Sphk#define IMR_CACHE_FLUSH 0x0100 /* IOMMU TTE cache flush address register */ 5364880Sphk#define IMR_CACHE_INVAL 0x0108 /* IOMMU TTE cache invalidate register */ 54132902Sphk 55101777Sphk/* streaming buffer registers */ 56101777Sphk#define ISR_CTL 0x0000 /* streaming buffer control reg */ 57101777Sphk#define ISR_PGFLUSH 0x0008 /* streaming buffer page flush */ 5864880Sphk#define ISR_FLUSHSYNC 0x0010 /* streaming buffer flush sync */ 5964880Sphk 6064880Sphk/* streaming buffer diagnostics registers */ 6164880Sphk#define ISD_DATA_DIAG 0x0000 /* streaming buffer data RAM diag 0..127 */ 6264880Sphk#define ISD_ERROR_DIAG 0x0400 /* streaming buffer error status diag 0..127 */ 63191990Sattilio#define ISD_PG_TAG_DIAG 0x0800 /* streaming buffer page tag diag 0..15 */ 6464880Sphk#define ISD_LN_TAG_DIAG 0x0900 /* streaming buffer line tag diag 0..15 */ 6565132Sphk 6664880Sphk/* streaming buffer control register */ 6764880Sphk#define STRBUF_EN 0x0000000000000001UL 6864880Sphk#define STRBUF_D 0x0000000000000002UL 69150342Sphk#define STRBUF_RR_DIS 0x0000000000000004UL 70150342Sphk 71150342Sphk#define IOMMU_MAXADDR(bits) ((1UL << (bits)) - 1) 7265132Sphk 73137006Sphk/* 74138106Sphk * control register bits 7564880Sphk */ 7664880Sphk/* Nummber of entries in the IOTSB - pre-Fire only */ 77150342Sphk#define IOMMUCR_TSBSZ_MASK 0x0000000000070000UL 78150342Sphk#define IOMMUCR_TSBSZ_SHIFT 16 79150342Sphk/* TSB cache snoop enable */ 80162398Skib#define IOMMUCR_SE 0x0000000000000400UL 8164880Sphk/* Cache modes - Fire and Oberon */ 82162647Stegge#define IOMMUCR_CM_NC_TLB_TBW 0x0000000000000000UL 8364880Sphk#define IOMMUCR_CM_LC_NTLB_NTBW 0x0000000000000100UL 84150342Sphk#define IOMMUCR_CM_LC_TLB_TBW 0x0000000000000200UL 85101069Srwatson#define IOMMUCR_CM_C_TLB_TBW 0x0000000000000300UL 86101069Srwatson/* IOMMU page size - pre-Fire only */ 87101069Srwatson#define IOMMUCR_8KPG 0x0000000000000000UL 88162647Stegge#define IOMMUCR_64KPG 0x0000000000000004UL 89107698Srwatson/* Bypass enable - Fire and Oberon */ 90150342Sphk#define IOMMUCR_BE 0x0000000000000002UL 9164880Sphk/* Diagnostic mode enable - pre-Fire only */ 9264880Sphk#define IOMMUCR_DE 0x0000000000000002UL 93150342Sphk/* IOMMU/translation enable */ 9464880Sphk#define IOMMUCR_EN 0x0000000000000001UL 95191990Sattilio 9665132Sphk/* 97150342Sphk * TSB base register bits 98150342Sphk */ 99150342Sphk /* TSB base address */ 10065132Sphk#define IOMMUTB_TB_MASK 0x000007ffffffe000UL 10165132Sphk#define IOMMUTB_TB_SHIFT 13 102138481Sphk/* IOMMU page size - Fire and Oberon */ 103175294Sattilio#define IOMMUTB_8KPG 0x0000000000000000UL 10465132Sphk#define IOMMUTB_64KPG 0x0000000000000100UL 105138481Sphk/* Nummber of entries in the IOTSB - Fire and Oberon */ 10664880Sphk#define IOMMUTB_TSBSZ_MASK 0x0000000000000004UL 10764880Sphk#define IOMMUTB_TSBSZ_SHIFT 0 10864880Sphk 10964880Sphk/* 110162398Skib * TSB size definitions for both control and TSB base register */ 111162398Skib#define IOMMU_TSB1K 0 112162398Skib#define IOMMU_TSB2K 1 113162398Skib#define IOMMU_TSB4K 2 114162398Skib#define IOMMU_TSB8K 3 115162398Skib#define IOMMU_TSB16K 4 116162398Skib#define IOMMU_TSB32K 5 11764880Sphk#define IOMMU_TSB64K 6 118191990Sattilio#define IOMMU_TSB128K 7 11964880Sphk/* Fire and Oberon */ 12064880Sphk#define IOMMU_TSB256K 8 12164880Sphk/* Fire and Oberon */ 12264880Sphk#define IOMMU_TSB512K 9 123162398Skib#define IOMMU_TSBENTRIES(tsbsz) \ 124162398Skib ((1 << (tsbsz)) << (IO_PAGE_SHIFT - IOTTE_SHIFT)) 12564880Sphk 12665132Sphk/* 127162398Skib * Diagnostic register definitions 128162398Skib */ 12976688Siedowse#define IOMMU_DTAG_VPNBITS 19 130191990Sattilio#define IOMMU_DTAG_VPNMASK ((1 << IOMMU_DTAG_VPNBITS) - 1) 13164880Sphk#define IOMMU_DTAG_VPNSHIFT 13 13264880Sphk#define IOMMU_DTAG_ERRBITS 3 133150342Sphk#define IOMMU_DTAG_ERRSHIFT 22 134150342Sphk#define IOMMU_DTAG_ERRMASK \ 135150501Sphk (((1 << IOMMU_DTAG_ERRBITS) - 1) << IOMMU_DTAG_ERRSHIFT) 136162398Skib 137162398Skib#define IOMMU_DDATA_PGBITS 21 138162398Skib#define IOMMU_DDATA_PGMASK ((1 << IOMMU_DDATA_PGBITS) - 1) 139162398Skib#define IOMMU_DDATA_PGSHIFT 13 140150342Sphk#define IOMMU_DDATA_C (1 << 28) 141162398Skib#define IOMMU_DDATA_V (1 << 30) 142162398Skib 143162398Skib/* 14464880Sphk * IOMMU stuff 14564880Sphk */ 14664880Sphk/* Entry valid */ 14765132Sphk#define IOTTE_V 0x8000000000000000UL 14865132Sphk/* Page size - pre-Fire only */ 14964880Sphk#define IOTTE_64K 0x2000000000000000UL 150191990Sattilio#define IOTTE_8K 0x0000000000000000UL 15164880Sphk/* Streamable page - streaming buffer equipped variants only */ 15265132Sphk#define IOTTE_STREAM 0x1000000000000000UL 15364880Sphk/* Accesses to the same bus segment - SBus only */ 15465132Sphk#define IOTTE_LOCAL 0x0800000000000000UL 15564880Sphk/* Physical address mask (based on Oberon) */ 15665132Sphk#define IOTTE_PAMASK 0x00007fffffffe000UL 157162398Skib/* Accesses to cacheable space - pre-Fire only */ 158191990Sattilio#define IOTTE_C 0x0000000000000010UL 15965132Sphk/* Writeable */ 16065132Sphk#define IOTTE_W 0x0000000000000002UL 161101308Sjeff 16264880Sphk/* log2 of the IOMMU TTE size */ 16364880Sphk#define IOTTE_SHIFT 3 16464880Sphk 16564880Sphk/* Streaming buffer line size */ 16664880Sphk#define STRBUF_LINESZ 64 167191990Sattilio 16864880Sphk/* 16964880Sphk * Number of bytes written by a stream buffer flushsync operation to indicate 17064880Sphk * completion. 17164880Sphk */ 17264880Sphk#define STRBUF_FLUSHSYNC_NBYTES STRBUF_LINESZ 17364880Sphk 17464880Sphk/* 17564880Sphk * On sun4u each bus controller has a separate IOMMU. The IOMMU has 17664880Sphk * a TSB which must be page aligned and physically contiguous. Mappings 17764880Sphk * can be of 8K IOMMU pages or 64K IOMMU pages. We use 8K for compatibility 17864880Sphk * with the CPU's MMU. 17964880Sphk * 18064880Sphk * On sysio, psycho, and psycho+, IOMMU TSBs using 8K pages can map the 18164880Sphk * following size segments: 182132902Sphk * 183116271Sphk * VA size VA base TSB size tsbsize 184116271Sphk * -------- -------- --------- ------- 185116271Sphk * 8MB ff800000 8K 0 18664880Sphk * 16MB ff000000 16K 1 18764880Sphk * 32MB fe000000 32K 2 18864880Sphk * 64MB fc000000 64K 3 189 * 128MB f8000000 128K 4 190 * 256MB f0000000 256K 5 191 * 512MB e0000000 512K 6 192 * 1GB c0000000 1MB 7 193 * 194 * Unfortunately, sabres on UltraSPARC IIi and IIe processors does not use 195 * this scheme to determine the IOVA base address. Instead, bits 31-29 are 196 * used to check against the Target Address Space register in the IIi and 197 * the IOMMU is used if they hit. God knows what goes on in the IIe. 198 * 199 */ 200 201#define IOTSB_BASESZ (1024 << IOTTE_SHIFT) 202#define IOTSB_VEND (~IO_PAGE_MASK) 203#define IOTSB_VSTART(sz) (u_int)(IOTSB_VEND << ((sz) + 10)) 204 205#define MAKEIOTTE(pa, w, c, s) \ 206 (((pa) & IOTTE_PAMASK) | ((w) ? IOTTE_W : 0) | \ 207 ((c) ? IOTTE_C : 0) | ((s) ? IOTTE_STREAM : 0) | \ 208 (IOTTE_V | IOTTE_8K)) 209#define IOTSBSLOT(va) \ 210 ((u_int)(((vm_offset_t)(va)) - (is->is_dvmabase)) >> IO_PAGE_SHIFT) 211 212#endif /* !_MACHINE_IOMMUREG_H_ */ 213