iommureg.h revision 127977
1238730Sdelphij/* 2293190Sdelphij * Copyright (c) 1992, 1993 3238730Sdelphij * The Regents of the University of California. All rights reserved. 4238730Sdelphij * 5238730Sdelphij * This software was developed by the Computer Systems Engineering group 6238730Sdelphij * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7238730Sdelphij * contributed to Berkeley. 8238730Sdelphij * 960786Sps * Redistribution and use in source and binary forms, with or without 1060786Sps * modification, are permitted provided that the following conditions 1160786Sps * are met: 1260786Sps * 1. Redistributions of source code must retain the above copyright 1360786Sps * notice, this list of conditions and the following disclaimer. 1460786Sps * 2. Redistributions in binary form must reproduce the above copyright 1560786Sps * notice, this list of conditions and the following disclaimer in the 1660786Sps * documentation and/or other materials provided with the distribution. 1760786Sps * 4. Neither the name of the University nor the names of its contributors 18161478Sdelphij * may be used to endorse or promote products derived from this software 1960786Sps * without specific prior written permission. 20161478Sdelphij * 2189019Sps * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 2289019Sps * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2360786Sps * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24161478Sdelphij * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 2560786Sps * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2689019Sps * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2789019Sps * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2889019Sps * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29237613Sdelphij * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 3060786Sps * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3160786Sps * SUCH DAMAGE. 3260786Sps * 3360786Sps * from: @(#)sbusreg.h 8.1 (Berkeley) 6/11/93 3460786Sps * from: NetBSD: iommureg.h,v 1.6 2001/07/20 00:07:13 eeh Exp 35128345Stjr * 3660786Sps * $FreeBSD: head/sys/sparc64/include/iommureg.h 127977 2004-04-07 05:00:01Z imp $ 3763128Sps */ 38293190Sdelphij 3960786Sps#ifndef _MACHINE_IOMMUREG_H_ 4060786Sps#define _MACHINE_IOMMUREG_H_ 41161478Sdelphij 4260786Sps/* 43161478Sdelphij * UltraSPARC IOMMU registers, common to both the sbus and PCI 44161478Sdelphij * controllers. 4560786Sps */ 4660786Sps 47161478Sdelphij/* iommmu registers */ 4860786Sps#define IMR_CTL 0x0000 /* IOMMU control register */ 4960786Sps#define IMR_TSB 0x0008 /* IOMMU TSB base register */ 5060786Sps#define IMR_FLUSH 0x0010 /* IOMMU flush register */ 5160786Sps 5260786Sps/* streaming buffer registers */ 5363128Sps#define ISR_CTL 0x0000 /* streaming buffer control reg */ 5460786Sps#define ISR_PGFLUSH 0x0008 /* streaming buffer page flush */ 5560786Sps#define ISR_FLUSHSYNC 0x0010 /* streaming buffer flush sync */ 5660786Sps 5760786Sps/* streaming buffer diagnostics registers. */ 5860786Sps#define ISD_DATA_DIAG 0x0000 /* streaming buffer data RAM diag 0..127 */ 5960786Sps#define ISD_ERROR_DIAG 0x0400 /* streaming buffer error status diag 0..127 */ 6060786Sps#define ISD_PG_TAG_DIAG 0x0800 /* streaming buffer page tag diag 0..15 */ 6163128Sps#define ISD_LN_TAG_DIAG 0x0900 /* streaming buffer line tag diag 0..15 */ 6263128Sps 6360786Sps/* streaming buffer control register */ 64161478Sdelphij#define STRBUF_EN 0x0000000000000001UL 65161478Sdelphij#define STRBUF_D 0x0000000000000002UL 66161478Sdelphij 67161478Sdelphij#define IOMMU_BITS 34 68161478Sdelphij#define IOMMU_MAXADDR (1UL << IOMMU_BITS) 6960786Sps 7060786Sps/* 7160786Sps * control register bits 7260786Sps */ 7360786Sps/* Nummber of entries in IOTSB */ 7460786Sps#define IOMMUCR_TSBSZ_SHIFT 16 7560786Sps#define IOMMUCR_TSB1K 0x0000000000000000UL 7660786Sps#define IOMMUCR_TSB2K 0x0000000000010000UL 7760786Sps#define IOMMUCR_TSB4K 0x0000000000020000UL 78161478Sdelphij#define IOMMUCR_TSB8K 0x0000000000030000UL 79161478Sdelphij#define IOMMUCR_TSB16K 0x0000000000040000UL 80161478Sdelphij#define IOMMUCR_TSB32K 0x0000000000050000UL 81293190Sdelphij#define IOMMUCR_TSB64K 0x0000000000060000UL 82161478Sdelphij#define IOMMUCR_TSB128K 0x0000000000070000UL 8389019Sps/* Mask for above */ 8489019Sps#define IOMMUCR_TSBMASK 0xfffffffffff8ffffUL 8589019Sps/* 8K iommu page size */ 8660786Sps#define IOMMUCR_8KPG 0x0000000000000000UL 8760786Sps/* 64K iommu page size */ 8860786Sps#define IOMMUCR_64KPG 0x0000000000000004UL 8989019Sps/* Diag enable */ 9089019Sps#define IOMMUCR_DE 0x0000000000000002UL 91161478Sdelphij/* Enable IOMMU */ 9289019Sps#define IOMMUCR_EN 0x0000000000000001UL 9389019Sps 94161478Sdelphij/* 95161478Sdelphij * Diagnostic register definitions. 96161478Sdelphij */ 97161478Sdelphij#define IOMMU_DTAG_VPNBITS 19 98161478Sdelphij#define IOMMU_DTAG_VPNMASK ((1 << IOMMU_DTAG_VPNBITS) - 1) 99161478Sdelphij#define IOMMU_DTAG_VPNSHIFT 13 100161478Sdelphij#define IOMMU_DTAG_ERRBITS 3 101161478Sdelphij#define IOMMU_DTAG_ERRSHIFT 22 10289019Sps#define IOMMU_DTAG_ERRMASK \ 10389019Sps (((1 << IOMMU_DTAG_ERRBITS) - 1) << IOMMU_DTAG_ERRSHIFT) 104161478Sdelphij 10589019Sps#define IOMMU_DDATA_PGBITS 21 10689019Sps#define IOMMU_DDATA_PGMASK ((1 << IOMMU_DDATA_PGBITS) - 1) 10789019Sps#define IOMMU_DDATA_PGSHIFT 13 10889019Sps#define IOMMU_DDATA_C (1 << 28) 10989019Sps#define IOMMU_DDATA_V (1 << 30) 11089019Sps 11189019Sps/* 11289019Sps * IOMMU stuff 113161478Sdelphij */ 114161478Sdelphij/* Entry valid */ 115161478Sdelphij#define IOTTE_V 0x8000000000000000UL 116161478Sdelphij/* 8K or 64K page? */ 117161478Sdelphij#define IOTTE_64K 0x2000000000000000UL 118161478Sdelphij#define IOTTE_8K 0x0000000000000000UL 119161478Sdelphij/* Is page streamable? */ 120161478Sdelphij#define IOTTE_STREAM 0x1000000000000000UL 121161478Sdelphij/* Accesses to same bus segment? */ 122161478Sdelphij#define IOTTE_LOCAL 0x0800000000000000UL 123161478Sdelphij/* Let's assume this is correct */ 124161478Sdelphij#define IOTTE_PAMASK 0x000001ffffffe000UL 12589019Sps/* Accesses to cacheable space */ 12689019Sps#define IOTTE_C 0x0000000000000010UL 127128345Stjr/* Writeable */ 128128345Stjr#define IOTTE_W 0x0000000000000002UL 129161478Sdelphij 13089019Sps/* log2 of the IOMMU TTE size. */ 13189019Sps#define IOTTE_SHIFT 3 13289019Sps 13389019Sps/* Streaming buffer line size. */ 13489019Sps#define STRBUF_LINESZ 64 13589019Sps 13689019Sps/* 137161478Sdelphij * Number of bytes written by a stream buffer flushsync operation to indicate 138161478Sdelphij * completion. 139161478Sdelphij */ 140161478Sdelphij#define STRBUF_FLUSHSYNC_NBYTES STRBUF_LINESZ 141161478Sdelphij 142161478Sdelphij/* 143161478Sdelphij * On sun4u each bus controller has a separate IOMMU. The IOMMU has 144161478Sdelphij * a TSB which must be page aligned and physically contiguous. Mappings 145161478Sdelphij * can be of 8K IOMMU pages or 64K IOMMU pages. We use 8K for compatibility 146161478Sdelphij * with the CPU's MMU. 14760786Sps * 14860786Sps * On sysio, psycho, and psycho+, IOMMU TSBs using 8K pages can map the 14960786Sps * following size segments: 15060786Sps * 15160786Sps * VA size VA base TSB size tsbsize 15260786Sps * -------- -------- --------- ------- 15360786Sps * 8MB ff800000 8K 0 154161478Sdelphij * 16MB ff000000 16K 1 15560786Sps * 32MB fe000000 32K 2 156161478Sdelphij * 64MB fc000000 64K 3 157161478Sdelphij * 128MB f8000000 128K 4 15860786Sps * 256MB f0000000 256K 5 15960786Sps * 512MB e0000000 512K 6 16063128Sps * 1GB c0000000 1MB 7 161128345Stjr * 162128345Stjr * Unfortunately, sabres on UltraSPARC IIi and IIe processors does not use 16360786Sps * this scheme to determine the IOVA base address. Instead, bits 31-29 are 16460786Sps * used to check against the Target Address Space register in the IIi and 16560786Sps * the the IOMMU is used if they hit. God knows what goes on in the IIe. 16660786Sps * 16760786Sps */ 16860786Sps 16960786Sps#define IOTSB_BASESZ (1024 << IOTTE_SHIFT) 17060786Sps#define IOTSB_VEND (~IO_PAGE_MASK) 17160786Sps#define IOTSB_VSTART(sz) (u_int)(IOTSB_VEND << ((sz) + 10)) 172128345Stjr 17360786Sps#define MAKEIOTTE(pa,w,c,s) \ 17460786Sps (((pa) & IOTTE_PAMASK) | ((w) ? IOTTE_W : 0) | \ 17563128Sps ((c) ? IOTTE_C : 0) | ((s) ? IOTTE_STREAM : 0) | \ 17663128Sps (IOTTE_V | IOTTE_8K)) 17763128Sps#define IOTSBSLOT(va) \ 17863128Sps ((u_int)(((vm_offset_t)(va)) - (is->is_dvmabase)) >> IO_PAGE_SHIFT) 17963128Sps 18063128Sps#endif /* !_MACHINE_IOMMUREG_H_ */ 18163128Sps