cpufunc.h revision 89033 
1/*-
2 * Copyright (c) 2001 Jake Burkholder.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/sparc64/include/cpufunc.h 89033 2002-01-08 04:36:01Z jake $
27 */
28
29#ifndef	_MACHINE_CPUFUNC_H_
30#define	_MACHINE_CPUFUNC_H_
31
32#include <machine/asi.h>
33#include <machine/pstate.h>
34
35/*
36 * membar operand macros for use in other macros when # is a special
37 * character.  Keep these in sync with what the hardware expects.
38 */
39#define	C_Lookaside	(0)
40#define	C_MemIssue	(1)
41#define	C_Sync		(2)
42#define	M_LoadLoad	(0)
43#define	M_StoreLoad	(1)
44#define	M_LoadStore	(2)
45#define	M_StoreStore	(3)
46
47#define	CMASK_SHIFT	(4)
48#define	MMASK_SHIFT	(0)
49
50#define	CMASK_GEN(bit)	((1 << (bit)) << CMASK_SHIFT)
51#define	MMASK_GEN(bit)	((1 << (bit)) << MMASK_SHIFT)
52
53#define	Lookaside	CMASK_GEN(C_Lookaside)
54#define	MemIssue	CMASK_GEN(C_MemIssue)
55#define	Sync		CMASK_GEN(C_Sync)
56#define	LoadLoad	MMASK_GEN(M_LoadLoad)
57#define	StoreLoad	MMASK_GEN(M_StoreLoad)
58#define	LoadStore	MMASK_GEN(M_LoadStore)
59#define	StoreStore	MMASK_GEN(M_StoreStore)
60
61#define	casa(rs1, rs2, rd, asi) ({					\
62	u_int __rd = (u_int32_t)(rd);					\
63	__asm __volatile("casa [%1] %2, %3, %0"				\
64	    : "+r" (__rd) : "r" (rs1), "n" (asi), "r" (rs2));		\
65	__rd;								\
66})
67
68#define	casxa(rs1, rs2, rd, asi) ({					\
69	u_long __rd = (u_int64_t)(rd);					\
70	__asm __volatile("casxa [%1] %2, %3, %0"			\
71	    : "+r" (__rd) : "r" (rs1), "n" (asi), "r" (rs2));		\
72	__rd;								\
73})
74
75#define	flush(va) do {							\
76	__asm __volatile("flush %0" : : "r" (va));			\
77} while (0)
78
79#define	flushw() do {							\
80	__asm __volatile("flushw" : :);					\
81} while (0)
82
83#define	mov(val, reg) do {						\
84	__asm __volatile("mov %0, %" __XSTRING(reg) : : "r" (val));	\
85} while (0)
86
87/* Generate ld*a/st*a functions for non-constant ASI's. */
88#define LDNC_GEN(tp, o)							\
89	static __inline tp						\
90	o ## _nc(caddr_t va, int asi)					\
91	{								\
92		tp r;							\
93		__asm __volatile("wr %2, 0, %%asi;" #o " [%1] %%asi, %0"\
94		    : "=r" (r) : "r" (va), "r" (asi));			\
95		return (r);						\
96	}
97
98LDNC_GEN(u_char, lduba);
99LDNC_GEN(u_short, lduha);
100LDNC_GEN(u_int, lduwa);
101LDNC_GEN(u_long, ldxa);
102
103#define	LD_GENERIC(va, asi, op, type) ({				\
104	type __r;							\
105	__asm __volatile(#op " [%1] %2, %0"				\
106	    : "=r" (__r) : "r" (va), "n" (asi));			\
107	__r;								\
108})
109
110#define	lduba(va, asi)	LD_GENERIC(va, asi, lduba, u_char)
111#define	lduha(va, asi)	LD_GENERIC(va, asi, lduha, u_short)
112#define	lduwa(va, asi)	LD_GENERIC(va, asi, lduwa, u_int)
113#define	ldxa(va, asi)	LD_GENERIC(va, asi, ldxa, u_long)
114
115#define STNC_GEN(tp, o)							\
116	static __inline void						\
117	o ## _nc(caddr_t va, int asi, tp val)				\
118	{								\
119		__asm __volatile("wr %2, 0, %%asi;" #o " %0, [%1] %%asi"\
120		    : : "r" (val), "r" (va), "r" (asi));		\
121	}
122
123STNC_GEN(u_char, stba);
124STNC_GEN(u_short, stha);
125STNC_GEN(u_int, stwa);
126STNC_GEN(u_long, stxa);
127
128#define	ST_GENERIC(va, asi, val, op)					\
129	__asm __volatile(#op " %0, [%1] %2"				\
130	    : : "r" (val), "r" (va), "n" (asi));			\
131
132#define	stba(va, asi, val)	ST_GENERIC(va, asi, val, stba)
133#define	stha(va, asi, val)	ST_GENERIC(va, asi, val, stha)
134#define	stwa(va, asi, val)	ST_GENERIC(va, asi, val, stwa)
135#define	stxa(va, asi, val)	ST_GENERIC(va, asi, val, stxa)
136
137#define	membar(mask) do {						\
138	__asm __volatile("membar %0" : : "n" (mask) : "memory");	\
139} while (0)
140
141#define	rd(name) ({							\
142	u_int64_t __sr;							\
143	__asm __volatile("rd %%" #name ", %0" : "=r" (__sr) :);		\
144	__sr;								\
145})
146
147#define	wr(name, val, xor) do {						\
148	__asm __volatile("wr %0, %1, %%" #name				\
149	    : : "r" (val), "rI" (xor));					\
150} while (0)
151
152#define	rdpr(name) ({							\
153	u_int64_t __pr;							\
154	__asm __volatile("rdpr %%" #name", %0" : "=r" (__pr) :);	\
155	__pr;								\
156})
157
158#define	wrpr(name, val, xor) do {					\
159	__asm __volatile("wrpr %0, %1, %%" #name			\
160	    : : "r" (val), "rI" (xor));					\
161} while (0)
162
163#define	CRITICAL_FORK	(0)
164
165static __inline void
166breakpoint(void)
167{
168	__asm __volatile("ta %%xcc, 1" : :);
169}
170
171static __inline critical_t
172cpu_critical_enter(void)
173{
174	critical_t pil;
175
176	pil = rdpr(pil);
177	wrpr(pil, 0, 14);
178	return (pil);
179}
180
181static __inline void
182cpu_critical_exit(critical_t pil)
183{
184	wrpr(pil, pil, 0);
185}
186
187void ascopy(u_long asi, vm_offset_t src, vm_offset_t dst, size_t len);
188void ascopyfrom(u_long sasi, vm_offset_t src, caddr_t dst, size_t len);
189void ascopyto(caddr_t src, u_long dasi, vm_offset_t dst, size_t len);
190void aszero(u_long asi, vm_offset_t dst, size_t len);
191
192/*
193 * Ultrasparc II doesn't implement popc in hardware.  Suck.
194 */
195#if 0
196#define	HAVE_INLINE_FFS
197/*
198 * See page 202 of the SPARC v9 Architecture Manual.
199 */
200static __inline int
201ffs(int mask)
202{
203	int result;
204	int neg;
205	int tmp;
206
207	__asm __volatile(
208	"	neg	%3, %1 ;	"
209	"	xnor	%3, %1, %2 ;	"
210	"	popc	%2, %0 ;	"
211	"	movrz	%3, %%g0, %0 ;	"
212	: "=r" (result), "=r" (neg), "=r" (tmp) : "r" (mask));
213	return (result);
214}
215#endif
216
217#undef LDNC_GEN
218#undef STNC_GEN
219
220#endif /* !_MACHINE_CPUFUNC_H_ */
221