cpufunc.h revision 145150
1/*- 2 * Copyright (c) 2001 Jake Burkholder. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/sparc64/include/cpufunc.h 145150 2005-04-16 14:57:38Z marius $ 27 */ 28 29#ifndef _MACHINE_CPUFUNC_H_ 30#define _MACHINE_CPUFUNC_H_ 31 32#include <machine/asi.h> 33#include <machine/pstate.h> 34 35struct thread; 36 37/* 38 * membar operand macros for use in other macros when # is a special 39 * character. Keep these in sync with what the hardware expects. 40 */ 41#define C_Lookaside (0) 42#define C_MemIssue (1) 43#define C_Sync (2) 44#define M_LoadLoad (0) 45#define M_StoreLoad (1) 46#define M_LoadStore (2) 47#define M_StoreStore (3) 48 49#define CMASK_SHIFT (4) 50#define MMASK_SHIFT (0) 51 52#define CMASK_GEN(bit) ((1 << (bit)) << CMASK_SHIFT) 53#define MMASK_GEN(bit) ((1 << (bit)) << MMASK_SHIFT) 54 55#define Lookaside CMASK_GEN(C_Lookaside) 56#define MemIssue CMASK_GEN(C_MemIssue) 57#define Sync CMASK_GEN(C_Sync) 58#define LoadLoad MMASK_GEN(M_LoadLoad) 59#define StoreLoad MMASK_GEN(M_StoreLoad) 60#define LoadStore MMASK_GEN(M_LoadStore) 61#define StoreStore MMASK_GEN(M_StoreStore) 62 63#define casa(rs1, rs2, rd, asi) ({ \ 64 u_int __rd = (uint32_t)(rd); \ 65 __asm __volatile("casa [%1] %2, %3, %0" \ 66 : "+r" (__rd) : "r" (rs1), "n" (asi), "r" (rs2)); \ 67 __rd; \ 68}) 69 70#define casxa(rs1, rs2, rd, asi) ({ \ 71 u_long __rd = (uint64_t)(rd); \ 72 __asm __volatile("casxa [%1] %2, %3, %0" \ 73 : "+r" (__rd) : "r" (rs1), "n" (asi), "r" (rs2)); \ 74 __rd; \ 75}) 76 77#define flush(va) do { \ 78 __asm __volatile("flush %0" : : "r" (va)); \ 79} while (0) 80 81#define flushw() do { \ 82 __asm __volatile("flushw" : :); \ 83} while (0) 84 85#define mov(val, reg) do { \ 86 __asm __volatile("mov %0, %" __XSTRING(reg) : : "r" (val)); \ 87} while (0) 88 89/* Generate ld*a/st*a functions for non-constant ASI's. */ 90#define LDNC_GEN(tp, o) \ 91 static __inline tp \ 92 o ## _nc(caddr_t va, int asi) \ 93 { \ 94 tp r; \ 95 __asm __volatile("wr %2, 0, %%asi;" #o " [%1] %%asi, %0"\ 96 : "=r" (r) : "r" (va), "r" (asi)); \ 97 return (r); \ 98 } 99 100LDNC_GEN(u_char, lduba); 101LDNC_GEN(u_short, lduha); 102LDNC_GEN(u_int, lduwa); 103LDNC_GEN(u_long, ldxa); 104 105#define LD_GENERIC(va, asi, op, type) ({ \ 106 type __r; \ 107 __asm __volatile(#op " [%1] %2, %0" \ 108 : "=r" (__r) : "r" (va), "n" (asi)); \ 109 __r; \ 110}) 111 112#define lduba(va, asi) LD_GENERIC(va, asi, lduba, u_char) 113#define lduha(va, asi) LD_GENERIC(va, asi, lduha, u_short) 114#define lduwa(va, asi) LD_GENERIC(va, asi, lduwa, u_int) 115#define ldxa(va, asi) LD_GENERIC(va, asi, ldxa, u_long) 116 117#define STNC_GEN(tp, o) \ 118 static __inline void \ 119 o ## _nc(caddr_t va, int asi, tp val) \ 120 { \ 121 __asm __volatile("wr %2, 0, %%asi;" #o " %0, [%1] %%asi"\ 122 : : "r" (val), "r" (va), "r" (asi)); \ 123 } 124 125STNC_GEN(u_char, stba); 126STNC_GEN(u_short, stha); 127STNC_GEN(u_int, stwa); 128STNC_GEN(u_long, stxa); 129 130#define ST_GENERIC(va, asi, val, op) \ 131 __asm __volatile(#op " %0, [%1] %2" \ 132 : : "r" (val), "r" (va), "n" (asi)); \ 133 134#define stba(va, asi, val) ST_GENERIC(va, asi, val, stba) 135#define stha(va, asi, val) ST_GENERIC(va, asi, val, stha) 136#define stwa(va, asi, val) ST_GENERIC(va, asi, val, stwa) 137#define stxa(va, asi, val) ST_GENERIC(va, asi, val, stxa) 138 139/* 140 * Attempt to read from addr, val. If a Data Access Error trap happens, 141 * they return -1 and the contents of val is undefined. A return of 0 142 * means no trap happened, and the contents of val is valid. 143 */ 144int fasword8(u_long asi, void *addr, uint8_t *val); 145int fasword16(u_long asi, void *addr, uint16_t *val); 146int fasword32(u_long asi, void *addr, uint32_t *val); 147 148#define membar(mask) do { \ 149 __asm __volatile("membar %0" : : "n" (mask) : "memory"); \ 150} while (0) 151 152#define rd(name) ({ \ 153 uint64_t __sr; \ 154 __asm __volatile("rd %%" #name ", %0" : "=r" (__sr) :); \ 155 __sr; \ 156}) 157 158#define wr(name, val, xor) do { \ 159 __asm __volatile("wr %0, %1, %%" #name \ 160 : : "r" (val), "rI" (xor)); \ 161} while (0) 162 163#define rdpr(name) ({ \ 164 uint64_t __pr; \ 165 __asm __volatile("rdpr %%" #name", %0" : "=r" (__pr) :); \ 166 __pr; \ 167}) 168 169#define wrpr(name, val, xor) do { \ 170 __asm __volatile("wrpr %0, %1, %%" #name \ 171 : : "r" (val), "rI" (xor)); \ 172} while (0) 173 174/* 175 * Macro intended to be used instead of wr(asr23, val, xor) for writing to 176 * the TICK_CMPR register in order to avoid a bug in BlackBird CPUs that 177 * can cause these writes to fail under certain condidtions which in turn 178 * causes the hardclock to stop. The workaround is to perform the write 179 * at the beginning of an I-Cache line directly followed by a dummy read. 180 */ 181#define wrtickcmpr(val, xor) ({ \ 182 __asm __volatile( \ 183 " ba,pt %%xcc, 1f ; " \ 184 " nop ; " \ 185 " .align 64 ; " \ 186 "1: wr %0, %1, %%asr23 ; " \ 187 " rd %%asr23, %%g0 ; " \ 188 : : "r" (val), "rI" (xor)); \ 189}) 190 191static __inline void 192breakpoint(void) 193{ 194 __asm __volatile("ta %%xcc, 1" : :); 195} 196 197static __inline register_t 198intr_disable(void) 199{ 200 u_long s; 201 202 s = rdpr(pstate); 203 wrpr(pstate, s & ~PSTATE_IE, 0); 204 return (s); 205} 206#define intr_restore(s) wrpr(pstate, (s), 0) 207 208/* 209 * In some places, it is required that the store is directly followed by a 210 * membar #Sync. Don't trust the compiler to not insert instructions in 211 * between. We also need to disable interrupts completely. 212 */ 213#define stxa_sync(va, asi, val) do { \ 214 u_long s; \ 215 s = intr_disable(); \ 216 __asm __volatile("stxa %0, [%1] %2; membar #Sync" \ 217 : : "r" (val), "r" (va), "n" (asi)); \ 218 intr_restore(s); \ 219} while (0) 220 221void ascopy(u_long asi, vm_offset_t src, vm_offset_t dst, size_t len); 222void ascopyfrom(u_long sasi, vm_offset_t src, caddr_t dst, size_t len); 223void ascopyto(caddr_t src, u_long dasi, vm_offset_t dst, size_t len); 224void aszero(u_long asi, vm_offset_t dst, size_t len); 225 226/* 227 * Ultrasparc II doesn't implement popc in hardware. Suck. 228 */ 229#if 0 230#define HAVE_INLINE_FFS 231/* 232 * See page 202 of the SPARC v9 Architecture Manual. 233 */ 234static __inline int 235ffs(int mask) 236{ 237 int result; 238 int neg; 239 int tmp; 240 241 __asm __volatile( 242 " neg %3, %1 ; " 243 " xnor %3, %1, %2 ; " 244 " popc %2, %0 ; " 245 " movrz %3, %%g0, %0 ; " 246 : "=r" (result), "=r" (neg), "=r" (tmp) : "r" (mask)); 247 return (result); 248} 249#endif 250 251#undef LDNC_GEN 252#undef STNC_GEN 253 254#endif /* !_MACHINE_CPUFUNC_H_ */ 255