bus_machdep.c revision 298635
1/*- 2 * Copyright (c) 2014 Andrew Turner 3 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 4 * All rights reserved. 5 * 6 * Portions of this software were developed by SRI International and the 7 * University of Cambridge Computer Laboratory under DARPA/AFRL contract 8 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 9 * 10 * Portions of this software were developed by the University of Cambridge 11 * Computer Laboratory as part of the CTSRD Project, with support from the 12 * UK Higher Education Innovation Fund (HEIF). 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36#include "opt_platform.h" 37 38#include <sys/param.h> 39__FBSDID("$FreeBSD: head/sys/riscv/riscv/bus_machdep.c 298635 2016-04-26 12:45:01Z br $"); 40 41#include <vm/vm.h> 42#include <vm/pmap.h> 43 44#include <machine/bus.h> 45 46uint8_t generic_bs_r_1(void *, bus_space_handle_t, bus_size_t); 47uint16_t generic_bs_r_2(void *, bus_space_handle_t, bus_size_t); 48uint32_t generic_bs_r_4(void *, bus_space_handle_t, bus_size_t); 49uint64_t generic_bs_r_8(void *, bus_space_handle_t, bus_size_t); 50 51void generic_bs_rm_1(void *, bus_space_handle_t, bus_size_t, uint8_t *, 52 bus_size_t); 53void generic_bs_rm_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, 54 bus_size_t); 55void generic_bs_rm_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, 56 bus_size_t); 57void generic_bs_rm_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, 58 bus_size_t); 59 60void generic_bs_rr_1(void *, bus_space_handle_t, bus_size_t, uint8_t *, 61 bus_size_t); 62void generic_bs_rr_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, 63 bus_size_t); 64void generic_bs_rr_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, 65 bus_size_t); 66void generic_bs_rr_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, 67 bus_size_t); 68 69void generic_bs_w_1(void *, bus_space_handle_t, bus_size_t, uint8_t); 70void generic_bs_w_2(void *, bus_space_handle_t, bus_size_t, uint16_t); 71void generic_bs_w_4(void *, bus_space_handle_t, bus_size_t, uint32_t); 72void generic_bs_w_8(void *, bus_space_handle_t, bus_size_t, uint64_t); 73 74void generic_bs_wm_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *, 75 bus_size_t); 76void generic_bs_wm_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 77 bus_size_t); 78void generic_bs_wm_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 79 bus_size_t); 80void generic_bs_wm_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 81 bus_size_t); 82 83void generic_bs_wr_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *, 84 bus_size_t); 85void generic_bs_wr_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 86 bus_size_t); 87void generic_bs_wr_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 88 bus_size_t); 89void generic_bs_wr_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 90 bus_size_t); 91 92static int 93generic_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flags, 94 bus_space_handle_t *bshp) 95{ 96 void *va; 97 98 va = pmap_mapdev(bpa, size); 99 if (va == NULL) 100 return (ENOMEM); 101 *bshp = (bus_space_handle_t)va; 102 return (0); 103} 104 105static void 106generic_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size) 107{ 108 109 pmap_unmapdev(bsh, size); 110} 111 112static void 113generic_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset, 114 bus_size_t size, int flags) 115{ 116} 117 118static int 119generic_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset, 120 bus_size_t size, bus_space_handle_t *nbshp) 121{ 122 123 *nbshp = bsh + offset; 124 return (0); 125} 126 127struct bus_space memmap_bus = { 128 /* cookie */ 129 .bs_cookie = NULL, 130 131 /* mapping/unmapping */ 132 .bs_map = generic_bs_map, 133 .bs_unmap = generic_bs_unmap, 134 .bs_subregion = generic_bs_subregion, 135 136 /* allocation/deallocation */ 137 .bs_alloc = NULL, 138 .bs_free = NULL, 139 140 /* barrier */ 141 .bs_barrier = generic_bs_barrier, 142 143 /* read single */ 144 .bs_r_1 = generic_bs_r_1, 145 .bs_r_2 = generic_bs_r_2, 146 .bs_r_4 = generic_bs_r_4, 147 .bs_r_8 = generic_bs_r_8, 148 149 /* read multiple */ 150 .bs_rm_1 = NULL, 151 .bs_rm_2 = NULL, 152 .bs_rm_4 = NULL, 153 .bs_rm_8 = NULL, 154 155 /* write single */ 156 .bs_w_1 = generic_bs_w_1, 157 .bs_w_2 = generic_bs_w_2, 158 .bs_w_4 = generic_bs_w_4, 159 .bs_w_8 = generic_bs_w_8, 160 161 /* write multiple */ 162 .bs_wm_1 = NULL, 163 .bs_wm_2 = NULL, 164 .bs_wm_4 = NULL, 165 .bs_wm_8 = NULL, 166 167 /* write region */ 168 .bs_wr_1 = NULL, 169 .bs_wr_2 = NULL, 170 .bs_wr_4 = NULL, 171 .bs_wr_8 = NULL, 172 173 /* set multiple */ 174 .bs_sm_1 = NULL, 175 .bs_sm_2 = NULL, 176 .bs_sm_4 = NULL, 177 .bs_sm_8 = NULL, 178 179 /* set region */ 180 .bs_sr_1 = NULL, 181 .bs_sr_2 = NULL, 182 .bs_sr_4 = NULL, 183 .bs_sr_8 = NULL, 184 185 /* copy */ 186 .bs_c_1 = NULL, 187 .bs_c_2 = NULL, 188 .bs_c_4 = NULL, 189 .bs_c_8 = NULL, 190 191 /* read single stream */ 192 .bs_r_1_s = NULL, 193 .bs_r_2_s = NULL, 194 .bs_r_4_s = NULL, 195 .bs_r_8_s = NULL, 196 197 /* read multiple stream */ 198 .bs_rm_1_s = NULL, 199 .bs_rm_2_s = NULL, 200 .bs_rm_4_s = NULL, 201 .bs_rm_8_s = NULL, 202 203 /* read region stream */ 204 .bs_rr_1_s = NULL, 205 .bs_rr_2_s = NULL, 206 .bs_rr_4_s = NULL, 207 .bs_rr_8_s = NULL, 208 209 /* write single stream */ 210 .bs_w_1_s = NULL, 211 .bs_w_2_s = NULL, 212 .bs_w_4_s = NULL, 213 .bs_w_8_s = NULL, 214 215 /* write multiple stream */ 216 .bs_wm_1_s = NULL, 217 .bs_wm_2_s = NULL, 218 .bs_wm_4_s = NULL, 219 .bs_wm_8_s = NULL, 220 221 /* write region stream */ 222 .bs_wr_1_s = NULL, 223 .bs_wr_2_s = NULL, 224 .bs_wr_4_s = NULL, 225 .bs_wr_8_s = NULL, 226}; 227 228#ifdef FDT 229bus_space_tag_t fdtbus_bs_tag = &memmap_bus; 230#endif 231