bus_machdep.c revision 295041 
1/*-
2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * Portions of this software were developed by SRI International and the
6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Portions of this software were developed by the University of Cambridge
10 * Computer Laboratory as part of the CTSRD Project, with support from the
11 * UK Higher Education Innovation Fund (HEIF).
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 *    notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 *    notice, this list of conditions and the following disclaimer in the
20 *    documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
34
35#include "opt_platform.h"
36
37#include <sys/param.h>
38__FBSDID("$FreeBSD: head/sys/riscv/riscv/bus_machdep.c 295041 2016-01-29 15:12:31Z br $");
39
40#include <vm/vm.h>
41#include <vm/pmap.h>
42
43#include <machine/bus.h>
44
45struct bus_space memmap_bus = {
46	/* cookie */
47	.bs_cookie = NULL,
48
49	/* mapping/unmapping */
50	.bs_map = NULL,
51	.bs_unmap = NULL,
52	.bs_subregion = NULL,
53
54	/* allocation/deallocation */
55	.bs_alloc = NULL,
56	.bs_free = NULL,
57
58	/* barrier */
59	.bs_barrier = NULL,
60
61	/* read single */
62	.bs_r_1 = NULL,
63	.bs_r_2 = NULL,
64	.bs_r_4 = NULL,
65	.bs_r_8 = NULL,
66
67	/* read multiple */
68	.bs_rm_1 = NULL,
69	.bs_rm_2 = NULL,
70	.bs_rm_4 = NULL,
71	.bs_rm_8 = NULL,
72
73	/* write single */
74	.bs_w_1 = NULL,
75	.bs_w_2 = NULL,
76	.bs_w_4 = NULL,
77	.bs_w_8 = NULL,
78
79	/* write multiple */
80	.bs_wm_1 = NULL,
81	.bs_wm_2 = NULL,
82	.bs_wm_4 = NULL,
83	.bs_wm_8 = NULL,
84
85	/* write region */
86	.bs_wr_1 = NULL,
87	.bs_wr_2 = NULL,
88	.bs_wr_4 = NULL,
89	.bs_wr_8 = NULL,
90
91	/* set multiple */
92	.bs_sm_1 = NULL,
93	.bs_sm_2 = NULL,
94	.bs_sm_4 = NULL,
95	.bs_sm_8 = NULL,
96
97	/* set region */
98	.bs_sr_1 = NULL,
99	.bs_sr_2 = NULL,
100	.bs_sr_4 = NULL,
101	.bs_sr_8 = NULL,
102
103	/* copy */
104	.bs_c_1 = NULL,
105	.bs_c_2 = NULL,
106	.bs_c_4 = NULL,
107	.bs_c_8 = NULL,
108
109	/* read single stream */
110	.bs_r_1_s = NULL,
111	.bs_r_2_s = NULL,
112	.bs_r_4_s = NULL,
113	.bs_r_8_s = NULL,
114
115	/* read multiple stream */
116	.bs_rm_1_s = NULL,
117	.bs_rm_2_s = NULL,
118	.bs_rm_4_s = NULL,
119	.bs_rm_8_s = NULL,
120
121	/* read region stream */
122	.bs_rr_1_s = NULL,
123	.bs_rr_2_s = NULL,
124	.bs_rr_4_s = NULL,
125	.bs_rr_8_s = NULL,
126
127	/* write single stream */
128	.bs_w_1_s = NULL,
129	.bs_w_2_s = NULL,
130	.bs_w_4_s = NULL,
131	.bs_w_8_s = NULL,
132
133	/* write multiple stream */
134	.bs_wm_1_s = NULL,
135	.bs_wm_2_s = NULL,
136	.bs_wm_4_s = NULL,
137	.bs_wm_8_s = NULL,
138
139	/* write region stream */
140	.bs_wr_1_s = NULL,
141	.bs_wr_2_s = NULL,
142	.bs_wr_4_s = NULL,
143	.bs_wr_8_s = NULL,
144};
145